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CTCaer
GitHub Repository: CTCaer/hekate
 Path: blob/master/bdk/soc/timer.h
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/*

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 * Timer/Watchdog driver for Tegra X1

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 *

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 * Copyright (c) 2019 CTCaer

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms and conditions of the GNU General Public License,

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 * version 2, as published by the Free Software Foundation.

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 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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 * more details.

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 *

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 * You should have received a copy of the GNU General Public License

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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

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 */

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#ifndef _TIMER_H_

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#define _TIMER_H_

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#include <utils/types.h>

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// TMR registers.

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#define TIMERUS_CNTR_1US   (0x10 + 0x0)

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#define TIMERUS_USEC_CFG   (0x10 + 0x4)

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#define TIMER_TMR8_TMR_PTV 0x78

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#define TIMER_TMR9_TMR_PTV 0x80

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#define  TIMER_PER_EN       BIT(30)

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#define  TIMER_EN           BIT(31)

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#define TIMER_TMR8_TMR_PCR 0x7C

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#define TIMER_TMR9_TMR_PCR 0x8C

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#define  TIMER_INTR_CLR     BIT(30)

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// WDT registers.

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#define TIMER_WDT4_CONFIG         (0x100 + 0x80)

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#define  TIMER_SRC(TMR)    ((TMR) & 0xF)

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#define  TIMER_PER(PER)    (((PER) & 0xFF) << 4)

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#define  TIMER_IRQENABL_EN BIT(12)

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#define  TIMER_FIQENABL_EN BIT(13)

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#define  TIMER_SYSRESET_EN BIT(14)

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#define  TIMER_PMCRESET_EN BIT(15)

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#define TIMER_WDT4_COMMAND        (0x108 + 0x80)

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#define  TIMER_START_CNT   BIT(0)

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#define  TIMER_CNT_DISABLE BIT(1)

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#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)

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#define  TIMER_MAGIC_PTRN  0xC45A

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u32  get_tmr_us();

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u32  get_tmr_ms();

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u32  get_tmr_s();

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void usleep(u32 us);

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void msleep(u32 ms);

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#define ILOOP(is) ((is) / 3)

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void isleep(u32 is);

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void timer_usleep(u32 us);

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void watchdog_start(u32 us, u32 mode);

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void watchdog_end();

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void watchdog_handle();

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bool watchdog_fired();

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#endif

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