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CTCaer
GitHub Repository: CTCaer/hekate
 Path: blob/master/bdk/storage/sdmmc_t210.h
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/*

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 * Copyright (c) 2018 naehrwert

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 * Copyright (c) 2018-2025 CTCaer

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms and conditions of the GNU General Public License,

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 * version 2, as published by the Free Software Foundation.

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 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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 * more details.

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 *

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 * You should have received a copy of the GNU General Public License

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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

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 */

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#ifndef _SDMMC_T210_H_

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#define _SDMMC_T210_H_

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#include <assert.h>

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#include <utils/types.h>

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#define SDHCI_TEGRA_TUNING_TAP_HW_UPDATED BIT(17)

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#define SDHCI_TEGRA_DLLCAL_CALIBRATE      BIT(31)

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#define SDHCI_TEGRA_DLLCAL_ACTIVE         BIT(31)

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#define SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD  BIT(31)

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#define SDHCI_TEGRA_PADCTRL_VREF_SEL_MASK 0xF

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#define SDHCI_TEGRA_AUTOCAL_SLW_OVERRIDE  BIT(28)

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#define SDHCI_TEGRA_AUTOCAL_ENABLE        BIT(29)

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#define SDHCI_TEGRA_AUTOCAL_START         BIT(31)

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#define SDHCI_TEGRA_AUTOCAL_ACTIVE        BIT(31)

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typedef struct _t210_sdmmc_t

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{

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/*  0x00 */ vu32 sysad;  // sdma system address.

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/*  0x04 */ vu16 blksize;

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/*  0x06 */ vu16 blkcnt;

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/*  0x08 */ vu32 argument;

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/*  0x0C */ vu16 trnmod;

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/*  0x0E */ vu16 cmdreg;

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/*  0x10 */ vu32 rspreg[4];

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/*  0x20 */ vu32 bdata; // Buffer data port.

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/*  0x24 */ vu32 prnsts;

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/*  0x28 */ vu8  hostctl;

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/*  0x29 */ vu8  pwrcon;

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/*  0x2A */ vu8  blkgap;

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/*  0x2B */ vu8  wakcon;

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/*  0x2C */ vu16 clkcon;

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/*  0x2E */ vu8  timeoutcon;

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/*  0x2F */ vu8  swrst;

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/*  0x30 */ vu16 norintsts;   // Normal interrupt status.

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/*  0x32 */ vu16 errintsts;   // Error  interrupt status.

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/*  0x34 */ vu16 norintstsen; // Enable irq status.

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/*  0x36 */ vu16 errintstsen; // Enable irq status.

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/*  0x38 */ vu16 norintsigen; // Enable irq signal to LIC/GIC.

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/*  0x3A */ vu16 errintsigen; // Enable irq signal to LIC/GIC.

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/*  0x3C */ vu16 acmd12errsts;

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/*  0x3E */ vu16 hostctl2;

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// CAP0: 0x376CD08C.

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//       12 MHz timeout clock. 208 MHz max base clock. 512B max block length. 8-bit support.

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//       ADMA2 support. HS25 support. SDMA support. No suspend/resume support. 3.3/3.0/1.8V support.

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//       64bit addressing for V3/V4 support. Async IRQ support. All report as removable.

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/*  0x40 */ vu32 capareg;

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// CAP1: 0x10002F73.

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//       SDR50/SDR104 support. No DDR50 support. Drive A/B/C/D support.

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//       Timer re-tuning info from other source. SDR50 requires re-tuning.

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//       Tuning uses timer and transfers should be 4MB limited.

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//       ADMA3 not supported. 1.8V VDD2 supported.

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/*  0x44 */ vu32 capareg_hi;

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/*  0x48 */ vu32 maxcurr;      // Get information by another method. Can be overriden via maxcurrover and maxcurrover_hi.

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/*  0x4C */ vu32 maxcurr_hi;

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/*  0x50 */ vu16 setacmd12err; // Force error in acmd12errsts.

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/*  0x52 */ vu16 setinterr;

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/*  0x54 */ vu8  admaerr;

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/*  0x55 */ vu8  rsvd1[3];     // 55-57 reserved.

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/*  0x58 */ vu32 admaaddr;

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/*  0x5C */ vu32 admaaddr_hi;

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/*  0x60 */ vu16 presets[11];

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/*  0x76 */ vu16 rsvd2;

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/*  0x78 */ vu32 adma3addr;

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/*  0x7C */ vu32 adma3addr_hi;

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/*  0x80 */ vu8  uhs2[124];    // 80-FB UHS-II.

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/*  0xFC */ vu16 slotintsts;

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/*  0xFE */ vu16 hcver;        // 0x303 (4.00).

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/* UHS-II range. Used for Vendor registers here */

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/* 0x100 */ vu32 venclkctl;

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/* 0x104 */ vu32 vensysswctl;

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/* 0x108 */ vu32 venerrintsts;

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/* 0x10C */ vu32 vencapover;

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/* 0x110 */ vu32 venbootctl;

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/* 0x114 */ vu32 venbootacktout;

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/* 0x118 */ vu32 venbootdattout;

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/* 0x11C */ vu32 vendebouncecnt;

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/* 0x120 */ vu32 venmiscctl;

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/* 0x124 */ vu32 maxcurrover;

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/* 0x128 */ vu32 maxcurrover_hi;

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/* 0x12C */ vu32 unk0[32]; // 0x12C

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/* 0x1AC */ vu32 veniotrimctl;

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/* 0x1B0 */ vu32 vendllcalcfg;

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/* 0x1B4 */ vu32 vendllctl0;

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/* 0x1B8 */ vu32 vendllctl1;

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/* 0x1BC */ vu32 vendllcalcfgsts;

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/* 0x1C0 */ vu32 ventunctl0;

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/* 0x1C4 */ vu32 ventunctl1;

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/* 0x1C8 */ vu32 ventunsts0;

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/* 0x1CC */ vu32 ventunsts1;

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/* 0x1D0 */ vu32 venclkgatehystcnt;

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/* 0x1D4 */ vu32 venpresetval0;

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/* 0x1D8 */ vu32 venpresetval1;

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/* 0x1DC */ vu32 venpresetval2;

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/* 0x1E0 */ vu32 sdmemcmppadctl;

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/* 0x1E4 */ vu32 autocalcfg;

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/* 0x1E8 */ vu32 autocalintval;

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/* 0x1EC */ vu32 autocalsts;

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/* 0x1F0 */ vu32 iospare;

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/* 0x1F4 */ vu32 mcciffifoctl;

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/* 0x1F8 */ vu32 timeoutwcoal;

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} t210_sdmmc_t;

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static_assert(sizeof(t210_sdmmc_t) == 0x1FC, "T210 SDMMC REG size is wrong!");

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#endif

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