CoCalc -- LoongArch64Emitter.cpp

GitHub Repository: hrydgard/ppsspp
Path: blob/master/Common/LoongArch64Emitter.cpp
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// Copyright (c) 2025- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#include <algorithm>
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#include <cstring>
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#include "Common/BitScan.h"
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#include "Common/CPUDetect.h"
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#include "Common/LoongArch64Emitter.h"
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namespace LoongArch64Gen {
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enum class Opcode32 {
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    // Note: invalid, just used for FixupBranch.
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    ZERO = 0x0,
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    ADD_W = 0x00100000,
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    ADD_D = 0x00108000,
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    SUB_W = 0x00110000,
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    SUB_D = 0x00118000,
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    ADDI_W = 0x02800000,
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    ADDI_D = 0x02c00000,
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    ADDU16I_D = 0x10000000,
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    ALSL_W = 0x00040000,
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    ALSL_D = 0X002c0000,
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    ALSL_WU = 0x00060000,
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    LU12I_W = 0x14000000,
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    LU32I_D = 0x16000000,
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    LU52I_D = 0x03000000,
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    SLT = 0x00120000,
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    SLTU = 0x00128000,
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    SLTI = 0x02000000,
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    SLTUI = 0x02400000,
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    PCADDI = 0x18000000,
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    PCADDU12I = 0x1c000000,
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    PCADDU18I = 0x1e000000,
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    PCALAU12I = 0x1a000000,
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    AND = 0x00148000,
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    OR = 0x00150000,
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    NOR = 0x00140000,
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    XOR = 0x00158000,
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    ANDN = 0x00168000,
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    ORN = 0x00160000,
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    ANDI = 0x03400000,
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    ORI = 0x03800000,
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    XORI = 0x03c00000,
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    MUL_W = 0x001c0000,
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    MULH_W = 0x001c8000,
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    MULH_WU = 0x001d0000,
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    MUL_D = 0x001d8000,
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    MULH_D = 0x001e0000,
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    MULH_DU = 0x001e8000,
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    MULW_D_W = 0x001f0000,
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    MULW_D_WU = 0x001f8000,
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    DIV_W = 0x00200000,
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    MOD_W = 0x00208000,
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    DIV_WU = 0x00210000,
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    MOD_WU = 0x00218000,
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    DIV_D = 0x00220000,
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    MOD_D = 0x00228000,
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    DIV_DU = 0x00230000,
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    MOD_DU = 0x00238000,
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    SLL_W = 0x00170000,
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    SRL_W = 0x00178000,
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    SRA_W = 0x00180000,
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    ROTR_W = 0x001b0000,
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    SLLI_W = 0x00408000,
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    SRLI_W = 0x00448000,
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    SRAI_W = 0x00488000,
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    ROTRI_W = 0x004c8000,
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    SLL_D = 0x00188000,
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    SRL_D = 0x00190000,
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    SRA_D = 0x00198000,
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    ROTR_D = 0x001b8000,
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    SLLI_D = 0x00410000,
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    SRLI_D = 0x00450000,
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    SRAI_D = 0x00490000,
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    ROTRI_D = 0x004d0000,
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    EXT_W_B = 0x00005c00,
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    EXT_W_H = 0x00005800,
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    CLO_W = 0x00001000,
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    CLO_D = 0x00002000,
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    CLZ_W = 0x00001400,
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    CLZ_D = 0x00002400,
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    CTO_W = 0x00001800,
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    CTO_D = 0x00002800,
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    CTZ_W = 0x00001c00,
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    CTZ_D = 0x00002c00,
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    BYTEPICK_W = 0x00080000,
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    BYTEPICK_D = 0x000c0000,
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    REVB_2H = 0x00003000,
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    REVB_4H = 0x00003400,
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    REVB_2W = 0x00003800,
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    REVB_D = 0x00003c00,
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    BITREV_4B = 0x00004800,
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    BITREV_8B = 0x00004c00,
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    BITREV_W = 0x00005000,
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    BITREV_D = 0x00005400,
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    BSTRINS_W = 0x00600000,
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    BSTRINS_D = 0x00800000,
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    BSTRPICK_W = 0x00608000,
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    BSTRPICK_D = 0x00c00000,
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    MASKEQZ = 0x00130000,
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    MASKNEZ = 0x00138000,
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    BEQ = 0x58000000,
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    BNE = 0x5c000000,
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    BLT = 0x60000000,
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    BGE = 0x64000000,
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    BLTU = 0x68000000,
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    BGEU = 0x6c000000,
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    BEQZ = 0x40000000,
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    BNEZ = 0x44000000,
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    B = 0x50000000,
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    BL = 0x54000000,
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    JIRL = 0x4c000000,
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    LD_B = 0x28000000,
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    LD_H = 0x28400000,
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    LD_W = 0x28800000,
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    LD_D = 0x28c00000,
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    LD_BU = 0x2a000000,
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    LD_HU = 0x2a400000,
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    LD_WU = 0x2a800000,
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    ST_B = 0x29000000,
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    ST_H = 0x29400000,
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    ST_W = 0x29800000,
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    ST_D = 0x29c00000,
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    LDX_B = 0x38000000,
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    LDX_H = 0x38040000,
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    LDX_W = 0x38080000,
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    LDX_D = 0x380c0000,
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    LDX_BU = 0x38200000,
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    LDX_HU = 0x38240000,
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    LDX_WU = 0x38280000,
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    STX_B = 0x38100000,
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    STX_H = 0x38140000,
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    STX_W = 0x38180000,
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    STX_D = 0x381c0000,
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    LDPTR_W = 0x24000000,
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    LDPTR_D = 0x26000000,
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    STPTR_W = 0x25000000,
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    STPTR_D = 0x27000000,
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    PRELD = 0x2ac00000,
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    PRELDX = 0x382c0000,
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    LDGT_B = 0x38780000,
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    LDGT_H = 0x38788000,
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    LDGT_W = 0x38790000,
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    LDGT_D = 0x38798000,
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    LDLE_B = 0x387a0000,
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    LDLE_H = 0x387a8000,
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    LDLE_W = 0x387b0000,
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    LDLE_D = 0x387b8000,
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    STGT_B = 0x387c0000,
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    STGT_H = 0x387c8000,
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    STGT_W = 0x387d0000,
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    STGT_D = 0x387d8000,
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    STLE_B = 0x387e0000,
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    STLE_H = 0x387e8000,
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    STLE_W = 0x387f0000,
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    STLE_D = 0x387f8000,
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    AMSWAP_W = 0x38600000,
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    AMSWAP_DB_W = 0x38690000,
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    AMSWAP_D = 0x38608000,
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    AMSWAP_DB_D = 0x38698000,
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    AMADD_W = 0x38610000,
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    AMADD_DB_W = 0x386a0000,
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    AMADD_D = 0x38618000,
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    AMADD_DB_D = 0x386a8000,
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    AMAND_W = 0x38620000,
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    AMAND_DB_W = 0x386b0000,
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    AMAND_D = 0x38628000,
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    AMAND_DB_D = 0x386b8000,
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    AMOR_W = 0x38630000,
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    AMOR_DB_W = 0x386c0000,
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    AMOR_D = 0x38638000,
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    AMOR_DB_D = 0x386c8000,
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    AMXOR_W = 0x38640000,
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    AMXOR_DB_W = 0x386d0000,
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    AMXOR_D = 0x38648000,
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    AMXOR_DB_D = 0x386d8000,
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    AMMAX_W = 0x38650000,
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    AMMAX_DB_W = 0x386e0000,
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    AMMAX_D = 0x38658000,
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    AMMAX_DB_D = 0x386e8000,
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    AMMIN_W = 0x38660000,
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    AMMIN_DB_W = 0x386f0000,
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    AMMIN_D = 0x38668000,
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    AMMIN_DB_D = 0x386f8000,
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    AMMAX_WU = 0x38670000,
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    AMMAX_DB_WU = 0x38700000,
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    AMMAX_DU = 0x38678000,
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    AMMAX_DB_DU = 0x38708000,
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    AMMIN_WU = 0x38680000,
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    AMMIN_DB_WU = 0x38710000,
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    AMMIN_DU = 0x38688000,
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    AMMIN_DB_DU = 0x38718000,
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    AMSWAP_B = 0x385c0000,
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    AMSWAP_DB_B = 0x385e0000,
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    AMSWAP_H = 0x385c8000,
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    AMSWAP_DB_H = 0x385e8000,
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    AMADD_B = 0x385d0000,
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    AMADD_DB_B = 0x385f0000,
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    AMADD_H = 0x385d8000,
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    AMADD_DB_H = 0x385f8000,
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    AMCAS_B = 0x38580000,
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    AMCAS_DB_B = 0x385a0000,
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    AMCAS_H = 0x38588000,
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    AMCAS_DB_H = 0x385a8000,
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    AMCAS_W = 0x38590000,
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    AMCAS_DB_W = 0x385b0000,
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    AMCAS_D = 0x38598000,
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    AMCAS_DB_D = 0x38698000,
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    CRC_W_B_W = 0x00240000,
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    CRC_W_H_W = 0x00248000,
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    CRC_W_W_W = 0x00250000,
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    CRC_W_D_W = 0x00258000,
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    CRCC_W_B_W = 0x00260000,
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    CRCC_W_H_W = 0x00268000,
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    CRCC_W_W_W = 0x00270000,
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    CRCC_W_D_W = 0x00278000,
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    SYSCALL = 0x002b0000,
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    BREAK = 0x002a0000,
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    ASRTLE_D = 0x00010000,
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    ASRTGT_D = 0x00018000,
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    RDTIMEL_W = 0x00006000,
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    RDTIMEH_W = 0x00006400,
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    RDTIME_D = 0x00006800,
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    CPUCFG = 0x00006c00,
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    FADD_S = 0x01008000,
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    FADD_D = 0x01010000,
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    FSUB_S = 0x01028000,
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    FSUB_D = 0x01030000,
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    FMUL_S = 0x01048000,
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    FMUL_D = 0x01050000,
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    FDIV_S = 0x01068000,
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    FDIV_D = 0x01070000,
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    FMADD_S = 0x08100000,
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    FMADD_D = 0x08200000,
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    FMSUB_S = 0x08500000,
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    FMSUB_D = 0x08600000,
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    FNMADD_S= 0x08900000,
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    FNMADD_D= 0x08a00000,
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    FNMSUB_S= 0x08d00000,
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    FNMSUB_D= 0x08e00000,
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    FMAX_S = 0x01088000,
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    FMAX_D = 0x01090000,
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    FMIN_S = 0x010a8000,
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    FMIN_D = 0x010b0000,
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    FMAXA_S = 0x010c8000,
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    FMAXA_D = 0x010d0000,
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    FMINA_S = 0x010e8000,
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    FMINA_D = 0x010f0000,
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    FABS_S = 0x01140400,
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    FABS_D = 0x01140800,
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    FNEG_S = 0x01141400,
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    FNEG_D = 0x01141800,
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    FSQRT_S = 0x01144400,
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    FSQRT_D = 0x01144800,
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    FRECIP_S = 0x01145400,
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    FRECIP_D = 0x01145800,
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    FRSQRT_S = 0x01146400,
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    FRSQRT_D = 0x01146800,
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    FSCALEB_S = 0x01108000,
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    FSCALEB_D = 0x01110000,
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    FLOGB_S = 0x01142400,
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    FLOGB_D = 0x01142800,
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    FCOPYSIGN_S = 0x01128000,
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    FCOPYSIGN_D = 0x01130000,
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    FCLASS_S = 0x01143400,
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    FCLASS_D = 0x01143800,
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    FRECIPE_S = 0x01147400,
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    FRECIPE_D = 0x01147800,
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    FRSQRTE_S = 0x01148400,
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    FRSQRTE_D = 0x01148800,
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    FCMP_COND_S = 0x0c100000,
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    FCMP_COND_D = 0x0c200000,
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    FCVT_S_D = 0x01191800,
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    FCVT_D_S = 0x01192400,
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    FFINT_S_W = 0x011d1000,
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    FFINT_S_L = 0x011d1800,
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    FFINT_D_W = 0x011d2000,
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    FFINT_D_L = 0x011d2800,
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    FTINT_W_S = 0x011b0400,
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    FTINT_W_D = 0x011b0800,
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    FTINT_L_S = 0x011b2400,
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    FTINT_L_D = 0x011b2800,
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    FTINTRM_W_S = 0x011a0400,
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    FTINTRM_W_D = 0x011a0800,
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    FTINTRM_L_S = 0x011a2400,
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    FTINTRM_L_D = 0x011a2800,
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    FTINTRP_W_S = 0x011a4400,
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    FTINTRP_W_D = 0x011a4800,
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    FTINTRP_L_S = 0x011a6400,
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    FTINTRP_L_D = 0x011a6800,
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    FTINTRZ_W_S = 0x011a8400,
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    FTINTRZ_W_D = 0x011a8800,
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    FTINTRZ_L_S = 0x011aa400,
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    FTINTRZ_L_D = 0x011aa800,
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    FTINTRNE_W_S = 0x011ac400,
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    FTINTRNE_W_D = 0x011ac800,
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    FTINTRNE_L_S = 0x011ae400,
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    FTINTRNE_L_D = 0x011ae800,
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    FRINT_S = 0x011e4400,
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    FRINT_D = 0x011e4800,
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    FMOV_S = 0x01149400,
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    FMOV_D = 0x01149800,
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    FSEL = 0x0d000000,
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    MOVGR2FR_W = 0x0114a400,
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    MOVGR2FR_D = 0x00114a800,
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    MOVGR2FRH_W = 0x0114ac00,
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    MOVFR2GR_S = 0x0114b400,
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    MOVFR2GR_D = 0x0114b800,
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    MOVFRH2GR_S = 0x0114bc00,
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    MOVGR2FCSR = 0x0114c000,
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    MOVFCSR2GR = 0x0114c800,
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    MOVFR2CF = 0x0114d000,
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    MOVCF2FR = 0x0114d400,
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    MOVGR2CF = 0x0114d800,
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    MOVCF2GR = 0x0114dc00,
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    BCEQZ = 0x48000000,
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    BCNEZ = 0x48000100,
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    FLD_S = 0x2b000000,
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    FLD_D = 0x2b800000,
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    FST_S = 0x2b400000,
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    FST_D = 0x2bc00000,
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    FLDX_S = 0x38300000,
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    FLDX_D = 0x38340000,
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    FSTX_S = 0x38380000,
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    FSTX_D = 0x383c0000,
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417
    FLDGT_S = 0x38740000,
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    FLDGT_D = 0x38748000,
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    FLDLE_S = 0x38750000,
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    FLDLE_D = 0x38758000,
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    FSTGT_S = 0x38760000,
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    FSTGT_D = 0x38768000,
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    FSTLE_S = 0x38770000,
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    FSTLE_D = 0x38778000,
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    VFMADD_S = 0x09100000,
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    VFMADD_D = 0x09200000,
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    VFMSUB_S = 0x09500000,
429
    VFMSUB_D = 0x09600000,
430
    VFNMADD_S = 0x09900000,
431
    VFNMADD_D = 0x09a00000,
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    VFNMSUB_S = 0x09d00000,
433
    VFNMSUB_D = 0x09e00000,
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    VFCMP_CAF_S = 0x0c500000,
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    VFCMP_SAF_S = 0x0c508000,
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    VFCMP_CLT_S = 0x0c510000,
437
    VFCMP_SLT_S = 0x0c518000,
438
    VFCMP_CEQ_S = 0x0c520000,
439
    VFCMP_SEQ_S = 0x0c528000,
440
    VFCMP_CLE_S = 0x0c530000,
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    VFCMP_SLE_S = 0x0c538000,
442
    VFCMP_CUN_S = 0x0c540000,
443
    VFCMP_SUN_S = 0x0c548000,
444
    VFCMP_CULT_S = 0x0c550000,
445
    VFCMP_SULT_S = 0x0c558000,
446
    VFCMP_CUEQ_S = 0x0c560000,
447
    VFCMP_SUEQ_S = 0x0c568000,
448
    VFCMP_CULE_S = 0x0c570000,
449
    VFCMP_SULE_S = 0x0c578000,
450
    VFCMP_CNE_S = 0x0c580000,
451
    VFCMP_SNE_S = 0x0c588000,
452
    VFCMP_COR_S = 0x0c5a0000,
453
    VFCMP_SOR_S = 0x0c5a8000,
454
    VFCMP_CUNE_S = 0x0c5c0000,
455
    VFCMP_SUNE_S = 0x0c5c8000,
456
    VFCMP_CAF_D = 0x0c600000,
457
    VFCMP_SAF_D = 0x0c608000,
458
    VFCMP_CLT_D = 0x0c610000,
459
    VFCMP_SLT_D = 0x0c618000,
460
    VFCMP_CEQ_D = 0x0c620000,
461
    VFCMP_SEQ_D = 0x0c628000,
462
    VFCMP_CLE_D = 0x0c630000,
463
    VFCMP_SLE_D = 0x0c638000,
464
    VFCMP_CUN_D = 0x0c640000,
465
    VFCMP_SUN_D = 0x0c648000,
466
    VFCMP_CULT_D = 0x0c650000,
467
    VFCMP_SULT_D = 0x0c658000,
468
    VFCMP_CUEQ_D = 0x0c660000,
469
    VFCMP_SUEQ_D = 0x0c668000,
470
    VFCMP_CULE_D = 0x0c670000,
471
    VFCMP_SULE_D = 0x0c678000,
472
    VFCMP_CNE_D = 0x0c680000,
473
    VFCMP_SNE_D = 0x0c688000,
474
    VFCMP_COR_D = 0x0c6a0000,
475
    VFCMP_SOR_D = 0x0c6a8000,
476
    VFCMP_CUNE_D = 0x0c6c0000,
477
    VFCMP_SUNE_D = 0x0c6c8000,
478
    VBITSEL_V = 0x0d100000,
479
    VSHUF_B = 0x0d500000,
480
    VLD = 0x2c000000,
481
    VST = 0x2c400000,
482
    VLDREPL_D = 0x30100000,
483
    VLDREPL_W = 0x30200000,
484
    VLDREPL_H = 0x30400000,
485
    VLDREPL_B = 0x30800000,
486
    VSTELM_D = 0x31100000,
487
    VSTELM_W = 0x31200000,
488
    VSTELM_H = 0x31400000,
489
    VSTELM_B = 0x31800000,
490
    VLDX = 0x38400000,
491
    VSTX = 0x38440000,
492
    VSEQ_B = 0x70000000,
493
    VSEQ_H = 0x70008000,
494
    VSEQ_W = 0x70010000,
495
    VSEQ_D = 0x70018000,
496
    VSLE_B = 0x70020000,
497
    VSLE_H = 0x70028000,
498
    VSLE_W = 0x70030000,
499
    VSLE_D = 0x70038000,
500
    VSLE_BU = 0x70040000,
501
    VSLE_HU = 0x70048000,
502
    VSLE_WU = 0x70050000,
503
    VSLE_DU = 0x70058000,
504
    VSLT_B = 0x70060000,
505
    VSLT_H = 0x70068000,
506
    VSLT_W = 0x70070000,
507
    VSLT_D = 0x70078000,
508
    VSLT_BU = 0x70080000,
509
    VSLT_HU = 0x70088000,
510
    VSLT_WU = 0x70090000,
511
    VSLT_DU = 0x70098000,
512
    VADD_B = 0x700a0000,
513
    VADD_H = 0x700a8000,
514
    VADD_W = 0x700b0000,
515
    VADD_D = 0x700b8000,
516
    VSUB_B = 0x700c0000,
517
    VSUB_H = 0x700c8000,
518
    VSUB_W = 0x700d0000,
519
    VSUB_D = 0x700d8000,
520
    VADDWEV_H_B = 0x701e0000,
521
    VADDWEV_W_H = 0x701e8000,
522
    VADDWEV_D_W = 0x701f0000,
523
    VADDWEV_Q_D = 0x701f8000,
524
    VSUBWEV_H_B = 0x70200000,
525
    VSUBWEV_W_H = 0x70208000,
526
    VSUBWEV_D_W = 0x70210000,
527
    VSUBWEV_Q_D = 0x70218000,
528
    VADDWOD_H_B = 0x70220000,
529
    VADDWOD_W_H = 0x70228000,
530
    VADDWOD_D_W = 0x70230000,
531
    VADDWOD_Q_D = 0x70238000,
532
    VSUBWOD_H_B = 0x70240000,
533
    VSUBWOD_W_H = 0x70248000,
534
    VSUBWOD_D_W = 0x70250000,
535
    VSUBWOD_Q_D = 0x70258000,
536
    VADDWEV_H_BU = 0x702e0000,
537
    VADDWEV_W_HU = 0x702e8000,
538
    VADDWEV_D_WU = 0x702f0000,
539
    VADDWEV_Q_DU = 0x702f8000,
540
    VSUBWEV_H_BU = 0x70300000,
541
    VSUBWEV_W_HU = 0x70308000,
542
    VSUBWEV_D_WU = 0x70310000,
543
    VSUBWEV_Q_DU = 0x70318000,
544
    VADDWOD_H_BU = 0x70320000,
545
    VADDWOD_W_HU = 0x70328000,
546
    VADDWOD_D_WU = 0x70330000,
547
    VADDWOD_Q_DU = 0x70338000,
548
    VSUBWOD_H_BU = 0x70340000,
549
    VSUBWOD_W_HU = 0x70348000,
550
    VSUBWOD_D_WU = 0x70350000,
551
    VSUBWOD_Q_DU = 0x70358000,
552
    VADDWEV_H_BU_B = 0x703e0000,
553
    VADDWEV_W_HU_H = 0x703e8000,
554
    VADDWEV_D_WU_W = 0x703f0000,
555
    VADDWEV_Q_DU_D = 0x703f8000,
556
    VADDWOD_H_BU_B = 0x70400000,
557
    VADDWOD_W_HU_H = 0x70408000,
558
    VADDWOD_D_WU_W = 0x70410000,
559
    VADDWOD_Q_DU_D = 0x70418000,
560
    VSADD_B = 0x70460000,
561
    VSADD_H = 0x70468000,
562
    VSADD_W = 0x70470000,
563
    VSADD_D = 0x70478000,
564
    VSSUB_B = 0x70480000,
565
    VSSUB_H = 0x70488000,
566
    VSSUB_W = 0x70490000,
567
    VSSUB_D = 0x70498000,
568
    VSADD_BU = 0x704a0000,
569
    VSADD_HU = 0x704a8000,
570
    VSADD_WU = 0x704b0000,
571
    VSADD_DU = 0x704b8000,
572
    VSSUB_BU = 0x704c0000,
573
    VSSUB_HU = 0x704c8000,
574
    VSSUB_WU = 0x704d0000,
575
    VSSUB_DU = 0x704d8000,
576
    VHADDW_H_B = 0x70540000,
577
    VHADDW_W_H = 0x70548000,
578
    VHADDW_D_W = 0x70550000,
579
    VHADDW_Q_D = 0x70558000,
580
    VHSUBW_H_B = 0x70560000,
581
    VHSUBW_W_H = 0x70568000,
582
    VHSUBW_D_W = 0x70570000,
583
    VHSUBW_Q_D = 0x70578000,
584
    VHADDW_HU_BU = 0x70580000,
585
    VHADDW_WU_HU = 0x70588000,
586
    VHADDW_DU_WU = 0x70590000,
587
    VHADDW_QU_DU = 0x70598000,
588
    VHSUBW_HU_BU = 0x705a0000,
589
    VHSUBW_WU_HU = 0x705a8000,
590
    VHSUBW_DU_WU = 0x705b0000,
591
    VHSUBW_QU_DU = 0x705b8000,
592
    VADDA_B = 0x705c0000,
593
    VADDA_H = 0x705c8000,
594
    VADDA_W = 0x705d0000,
595
    VADDA_D = 0x705d8000,
596
    VABSD_B = 0x70600000,
597
    VABSD_H = 0x70608000,
598
    VABSD_W = 0x70610000,
599
    VABSD_D = 0x70618000,
600
    VABSD_BU = 0x70620000,
601
    VABSD_HU = 0x70628000,
602
    VABSD_WU = 0x70630000,
603
    VABSD_DU = 0x70638000,
604
    VAVG_B = 0x70640000,
605
    VAVG_H = 0x70648000,
606
    VAVG_W = 0x70650000,
607
    VAVG_D = 0x70658000,
608
    VAVG_BU = 0x70660000,
609
    VAVG_HU = 0x70668000,
610
    VAVG_WU = 0x70670000,
611
    VAVG_DU = 0x70678000,
612
    VAVGR_B = 0x70680000,
613
    VAVGR_H = 0x70688000,
614
    VAVGR_W = 0x70690000,
615
    VAVGR_D = 0x70698000,
616
    VAVGR_BU = 0x706a0000,
617
    VAVGR_HU = 0x706a8000,
618
    VAVGR_WU = 0x706b0000,
619
    VAVGR_DU = 0x706b8000,
620
    VMAX_B = 0x70700000,
621
    VMAX_H = 0x70708000,
622
    VMAX_W = 0x70710000,
623
    VMAX_D = 0x70718000,
624
    VMIN_B = 0x70720000,
625
    VMIN_H = 0x70728000,
626
    VMIN_W = 0x70730000,
627
    VMIN_D = 0x70738000,
628
    VMAX_BU = 0x70740000,
629
    VMAX_HU = 0x70748000,
630
    VMAX_WU = 0x70750000,
631
    VMAX_DU = 0x70758000,
632
    VMIN_BU = 0x70760000,
633
    VMIN_HU = 0x70768000,
634
    VMIN_WU = 0x70770000,
635
    VMIN_DU = 0x70778000,
636
    VMUL_B = 0x70840000,
637
    VMUL_H = 0x70848000,
638
    VMUL_W = 0x70850000,
639
    VMUL_D = 0x70858000,
640
    VMUH_B = 0x70860000,
641
    VMUH_H = 0x70868000,
642
    VMUH_W = 0x70870000,
643
    VMUH_D = 0x70878000,
644
    VMUH_BU = 0x70880000,
645
    VMUH_HU = 0x70888000,
646
    VMUH_WU = 0x70890000,
647
    VMUH_DU = 0x70898000,
648
    VMULWEV_H_B = 0x70900000,
649
    VMULWEV_W_H = 0x70908000,
650
    VMULWEV_D_W = 0x70910000,
651
    VMULWEV_Q_D = 0x70918000,
652
    VMULWOD_H_B = 0x70920000,
653
    VMULWOD_W_H = 0x70928000,
654
    VMULWOD_D_W = 0x70930000,
655
    VMULWOD_Q_D = 0x70938000,
656
    VMULWEV_H_BU = 0x70980000,
657
    VMULWEV_W_HU = 0x70988000,
658
    VMULWEV_D_WU = 0x70990000,
659
    VMULWEV_Q_DU = 0x70998000,
660
    VMULWOD_H_BU = 0x709a0000,
661
    VMULWOD_W_HU = 0x709a8000,
662
    VMULWOD_D_WU = 0x709b0000,
663
    VMULWOD_Q_DU = 0x709b8000,
664
    VMULWEV_H_BU_B = 0x70a00000,
665
    VMULWEV_W_HU_H = 0x70a08000,
666
    VMULWEV_D_WU_W = 0x70a10000,
667
    VMULWEV_Q_DU_D = 0x70a18000,
668
    VMULWOD_H_BU_B = 0x70a20000,
669
    VMULWOD_W_HU_H = 0x70a28000,
670
    VMULWOD_D_WU_W = 0x70a30000,
671
    VMULWOD_Q_DU_D = 0x70a38000,
672
    VMADD_B = 0x70a80000,
673
    VMADD_H = 0x70a88000,
674
    VMADD_W = 0x70a90000,
675
    VMADD_D = 0x70a98000,
676
    VMSUB_B = 0x70aa0000,
677
    VMSUB_H = 0x70aa8000,
678
    VMSUB_W = 0x70ab0000,
679
    VMSUB_D = 0x70ab8000,
680
    VMADDWEV_H_B = 0x70ac0000,
681
    VMADDWEV_W_H = 0x70ac8000,
682
    VMADDWEV_D_W = 0x70ad0000,
683
    VMADDWEV_Q_D = 0x70ad8000,
684
    VMADDWOD_H_B = 0x70ae0000,
685
    VMADDWOD_W_H = 0x70ae8000,
686
    VMADDWOD_D_W = 0x70af0000,
687
    VMADDWOD_Q_D = 0x70af8000,
688
    VMADDWEV_H_BU = 0x70b40000,
689
    VMADDWEV_W_HU = 0x70b48000,
690
    VMADDWEV_D_WU = 0x70b50000,
691
    VMADDWEV_Q_DU = 0x70b58000,
692
    VMADDWOD_H_BU = 0x70b60000,
693
    VMADDWOD_W_HU = 0x70b68000,
694
    VMADDWOD_D_WU = 0x70b70000,
695
    VMADDWOD_Q_DU = 0x70b78000,
696
    VMADDWEV_H_BU_B = 0x70bc0000,
697
    VMADDWEV_W_HU_H = 0x70bc8000,
698
    VMADDWEV_D_WU_W = 0x70bd0000,
699
    VMADDWEV_Q_DU_D = 0x70bd8000,
700
    VMADDWOD_H_BU_B = 0x70be0000,
701
    VMADDWOD_W_HU_H = 0x70be8000,
702
    VMADDWOD_D_WU_W = 0x70bf0000,
703
    VMADDWOD_Q_DU_D = 0x70bf8000,
704
    VDIV_B = 0x70e00000,
705
    VDIV_H = 0x70e08000,
706
    VDIV_W = 0x70e10000,
707
    VDIV_D = 0x70e18000,
708
    VMOD_B = 0x70e20000,
709
    VMOD_H = 0x70e28000,
710
    VMOD_W = 0x70e30000,
711
    VMOD_D = 0x70e38000,
712
    VDIV_BU = 0x70e40000,
713
    VDIV_HU = 0x70e48000,
714
    VDIV_WU = 0x70e50000,
715
    VDIV_DU = 0x70e58000,
716
    VMOD_BU = 0x70e60000,
717
    VMOD_HU = 0x70e68000,
718
    VMOD_WU = 0x70e70000,
719
    VMOD_DU = 0x70e78000,
720
    VSLL_B = 0x70e80000,
721
    VSLL_H = 0x70e88000,
722
    VSLL_W = 0x70e90000,
723
    VSLL_D = 0x70e98000,
724
    VSRL_B = 0x70ea0000,
725
    VSRL_H = 0x70ea8000,
726
    VSRL_W = 0x70eb0000,
727
    VSRL_D = 0x70eb8000,
728
    VSRA_B = 0x70ec0000,
729
    VSRA_H = 0x70ec8000,
730
    VSRA_W = 0x70ed0000,
731
    VSRA_D = 0x70ed8000,
732
    VROTR_B = 0x70ee0000,
733
    VROTR_H = 0x70ee8000,
734
    VROTR_W = 0x70ef0000,
735
    VROTR_D = 0x70ef8000,
736
    VSRLR_B = 0x70f00000,
737
    VSRLR_H = 0x70f08000,
738
    VSRLR_W = 0x70f10000,
739
    VSRLR_D = 0x70f18000,
740
    VSRAR_B = 0x70f20000,
741
    VSRAR_H = 0x70f28000,
742
    VSRAR_W = 0x70f30000,
743
    VSRAR_D = 0x70f38000,
744
    VSRLN_B_H = 0x70f48000,
745
    VSRLN_H_W = 0x70f50000,
746
    VSRLN_W_D = 0x70f58000,
747
    VSRAN_B_H = 0x70f68000,
748
    VSRAN_H_W = 0x70f70000,
749
    VSRAN_W_D = 0x70f78000,
750
    VSRLRN_B_H = 0x70f88000,
751
    VSRLRN_H_W = 0x70f90000,
752
    VSRLRN_W_D = 0x70f98000,
753
    VSRARN_B_H = 0x70fa8000,
754
    VSRARN_H_W = 0x70fb0000,
755
    VSRARN_W_D = 0x70fb8000,
756
    VSSRLN_B_H = 0x70fc8000,
757
    VSSRLN_H_W = 0x70fd0000,
758
    VSSRLN_W_D = 0x70fd8000,
759
    VSSRAN_B_H = 0x70fe8000,
760
    VSSRAN_H_W = 0x70ff0000,
761
    VSSRAN_W_D = 0x70ff8000,
762
    VSSRLRN_B_H = 0x71008000,
763
    VSSRLRN_H_W = 0x71010000,
764
    VSSRLRN_W_D = 0x71018000,
765
    VSSRARN_B_H = 0x71028000,
766
    VSSRARN_H_W = 0x71030000,
767
    VSSRARN_W_D = 0x71038000,
768
    VSSRLN_BU_H = 0x71048000,
769
    VSSRLN_HU_W = 0x71050000,
770
    VSSRLN_WU_D = 0x71058000,
771
    VSSRAN_BU_H = 0x71068000,
772
    VSSRAN_HU_W = 0x71070000,
773
    VSSRAN_WU_D = 0x71078000,
774
    VSSRLRN_BU_H = 0x71088000,
775
    VSSRLRN_HU_W = 0x71090000,
776
    VSSRLRN_WU_D = 0x71098000,
777
    VSSRARN_BU_H = 0x710a8000,
778
    VSSRARN_HU_W = 0x710b0000,
779
    VSSRARN_WU_D = 0x710b8000,
780
    VBITCLR_B = 0x710c0000,
781
    VBITCLR_H = 0x710c8000,
782
    VBITCLR_W = 0x710d0000,
783
    VBITCLR_D = 0x710d8000,
784
    VBITSET_B = 0x710e0000,
785
    VBITSET_H = 0x710e8000,
786
    VBITSET_W = 0x710f0000,
787
    VBITSET_D = 0x710f8000,
788
    VBITREV_B = 0x71100000,
789
    VBITREV_H = 0x71108000,
790
    VBITREV_W = 0x71110000,
791
    VBITREV_D = 0x71118000,
792
    VPACKEV_B = 0x71160000,
793
    VPACKEV_H = 0x71168000,
794
    VPACKEV_W = 0x71170000,
795
    VPACKEV_D = 0x71178000,
796
    VPACKOD_B = 0x71180000,
797
    VPACKOD_H = 0x71188000,
798
    VPACKOD_W = 0x71190000,
799
    VPACKOD_D = 0x71198000,
800
    VILVL_B = 0x711a0000,
801
    VILVL_H = 0x711a8000,
802
    VILVL_W = 0x711b0000,
803
    VILVL_D = 0x711b8000,
804
    VILVH_B = 0x711c0000,
805
    VILVH_H = 0x711c8000,
806
    VILVH_W = 0x711d0000,
807
    VILVH_D = 0x711d8000,
808
    VPICKEV_B = 0x711e0000,
809
    VPICKEV_H = 0x711e8000,
810
    VPICKEV_W = 0x711f0000,
811
    VPICKEV_D = 0x711f8000,
812
    VPICKOD_B = 0x71200000,
813
    VPICKOD_H = 0x71208000,
814
    VPICKOD_W = 0x71210000,
815
    VPICKOD_D = 0x71218000,
816
    VREPLVE_B = 0x71220000,
817
    VREPLVE_H = 0x71228000,
818
    VREPLVE_W = 0x71230000,
819
    VREPLVE_D = 0x71238000,
820
    VAND_V = 0x71260000,
821
    VOR_V = 0x71268000,
822
    VXOR_V = 0x71270000,
823
    VNOR_V = 0x71278000,
824
    VANDN_V = 0x71280000,
825
    VORN_V = 0x71288000,
826
    VFRSTP_B = 0x712b0000,
827
    VFRSTP_H = 0x712b8000,
828
    VADD_Q = 0x712d0000,
829
    VSUB_Q = 0x712d8000,
830
    VSIGNCOV_B = 0x712e0000,
831
    VSIGNCOV_H = 0x712e8000,
832
    VSIGNCOV_W = 0x712f0000,
833
    VSIGNCOV_D = 0x712f8000,
834
    VFADD_S = 0x71308000,
835
    VFADD_D = 0x71310000,
836
    VFSUB_S = 0x71328000,
837
    VFSUB_D = 0x71330000,
838
    VFMUL_S = 0x71388000,
839
    VFMUL_D = 0x71390000,
840
    VFDIV_S = 0x713a8000,
841
    VFDIV_D = 0x713b0000,
842
    VFMAX_S = 0x713c8000,
843
    VFMAX_D = 0x713d0000,
844
    VFMIN_S = 0x713e8000,
845
    VFMIN_D = 0x713f0000,
846
    VFMAXA_S = 0x71408000,
847
    VFMAXA_D = 0x71410000,
848
    VFMINA_S = 0x71428000,
849
    VFMINA_D = 0x71430000,
850
    VFCVT_H_S = 0x71460000,
851
    VFCVT_S_D = 0x71468000,
852
    VFFINT_S_L = 0x71480000,
853
    VFTINT_W_D = 0x71498000,
854
    VFTINTRM_W_D = 0x714a0000,
855
    VFTINTRP_W_D = 0x714a8000,
856
    VFTINTRZ_W_D = 0x714b0000,
857
    VFTINTRNE_W_D = 0x714b8000,
858
    VSHUF_H = 0x717a8000,
859
    VSHUF_W = 0x717b0000,
860
    VSHUF_D = 0x717b8000,
861
    VSEQI_B = 0x72800000,
862
    VSEQI_H = 0x72808000,
863
    VSEQI_W = 0x72810000,
864
    VSEQI_D = 0x72818000,
865
    VSLEI_B = 0x72820000,
866
    VSLEI_H = 0x72828000,
867
    VSLEI_W = 0x72830000,
868
    VSLEI_D = 0x72838000,
869
    VSLEI_BU = 0x72840000,
870
    VSLEI_HU = 0x72848000,
871
    VSLEI_WU = 0x72850000,
872
    VSLEI_DU = 0x72858000,
873
    VSLTI_B = 0x72860000,
874
    VSLTI_H = 0x72868000,
875
    VSLTI_W = 0x72870000,
876
    VSLTI_D = 0x72878000,
877
    VSLTI_BU = 0x72880000,
878
    VSLTI_HU = 0x72888000,
879
    VSLTI_WU = 0x72890000,
880
    VSLTI_DU = 0x72898000,
881
    VADDI_BU = 0x728a0000,
882
    VADDI_HU = 0x728a8000,
883
    VADDI_WU = 0x728b0000,
884
    VADDI_DU = 0x728b8000,
885
    VSUBI_BU = 0x728c0000,
886
    VSUBI_HU = 0x728c8000,
887
    VSUBI_WU = 0x728d0000,
888
    VSUBI_DU = 0x728d8000,
889
    VBSLL_V = 0x728e0000,
890
    VBSRL_V = 0x728e8000,
891
    VMAXI_B = 0x72900000,
892
    VMAXI_H = 0x72908000,
893
    VMAXI_W = 0x72910000,
894
    VMAXI_D = 0x72918000,
895
    VMINI_B = 0x72920000,
896
    VMINI_H = 0x72928000,
897
    VMINI_W = 0x72930000,
898
    VMINI_D = 0x72938000,
899
    VMAXI_BU = 0x72940000,
900
    VMAXI_HU = 0x72948000,
901
    VMAXI_WU = 0x72950000,
902
    VMAXI_DU = 0x72958000,
903
    VMINI_BU = 0x72960000,
904
    VMINI_HU = 0x72968000,
905
    VMINI_WU = 0x72970000,
906
    VMINI_DU = 0x72978000,
907
    VFRSTPI_B = 0x729a0000,
908
    VFRSTPI_H = 0x729a8000,
909
    VCLO_B = 0x729c0000,
910
    VCLO_H = 0x729c0400,
911
    VCLO_W = 0x729c0800,
912
    VCLO_D = 0x729c0c00,
913
    VCLZ_B = 0x729c1000,
914
    VCLZ_H = 0x729c1400,
915
    VCLZ_W = 0x729c1800,
916
    VCLZ_D = 0x729c1c00,
917
    VPCNT_B = 0x729c2000,
918
    VPCNT_H = 0x729c2400,
919
    VPCNT_W = 0x729c2800,
920
    VPCNT_D = 0x729c2c00,
921
    VNEG_B = 0x729c3000,
922
    VNEG_H = 0x729c3400,
923
    VNEG_W = 0x729c3800,
924
    VNEG_D = 0x729c3c00,
925
    VMSKLTZ_B = 0x729c4000,
926
    VMSKLTZ_H = 0x729c4400,
927
    VMSKLTZ_W = 0x729c4800,
928
    VMSKLTZ_D = 0x729c4c00,
929
    VMSKGEZ_B = 0x729c5000,
930
    VMSKNZ_B = 0x729c6000,
931
    VSETEQZ_V = 0x729c9800,
932
    VSETNEZ_V = 0x729c9c00,
933
    VSETANYEQZ_B = 0x729ca000,
934
    VSETANYEQZ_H = 0x729ca400,
935
    VSETANYEQZ_W = 0x729ca800,
936
    VSETANYEQZ_D = 0x729cac00,
937
    VSETALLNEZ_B = 0x729cb000,
938
    VSETALLNEZ_H = 0x729cb400,
939
    VSETALLNEZ_W = 0x729cb800,
940
    VSETALLNEZ_D = 0x729cbc00,
941
    VFLOGB_S = 0x729cc400,
942
    VFLOGB_D = 0x729cc800,
943
    VFCLASS_S = 0x729cd400,
944
    VFCLASS_D = 0x729cd800,
945
    VFSQRT_S = 0x729ce400,
946
    VFSQRT_D = 0x729ce800,
947
    VFRECIP_S = 0x729cf400,
948
    VFRECIP_D = 0x729cf800,
949
    VFRSQRT_S = 0x729d0400,
950
    VFRSQRT_D = 0x729d0800,
951
    VFRECIPE_S = 0x729d1400,
952
    VFRECIPE_D = 0x729d1800,
953
    VFRSQRTE_S = 0x729d2400,
954
    VFRSQRTE_D = 0x729d2800,
955
    VFRINT_S = 0x729d3400,
956
    VFRINT_D = 0x729d3800,
957
    VFRINTRM_S = 0x729d4400,
958
    VFRINTRM_D = 0x729d4800,
959
    VFRINTRP_S = 0x729d5400,
960
    VFRINTRP_D = 0x729d5800,
961
    VFRINTRZ_S = 0x729d6400,
962
    VFRINTRZ_D = 0x729d6800,
963
    VFRINTRNE_S = 0x729d7400,
964
    VFRINTRNE_D = 0x729d7800,
965
    VFCVTL_S_H = 0x729de800,
966
    VFCVTH_S_H = 0x729dec00,
967
    VFCVTL_D_S = 0x729df000,
968
    VFCVTH_D_S = 0x729df400,
969
    VFFINT_S_W = 0x729e0000,
970
    VFFINT_S_WU = 0x729e0400,
971
    VFFINT_D_L = 0x729e0800,
972
    VFFINT_D_LU = 0x729e0c00,
973
    VFFINTL_D_W = 0x729e1000,
974
    VFFINTH_D_W = 0x729e1400,
975
    VFTINT_W_S = 0x729e3000,
976
    VFTINT_L_D = 0x729e3400,
977
    VFTINTRM_W_S = 0x729e3800,
978
    VFTINTRM_L_D = 0x729e3c00,
979
    VFTINTRP_W_S = 0x729e4000,
980
    VFTINTRP_L_D = 0x729e4400,
981
    VFTINTRZ_W_S = 0x729e4800,
982
    VFTINTRZ_L_D = 0x729e4c00,
983
    VFTINTRNE_W_S = 0x729e5000,
984
    VFTINTRNE_L_D = 0x729e5400,
985
    VFTINT_WU_S = 0x729e5800,
986
    VFTINT_LU_D = 0x729e5c00,
987
    VFTINTRZ_WU_S = 0x729e7000,
988
    VFTINTRZ_LU_D = 0x729e7400,
989
    VFTINTL_L_S = 0x729e8000,
990
    VFTINTH_L_S = 0x729e8400,
991
    VFTINTRML_L_S = 0x729e8800,
992
    VFTINTRMH_L_S = 0x729e8c00,
993
    VFTINTRPL_L_S = 0x729e9000,
994
    VFTINTRPH_L_S = 0x729e9400,
995
    VFTINTRZL_L_S = 0x729e9800,
996
    VFTINTRZH_L_S = 0x729e9c00,
997
    VFTINTRNEL_L_S = 0x729ea000,
998
    VFTINTRNEH_L_S = 0x729ea400,
999
    VEXTH_H_B = 0x729ee000,
1000
    VEXTH_W_H = 0x729ee400,
1001
    VEXTH_D_W = 0x729ee800,
1002
    VEXTH_Q_D = 0x729eec00,
1003
    VEXTH_HU_BU = 0x729ef000,
1004
    VEXTH_WU_HU = 0x729ef400,
1005
    VEXTH_DU_WU = 0x729ef800,
1006
    VEXTH_QU_DU = 0x729efc00,
1007
    VREPLGR2VR_B = 0x729f0000,
1008
    VREPLGR2VR_H = 0x729f0400,
1009
    VREPLGR2VR_W = 0x729f0800,
1010
    VREPLGR2VR_D = 0x729f0c00,
1011
    VROTRI_B = 0x72a02000,
1012
    VROTRI_H = 0x72a04000,
1013
    VROTRI_W = 0x72a08000,
1014
    VROTRI_D = 0x72a10000,
1015
    VSRLRI_B = 0x72a42000,
1016
    VSRLRI_H = 0x72a44000,
1017
    VSRLRI_W = 0x72a48000,
1018
    VSRLRI_D = 0x72a50000,
1019
    VSRARI_B = 0x72a82000,
1020
    VSRARI_H = 0x72a84000,
1021
    VSRARI_W = 0x72a88000,
1022
    VSRARI_D = 0x72a90000,
1023
    VINSGR2VR_B = 0x72eb8000,
1024
    VINSGR2VR_H = 0x72ebc000,
1025
    VINSGR2VR_W = 0x72ebe000,
1026
    VINSGR2VR_D = 0x72ebf000,
1027
    VPICKVE2GR_B = 0x72ef8000,
1028
    VPICKVE2GR_H = 0x72efc000,
1029
    VPICKVE2GR_W = 0x72efe000,
1030
    VPICKVE2GR_D = 0x72eff000,
1031
    VPICKVE2GR_BU = 0x72f38000,
1032
    VPICKVE2GR_HU = 0x72f3c000,
1033
    VPICKVE2GR_WU = 0x72f3e000,
1034
    VPICKVE2GR_DU = 0x72f3f000,
1035
    VREPLVEI_B = 0x72f78000,
1036
    VREPLVEI_H = 0x72f7c000,
1037
    VREPLVEI_W = 0x72f7e000,
1038
    VREPLVEI_D = 0x72f7f000,
1039
    VSLLWIL_H_B = 0x73082000,
1040
    VSLLWIL_W_H = 0x73084000,
1041
    VSLLWIL_D_W = 0x73088000,
1042
    VEXTL_Q_D = 0x73090000,
1043
    VSLLWIL_HU_BU = 0x730c2000,
1044
    VSLLWIL_WU_HU = 0x730c4000,
1045
    VSLLWIL_DU_WU = 0x730c8000,
1046
    VEXTL_QU_DU = 0x730d0000,
1047
    VBITCLRI_B = 0x73102000,
1048
    VBITCLRI_H = 0x73104000,
1049
    VBITCLRI_W = 0x73108000,
1050
    VBITCLRI_D = 0x73110000,
1051
    VBITSETI_B = 0x73142000,
1052
    VBITSETI_H = 0x73144000,
1053
    VBITSETI_W = 0x73148000,
1054
    VBITSETI_D = 0x73150000,
1055
    VBITREVI_B = 0x73182000,
1056
    VBITREVI_H = 0x73184000,
1057
    VBITREVI_W = 0x73188000,
1058
    VBITREVI_D = 0x73190000,
1059
    VSAT_B = 0x73242000,
1060
    VSAT_H = 0x73244000,
1061
    VSAT_W = 0x73248000,
1062
    VSAT_D = 0x73250000,
1063
    VSAT_BU = 0x73282000,
1064
    VSAT_HU = 0x73284000,
1065
    VSAT_WU = 0x73288000,
1066
    VSAT_DU = 0x73290000,
1067
    VSLLI_B = 0x732c2000,
1068
    VSLLI_H = 0x732c4000,
1069
    VSLLI_W = 0x732c8000,
1070
    VSLLI_D = 0x732d0000,
1071
    VSRLI_B = 0x73302000,
1072
    VSRLI_H = 0x73304000,
1073
    VSRLI_W = 0x73308000,
1074
    VSRLI_D = 0x73310000,
1075
    VSRAI_B = 0x73342000,
1076
    VSRAI_H = 0x73344000,
1077
    VSRAI_W = 0x73348000,
1078
    VSRAI_D = 0x73350000,
1079
    VSRLNI_B_H = 0x73404000,
1080
    VSRLNI_H_W = 0x73408000,
1081
    VSRLNI_W_D = 0x73410000,
1082
    VSRLNI_D_Q = 0x73420000,
1083
    VSRLRNI_B_H = 0x73444000,
1084
    VSRLRNI_H_W = 0x73448000,
1085
    VSRLRNI_W_D = 0x73450000,
1086
    VSRLRNI_D_Q = 0x73460000,
1087
    VSSRLNI_B_H = 0x73484000,
1088
    VSSRLNI_H_W = 0x73488000,
1089
    VSSRLNI_W_D = 0x73490000,
1090
    VSSRLNI_D_Q = 0x734a0000,
1091
    VSSRLNI_BU_H = 0x734c4000,
1092
    VSSRLNI_HU_W = 0x734c8000,
1093
    VSSRLNI_WU_D = 0x734d0000,
1094
    VSSRLNI_DU_Q = 0x734e0000,
1095
    VSSRLRNI_B_H = 0x73504000,
1096
    VSSRLRNI_H_W = 0x73508000,
1097
    VSSRLRNI_W_D = 0x73510000,
1098
    VSSRLRNI_D_Q = 0x73520000,
1099
    VSSRLRNI_BU_H = 0x73544000,
1100
    VSSRLRNI_HU_W = 0x73548000,
1101
    VSSRLRNI_WU_D = 0x73550000,
1102
    VSSRLRNI_DU_Q = 0x73560000,
1103
    VSRANI_B_H = 0x73584000,
1104
    VSRANI_H_W = 0x73588000,
1105
    VSRANI_W_D = 0x73590000,
1106
    VSRANI_D_Q = 0x735a0000,
1107
    VSRARNI_B_H = 0x735c4000,
1108
    VSRARNI_H_W = 0x735c8000,
1109
    VSRARNI_W_D = 0x735d0000,
1110
    VSRARNI_D_Q = 0x735e0000,
1111
    VSSRANI_B_H = 0x73604000,
1112
    VSSRANI_H_W = 0x73608000,
1113
    VSSRANI_W_D = 0x73610000,
1114
    VSSRANI_D_Q = 0x73620000,
1115
    VSSRANI_BU_H = 0x73644000,
1116
    VSSRANI_HU_W = 0x73648000,
1117
    VSSRANI_WU_D = 0x73650000,
1118
    VSSRANI_DU_Q = 0x73660000,
1119
    VSSRARNI_B_H = 0x73684000,
1120
    VSSRARNI_H_W = 0x73688000,
1121
    VSSRARNI_W_D = 0x73690000,
1122
    VSSRARNI_D_Q = 0x736a0000,
1123
    VSSRARNI_BU_H = 0x736c4000,
1124
    VSSRARNI_HU_W = 0x736c8000,
1125
    VSSRARNI_WU_D = 0x736d0000,
1126
    VSSRARNI_DU_Q = 0x736e0000,
1127
    VEXTRINS_D = 0x73800000,
1128
    VEXTRINS_W = 0x73840000,
1129
    VEXTRINS_H = 0x73880000,
1130
    VEXTRINS_B = 0x738c0000,
1131
    VSHUF4I_B = 0x73900000,
1132
    VSHUF4I_H = 0x73940000,
1133
    VSHUF4I_W = 0x73980000,
1134
    VSHUF4I_D = 0x739c0000,
1135
    VBITSELI_B = 0x73c40000,
1136
    VANDI_B = 0x73d00000,
1137
    VORI_B = 0x73d40000,
1138
    VXORI_B = 0x73d80000,
1139
    VNORI_B = 0x73dc0000,
1140
    VLDI = 0x73e00000,
1141
    VPERMI_W = 0x73e40000,
1142
};
1143

1144
static inline s32 SignReduce32(s32 v, int width) {
1145
	int shift = 32 - width;
1146
	return (v << shift) >> shift;
1147
}
1148

1149
static inline s64 SignReduce64(s64 v, int width) {
1150
	int shift = 64 - width;
1151
	return (v << shift) >> shift;
1152
}
1153

1154
static inline bool SupportsCPUCFG() {
1155
    return cpu_info.LOONGARCH_CPUCFG;
1156
}
1157

1158
static inline bool SupportsLAM() {
1159
    return cpu_info.LOONGARCH_LAM;
1160
}
1161

1162
static inline bool SupportsUAL() {
1163
    return cpu_info.LOONGARCH_UAL;
1164
}
1165

1166
static inline bool SupportsFPU() {
1167
    return cpu_info.LOONGARCH_FPU;
1168
}
1169

1170
static inline bool SupportsLSX() {
1171
    return cpu_info.LOONGARCH_LSX;
1172
}
1173

1174
static inline bool SupportsLASX() {
1175
    return cpu_info.LOONGARCH_LASX;
1176
}
1177

1178
static inline bool SupportsCRC32() {
1179
    return cpu_info.LOONGARCH_CRC32;
1180
}
1181

1182
static inline bool SupportsComplex() {
1183
    return cpu_info.LOONGARCH_COMPLEX;
1184
}
1185

1186
static inline bool SupportsCrypto() {
1187
    return cpu_info.LOONGARCH_CRYPTO;
1188
}
1189

1190
static inline bool SupportsLVZ() {
1191
    return cpu_info.LOONGARCH_LVZ;
1192
}
1193

1194
static inline bool SupportsLBT_X86() {
1195
    return cpu_info.LOONGARCH_LBT_X86;
1196
}
1197

1198
static inline bool SupportsLBT_ARM() {
1199
    return cpu_info.LOONGARCH_LBT_ARM;
1200
}
1201

1202
static inline bool SupportsLBT_MIPS() {
1203
    return cpu_info.LOONGARCH_LBT_MIPS;
1204
}
1205

1206
static inline bool SupportsPTW() {
1207
    return cpu_info.LOONGARCH_PTW;
1208
}
1209

1210
LoongArch64Emitter::LoongArch64Emitter(const u8 *ptr, u8 *writePtr) {
1211
    SetCodePointer(ptr, writePtr);
1212
}
1213

1214
void LoongArch64Emitter::SetCodePointer(const u8 *ptr, u8 *writePtr) {
1215
	code_ = ptr;
1216
	writable_ = writePtr;
1217
    lastCacheFlushEnd_ = ptr;
1218
}
1219

1220
const u8 *LoongArch64Emitter::GetCodePointer() const {
1221
	return code_;
1222
}
1223

1224
u8 *LoongArch64Emitter::GetWritableCodePtr() {
1225
	return writable_;
1226
}
1227

1228
static inline u32 EncodeDJK(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1229
    _assert_msg_(IsGPR(rd), "DJK instruction rd must be GPR");
1230
    _assert_msg_(IsGPR(rj), "DJK instruction rj must be GPR");
1231
    _assert_msg_(IsGPR(rk), "DJK instruction rk must be GPR");
1232
    return (u32)opcode | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd;
1233
}
1234

1235
static inline u32 EncodeDJSk12(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
1236
    _assert_msg_(IsGPR(rd), "DJSk12 instruction rd must be GPR");
1237
    _assert_msg_(IsGPR(rj), "DJSk12 instruction rj must be GPR");
1238
    return (u32)opcode | ((u32)(si12 & 0xFFF) << 10) | ((u32)rj << 5) | (u32)rd;
1239
}
1240

1241
static inline u32 EncodeDJUk12(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12) {
1242
    _assert_msg_(IsGPR(rd), "DJUk12 instruction rd must be GPR");
1243
    _assert_msg_(IsGPR(rj), "DJUk12 instruction rj must be GPR");
1244
    return (u32)opcode | ((u32)(ui12 & 0xFFF) << 10) | ((u32)rj << 5) | (u32)rd;
1245
}
1246

1247
static inline u32 EncodeDJSk16(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, s16 si16) {
1248
    _assert_msg_(IsGPR(rd), "DJSk16 instruction rd must be GPR");
1249
    _assert_msg_(IsGPR(rj), "DJSk16 instruction rj must be GPR");
1250
    return (u32)opcode | ((u32)si16 << 10) | ((u32)rj << 5) | (u32)rd;
1251
}
1252

1253
static inline u32 EncodeDJKUa2pp1(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) {
1254
    _assert_msg_(IsGPR(rd), "DJKUa2pp1 instruction rd must be GPR");
1255
    _assert_msg_(IsGPR(rj), "DJKUa2pp1 instruction rj must be GPR");
1256
    _assert_msg_(IsGPR(rk), "DJKUa2pp1 instruction rk must be GPR");
1257
    // cpu will perform as sa2 + 1
1258
    return (u32)opcode | (u32)((sa2 - 1) & 0x3) << 15 | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd;
1259
}
1260

1261
static inline u32 EncodeDJKUa3pp1(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa3) {
1262
    _assert_msg_(IsGPR(rd), "DJKUa3pp1 instruction rd must be GPR");
1263
    _assert_msg_(IsGPR(rj), "DJKUa3pp1 instruction rj must be GPR");
1264
    _assert_msg_(IsGPR(rk), "DJKUa3pp1 instruction rk must be GPR");
1265
    // cpu will perform as sa3 + 1
1266
    return (u32)opcode | (u32)((sa3 - 1) & 0x7) << 15 | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd;
1267
}
1268

1269
static inline u32 EncodeDSj20(Opcode32 opcode, LoongArch64Reg rd, s32 si20) {
1270
    _assert_msg_(IsGPR(rd), "DSj20 instruction rd must be GPR");
1271
    return (u32)opcode | ((u32)(si20 & 0xFFFFF) << 5) | (u32)rd;
1272
}
1273

1274
static inline u32 EncodeDJUk5(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) {
1275
    _assert_msg_(IsGPR(rd), "DJUk5 instruction rd must be GPR");
1276
    _assert_msg_(IsGPR(rj), "DJUk5 instruction rj must be GPR");
1277
    return (u32)opcode | ((u32)(ui5 & 0x1F) << 10) | ((u32)rj << 5) | (u32)rd;
1278
}
1279

1280
static inline u32 EncodeDJUk6(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) {
1281
    _assert_msg_(IsGPR(rd), "DJUk6 instruction rd must be GPR");
1282
    _assert_msg_(IsGPR(rj), "DJUk6 instruction rj must be GPR");
1283
    return (u32)opcode | ((u32)(ui6 & 0x3F) << 10) | ((u32)rj << 5) | (u32)rd;
1284
}
1285

1286
static inline u32 EncodeDJ(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj) {
1287
    _assert_msg_(IsGPR(rd), "DJ instruction rd must be GPR");
1288
    _assert_msg_(IsGPR(rj), "DJ instruction rj must be GPR");
1289
    return (u32)opcode | ((u32)rj << 5) | (u32)rd;
1290
}
1291

1292
static inline u32 EncodeJK(Opcode32 opcode, LoongArch64Reg rj, LoongArch64Reg rk) {
1293
    _assert_msg_(IsGPR(rj), "JK instruction rj must be GPR");
1294
    _assert_msg_(IsGPR(rk), "JK instruction rk must be GPR");
1295
    return (u32)opcode | ((u32)rk << 5) | ((u32)rj << 5);
1296
}
1297

1298
static inline u32 EncodeDJKUa2(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) {
1299
    _assert_msg_(IsGPR(rd), "DJKUa2 instruction rd must be GPR");
1300
    _assert_msg_(IsGPR(rj), "DJKUa2 instruction rj must be GPR");
1301
    _assert_msg_(IsGPR(rk), "DJKUa2 instruction rk must be GPR");
1302
    return (u32)opcode | ((u32)(sa2 & 0x3) << 15) | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd;
1303
}
1304

1305
static inline u32 EncodeDJUk5Um5(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u8 msbw, u8 lsbw) {
1306
    _assert_msg_(IsGPR(rd), "DJUk5Um5 instruction rd must be GPR");
1307
    _assert_msg_(IsGPR(rj), "DJUk5Um5 instruction rj must be GPR");
1308
    return (u32)opcode | ((u32)(msbw & 0x1F) << 16) | ((u32)(lsbw & 0x1f) << 10) | ((u32)rj << 5) | (u32)rd;
1309
}
1310

1311
static inline u32 EncodeDJUk6Um6(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u8 msbd, u8 lsbd) {
1312
    _assert_msg_(IsGPR(rd), "DJUk6Um6 instruction rd must be GPR");
1313
    _assert_msg_(IsGPR(rj), "DJUk6Um6 instruction rj must be GPR");
1314
    return (u32)opcode | ((u32)(msbd & 0x3F) << 16) | ((u32)(lsbd & 0x3f) << 10) | ((u32)rj << 5) | (u32)rd;
1315
}
1316

1317
static inline u32 EncodeDJKUa3(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa3) {
1318
    _assert_msg_(IsGPR(rd), "DJKUa3 instruction rd must be GPR");
1319
    _assert_msg_(IsGPR(rj), "DJKUa3 instruction rj must be GPR");
1320
    _assert_msg_(IsGPR(rk), "DJKUa3 instruction rk must be GPR");
1321
    return (u32)opcode | (u32)(sa3 & 0x7) << 15 | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd;
1322
}
1323

1324
static inline u32 EncodeJDSk16ps2(Opcode32 opcode, LoongArch64Reg rj, LoongArch64Reg rd, s32 offs16) {
1325
    _assert_msg_(IsGPR(rd), "JDSk16ps2 instruction rd must be GPR");
1326
    _assert_msg_(IsGPR(rj), "JDSk16ps2 instruction rj must be GPR");
1327
    _assert_msg_((offs16 & 3) == 0, "offs16 immediate must be aligned to 4");
1328
    u32 offs = (u32)(offs16 >> 2);
1329
    return (u32)opcode | ((offs & 0xFFFF) << 10) | ((u32)rj << 5) | (u32)rd;
1330
}
1331

1332
static inline u32 EncodeDJSk16ps2(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, s32 offs16) {
1333
    _assert_msg_(IsGPR(rd), "DJSk16ps2 instruction rd must be GPR");
1334
    _assert_msg_(IsGPR(rj), "DJSk16ps2 instruction rj must be GPR");
1335
    _assert_msg_((offs16 & 3) == 0, "offs16 immediate must be aligned to 4");
1336
    u32 offs = (u32)(offs16 >> 2) & 0xFFFF;
1337
    return (u32)opcode | ((offs & 0xFFFF) << 10) | ((u32)rj << 5) | (u32)rd;
1338
}
1339

1340
static inline u32 EncodeJSd5k16(Opcode32 opcode, LoongArch64Reg rj, s32 offs21) {
1341
    _assert_msg_(IsGPR(rj), "JSd5k16 instruction rj must be GPR");
1342
    _assert_msg_((offs21 & 3) == 0, "offs21 immediate must be aligned to 4");
1343
    u32 offs = (u32)(offs21 >> 2);
1344
    return (u32)opcode | ((offs & 0xFFFF) << 10) | ((u32)rj << 5) | ((offs >> 16) & 0x1F);
1345
}
1346

1347
static inline u32 EncodeSd10k16ps2(Opcode32 opcode, s32 offs26) {
1348
    _assert_msg_((offs26 & 3) == 0, "offs21 immediate must be aligned to 4");
1349
    u32 offs = (u32)(offs26 >> 2);
1350
    return (u32)opcode | ((offs & 0xFFFF) << 10) | ((offs >> 16) & 0x3FF);
1351
}
1352

1353
static inline u32 EncodeDJSk14ps2(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) {
1354
    _assert_msg_(IsGPR(rd), "DJSk14ps2 instruction rd must be GPR");
1355
    _assert_msg_(IsGPR(rj), "DJSk14ps2 instruction rj must be GPR");
1356
    _assert_msg_((si14 & 3) == 0, "offs21 immediate must be aligned to 4");
1357
    u32 si = (u32)(si14 >> 2);
1358
    return (u32)opcode | (si & 0x3FFF) << 10 | ((u32)rj << 5) | (u32)rd;
1359
}
1360

1361
static inline u32 EncodeUd5JSk12(Opcode32 opcode, u32 hint, LoongArch64Reg rj, s16 si12) {
1362
    _assert_msg_(IsGPR(rj), "Ud5JSk12 instruction rj must be GPR");
1363
    _assert_msg_((si12 & 3) == 0, "offs21 immediate must be aligned to 4");
1364
    return (u32)opcode | ((u32)(si12 & 0xFFF) << 10) | ((u32)rj << 5) | (u32)(hint & 0x1F);
1365
}
1366

1367
static inline u32 EncodeUd5JK(Opcode32 opcode, u32 hint, LoongArch64Reg rj, LoongArch64Reg rk) {
1368
    _assert_msg_(IsGPR(rj), "Ud5JK instruction rj must be GPR");
1369
    _assert_msg_(IsGPR(rk), "Ud5JK instruction rk must be GPR");
1370
    return (u32)opcode | ((u32)rk << 10) | ((u32)rj << 5) | (u32)(hint & 0x1F);
1371
}
1372

1373
static inline u32 EncodeDKJ(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
1374
    _assert_msg_(IsGPR(rd), "DKJ instruction rd must be GPR");
1375
    _assert_msg_(IsGPR(rj), "DKJ instruction rj must be GPR");
1376
    _assert_msg_(IsGPR(rk), "DKJ instruction rk must be GPR");
1377
    return (u32)opcode | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd;
1378
}
1379

1380
static inline u32 EncodeUd15(Opcode32 opcode, u16 code) {
1381
    return (u32)opcode | (u32)(code & 0x7FFF);
1382
}
1383

1384
static inline u32 EncodeFdFjFk(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
1385
    _assert_msg_(IsFPR(fd), "FdFjFk instruction fd must be FPR");
1386
    _assert_msg_(IsFPR(fj), "FdFjFk instruction fj must be FPR");
1387
    _assert_msg_(IsFPR(fk), "FdFjFk instruction fk must be FPR");
1388
    return (u32)opcode | ((u32)DecodeReg(fk) << 10) | ((u32)DecodeReg(fj) << 5) | (u32)DecodeReg(fd);
1389
}
1390

1391
static inline u32 EncodeFdFjFkFa(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
1392
    _assert_msg_(IsFPR(fd), "FdFjFkFa instruction fd must be FPR");
1393
    _assert_msg_(IsFPR(fj), "FdFjFkFa instruction fj must be FPR");
1394
    _assert_msg_(IsFPR(fk), "FdFjFkFa instruction fk must be FPR");
1395
    _assert_msg_(IsFPR(fa), "FdFjFkFa instruction fk must be FPR");
1396
    return (u32)opcode | ((u32)DecodeReg(fa) << 15) | ((u32)DecodeReg(fk) << 10) | ((u32)DecodeReg(fj) << 5) | (u32)DecodeReg(fd);
1397
}
1398

1399
static inline u32 EncodeFdFj(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg fj) {
1400
    _assert_msg_(IsFPR(fd), "FdFj instruction fd must be FPR");
1401
    _assert_msg_(IsFPR(fj), "FdFj instruction fj must be FPR");
1402
    return (u32)opcode | ((u32)DecodeReg(fj) << 5) | (u32)DecodeReg(fd);
1403
}
1404

1405
static inline u32 EncodeCdFjFkFcond(Opcode32 opcode, LoongArch64CFR cd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Fcond cond) {
1406
    _assert_msg_(IsCFR(cd), "CdFjFkFcond instruction cd must be CFR");
1407
    _assert_msg_(IsFPR(fj), "CdFjFkFcond instruction fj must be FPR");
1408
    _assert_msg_(IsFPR(fk), "CdFjFkFcond instruction fk must be FPR");
1409
    return (u32)opcode | ((u32)cond << 15) | ((u32)DecodeReg(fk) << 10) | ((u32)DecodeReg(fj) << 5) | (u32)cd;
1410
}
1411

1412
static inline u32 EncodeFdFjFkCa(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64CFR ca) {
1413
    _assert_msg_(IsFPR(fd), "FdFjFkCa instruction fd must be FPR");
1414
    _assert_msg_(IsFPR(fj), "FdFjFkCa instruction fj must be FPR");
1415
    _assert_msg_(IsFPR(fk), "FdFjFkCa instruction fk must be FPR");
1416
    _assert_msg_(IsCFR(ca), "FdFjFkCa instruction ca must be CFR");
1417
    return (u32)opcode | ((u32)ca << 15) | ((u32)DecodeReg(fk) << 10) | ((u32)DecodeReg(fj) << 5) | (u32)DecodeReg(fd);
1418
}
1419

1420
static inline u32 EncodeFdJ(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg rj) {
1421
    _assert_msg_(IsFPR(fd), "FdJ instruction fd must be FPR");
1422
    _assert_msg_(IsGPR(rj), "FdJ instruction rj must be GPR");
1423
    return (u32)opcode | ((u32)rj << 5) | (u32)DecodeReg(fd);
1424
}
1425

1426
static inline u32 EncodeDFj(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg fj) {
1427
    _assert_msg_(IsGPR(rd), "DFj instruction rd must be GPR");
1428
    _assert_msg_(IsFPR(fj), "DFj instruction fj must be FPR");
1429
    return (u32)opcode | ((u32)fj << 5) | (u32)DecodeReg(rd);
1430
}
1431

1432
static inline u32 EncodeJUd5(Opcode32 opcode, LoongArch64FCSR fcsr, LoongArch64Reg rj) {
1433
    _assert_msg_(IsFCSR(fcsr), "JUd5 instruction fcsr must be FCSR");
1434
    _assert_msg_(IsGPR(rj), "JUd5 instruction rj must be GPR");
1435
    return (u32)opcode | ((u32)rj << 5) | (u32)fcsr;
1436
}
1437

1438
static inline u32 EncodeDUj5(Opcode32 opcode, LoongArch64Reg rd, LoongArch64FCSR fcsr) {
1439
    _assert_msg_(IsGPR(rd), "DUj5 instruction rd must be GPR");
1440
    _assert_msg_(IsFCSR(fcsr), "DUj5 instruction fcsr must be FCSR");
1441
    return (u32)opcode | ((u32)fcsr << 5) | (u32)rd;
1442
}
1443

1444
static inline u32 EncodeCdFj(Opcode32 opcode, LoongArch64CFR cd, LoongArch64Reg fj) {
1445
    _assert_msg_(IsCFR(cd), "CdFj instruction cd must be CFR");
1446
    _assert_msg_(IsFPR(fj), "CdFj instruction fj must be FPR");
1447
    return (u32)opcode | ((u32)DecodeReg(fj) << 5) | (u32)cd;
1448
}
1449

1450
static inline u32 EncodeFdCj(Opcode32 opcode, LoongArch64Reg fd, LoongArch64CFR cj) {
1451
    _assert_msg_(IsFPR(fd), "FdCj instruction fd must be FPR");
1452
    _assert_msg_(IsCFR(cj), "FdCj instruction cj must be CFR");
1453
    return (u32)opcode | ((u32)cj << 5) | (u32)DecodeReg(fd);
1454
}
1455

1456
static inline u32 EncodeCdJ(Opcode32 opcode, LoongArch64CFR cd, LoongArch64Reg rj) {
1457
    _assert_msg_(IsCFR(cd), "CdJ instruction cd must be CFR");
1458
    _assert_msg_(IsGPR(rj), "CdJ instruction rj must be GPR");
1459
    return (u32)opcode | ((u32)rj << 5) | (u32)cd;
1460
}
1461

1462
static inline u32 EncodeDCj(Opcode32 opcode, LoongArch64Reg rd, LoongArch64CFR cj) {
1463
    _assert_msg_(IsGPR(rd), "DCj instruction rd must be GPR");
1464
    _assert_msg_(IsCFR(cj), "DCj instruction cj must be CFR");
1465
    return (u32)opcode | ((u32)cj << 5) | (u32)rd;
1466
}
1467

1468
static inline u32 EncodeCjSd5k16ps2(Opcode32 opcode, LoongArch64CFR cj, s32 offs21) {
1469
    _assert_msg_(IsCFR(cj), "CjSd5k16ps2 instruction cj must be CFR");
1470
    _assert_msg_((offs21 & 3) == 0, "offs21 immediate must be aligned to 4");
1471
    u32 offs = (u32)(offs21 >> 2);
1472
    return (u32)opcode | ((offs & 0xFFFF) << 10) | ((u32)cj << 5) | ((offs >> 16) & 0x1F);
1473
}
1474

1475
static inline u32 EncodeFdJSk12(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) {
1476
    _assert_msg_(IsFPR(fd), "FdJSk12 instruction fd must be FPR");
1477
    _assert_msg_(IsGPR(rj), "FdJSk12 instruction rj must be GPR");
1478
    return (u32)opcode | ((u32)(si12 & 0xFFF) << 10) | ((u32)rj << 5) | (u32)DecodeReg(fd);
1479
}
1480

1481
static inline u32 EncodeFdJK(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
1482
    _assert_msg_(IsFPR(fd), "FdJK instruction fd must be FPR");
1483
    _assert_msg_(IsGPR(rj), "FdJK instruction rj must be GPR");
1484
    _assert_msg_(IsGPR(rk), "FdJK instruction rk must be GPR");
1485
    return (u32)opcode | ((u32)rk << 10) | ((u32)rj << 5) | (u32)DecodeReg(fd);
1486
}
1487

1488
static inline u32 EncodeVdVjVkVa(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
1489
    _assert_msg_(IsVPR(vd), "VdVjVkVa instruction vd must be VPR");
1490
    _assert_msg_(IsVPR(vj), "VdVjVkVa instruction vj must be VPR");
1491
    _assert_msg_(IsVPR(vk), "VdVjVkVa instruction vk must be VPR");
1492
    _assert_msg_(IsVPR(va), "VdVjVkVa instruction vk must be VPR");
1493
    return (u32)opcode | ((u32)DecodeReg(va) << 15) | ((u32)DecodeReg(vk) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1494
}
1495

1496
static inline u32 EncodeVdVjVk(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
1497
    _assert_msg_(IsVPR(vd), "VdVjVk instruction vd must be VPR");
1498
    _assert_msg_(IsVPR(vj), "VdVjVk instruction vj must be VPR");
1499
    _assert_msg_(IsVPR(vk), "VdVjVk instruction vk must be VPR");
1500
    return (u32)opcode | ((u32)DecodeReg(vk) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1501
}
1502

1503
static inline u32 EncodeVdJSk12(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si12) {
1504
    _assert_msg_(IsVPR(vd), "VdJSk12 instruction vd must be VPR");
1505
    _assert_msg_(IsGPR(rj), "VdJSk12 instruction rj must be GPR");
1506
    return (u32)opcode | ((u32)(si12 & 0xFFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1507
}
1508

1509
static inline u32 EncodeVdJSk11(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si11) {
1510
    _assert_msg_(IsVPR(vd), "VdJSk11 instruction vd must be VPR");
1511
    _assert_msg_(IsGPR(rj), "VdJSk11 instruction rj must be GPR");
1512
    return (u32)opcode | ((u32)((si11 >> 1) & 0x7FF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1513
}
1514

1515
static inline u32 EncodeVdJSk10(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si10) {
1516
    _assert_msg_(IsVPR(vd), "VdJSk10 instruction vd must be VPR");
1517
    _assert_msg_(IsGPR(rj), "VdJSk10 instruction rj must be GPR");
1518
    return (u32)opcode | ((u32)((si10 >> 2) & 0x3FF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1519
}
1520

1521
static inline u32 EncodeVdJSk9(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si9) {
1522
    _assert_msg_(IsVPR(vd), "VdJSk9 instruction vd must be VPR");
1523
    _assert_msg_(IsGPR(rj), "VdJSk9 instruction rj must be GPR");
1524
    return (u32)opcode | ((u32)((si9 >> 3) & 0x1FF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1525
}
1526

1527
static inline u32 EncodeVdJSk8Un1(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx1) {
1528
    _assert_msg_(IsVPR(vd), "VdJSk8Un1 instruction vd must be VPR");
1529
    _assert_msg_(IsGPR(rj), "VdJSk8Un1 instruction rj must be GPR");
1530
    return (u32)opcode | (u32)((idx1 & 0x1) << 18) | ((u32)((si8 >> 3) & 0xFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1531
}
1532

1533
static inline u32 EncodeVdJSk8Un2(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx2) {
1534
    _assert_msg_(IsVPR(vd), "VdJSk8Un2 instruction vd must be VPR");
1535
    _assert_msg_(IsGPR(rj), "VdJSk8Un2 instruction rj must be GPR");
1536
    return (u32)opcode | (u32)((idx2 & 0x3) << 18) | ((u32)((si8 >> 2) & 0xFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1537
}
1538

1539
static inline u32 EncodeVdJSk8Un3(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx3) {
1540
    _assert_msg_(IsVPR(vd), "VdJSk8Un3 instruction vd must be VPR");
1541
    _assert_msg_(IsGPR(rj), "VdJSk8Un3 instruction rj must be GPR");
1542
    return (u32)opcode | (u32)((idx3 & 0x7) << 18) | ((u32)((si8 >> 1) & 0xFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1543
}
1544

1545
static inline u32 EncodeVdJSk8Un4(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx4) {
1546
    _assert_msg_(IsVPR(vd), "VdJSk8Un4 instruction vd must be VPR");
1547
    _assert_msg_(IsGPR(rj), "VdJSk8Un4 instruction rj must be GPR");
1548
    return (u32)opcode | (u32)((idx4 & 0xF) << 18) | ((u32)(si8 & 0xFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1549
}
1550

1551
static inline u32 EncodeVdJK(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, LoongArch64Reg rk) {
1552
    _assert_msg_(IsVPR(vd), "VdJK instruction vd must be VPR");
1553
    _assert_msg_(IsGPR(rj), "VdJK instruction rj must be GPR");
1554
    _assert_msg_(IsGPR(rk), "VdJK instruction rk must be GPR");
1555
    return (u32)opcode | ((u32)DecodeReg(rk) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1556
}
1557

1558
static inline u32 EncodeVdVjSk5(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
1559
    _assert_msg_(IsVPR(vd), "VdVjSk5 instruction vd must be VPR");
1560
    _assert_msg_(IsVPR(vj), "VdVjSk5 instruction vj must be VPR");
1561
    return (u32)opcode | ((u32)(si5 & 0x1F) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1562
}
1563

1564
static inline u32 EncodeVdVjUk1(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui1) {
1565
    _assert_msg_(IsVPR(vd), "VdVjUk1 instruction vd must be VPR");
1566
    _assert_msg_(IsVPR(vj), "VdVjUk1 instruction vj must be VPR");
1567
    return (u32)opcode | ((u32)(ui1 & 0x1) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1568
}
1569

1570
static inline u32 EncodeVdVjUk2(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui2) {
1571
    _assert_msg_(IsVPR(vd), "VdVjUk2 instruction vd must be VPR");
1572
    _assert_msg_(IsVPR(vj), "VdVjUk2 instruction vj must be VPR");
1573
    return (u32)opcode | ((u32)(ui2 & 0x3) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1574
}
1575

1576
static inline u32 EncodeVdVjUk3(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
1577
    _assert_msg_(IsVPR(vd), "VdVjUk3 instruction vd must be VPR");
1578
    _assert_msg_(IsVPR(vj), "VdVjUk3 instruction vj must be VPR");
1579
    return (u32)opcode | ((u32)(ui3 & 0x7) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1580
}
1581

1582
static inline u32 EncodeVdVjUk4(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
1583
    _assert_msg_(IsVPR(vd), "VdVjUk4 instruction vd must be VPR");
1584
    _assert_msg_(IsVPR(vj), "VdVjUk4 instruction vj must be VPR");
1585
    return (u32)opcode | ((u32)(ui4 & 0xF) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1586
}
1587

1588
static inline u32 EncodeVdVjUk5(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
1589
    _assert_msg_(IsVPR(vd), "VdVjUk5 instruction vd must be VPR");
1590
    _assert_msg_(IsVPR(vj), "VdVjUk5 instruction vj must be VPR");
1591
    return (u32)opcode | ((u32)(ui5 & 0x1F) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1592
}
1593

1594
static inline u32 EncodeVdVjUk6(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
1595
    _assert_msg_(IsVPR(vd), "VdVjUk6 instruction vd must be VPR");
1596
    _assert_msg_(IsVPR(vj), "VdVjUk6 instruction vj must be VPR");
1597
    return (u32)opcode | ((u32)(ui6 & 0x3F) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1598
}
1599

1600
static inline u32 EncodeVdVjUk7(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
1601
    _assert_msg_(IsVPR(vd), "VdVjUk7 instruction vd must be VPR");
1602
    _assert_msg_(IsVPR(vj), "VdVjUk7 instruction vj must be VPR");
1603
    return (u32)opcode | ((u32)(ui7 & 0x7F) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1604
}
1605

1606
static inline u32 EncodeVdVjUk8(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
1607
    _assert_msg_(IsVPR(vd), "VdVjUk8 instruction vd must be VPR");
1608
    _assert_msg_(IsVPR(vj), "VdVjUk8 instruction vj must be VPR");
1609
    return (u32)opcode | ((u32)(ui8 & 0xFF) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1610
}
1611

1612
static inline u32 EncodeVdVj(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj) {
1613
    _assert_msg_(IsVPR(vd), "VdVj instruction vd must be VPR");
1614
    _assert_msg_(IsVPR(vj), "VdVj instruction vj must be VPR");
1615
    return (u32)opcode | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1616
}
1617

1618
static inline u32 EncodeVdVjK(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) {
1619
    _assert_msg_(IsVPR(vd), "VdVjK instruction vd must be VPR");
1620
    _assert_msg_(IsVPR(vj), "VdVjK instruction vj must be VPR");
1621
    _assert_msg_(IsGPR(rk), "VdVjK instruction rk must be GPR");
1622
    return (u32)opcode | ((u32)DecodeReg(rk) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd);
1623
}
1624

1625
static inline u32 EncodeCdVj(Opcode32 opcode, LoongArch64CFR cd, LoongArch64Reg vj) {
1626
    _assert_msg_(IsCFR(cd), "CdVj instruction cd must be CFR");
1627
    _assert_msg_(IsVPR(vj), "CdVj instruction vj must be VPR");
1628
    return (u32)opcode | ((u32)DecodeReg(vj) << 5) | (u32)(cd & 0x7);
1629
}
1630

1631
static inline u32 EncodeVdJ(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj) {
1632
    _assert_msg_(IsVPR(vd), "VdJ instruction vd must be VPR");
1633
    _assert_msg_(IsGPR(rj), "VdJ instruction rj must be GPR");
1634
    return (u32)opcode | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1635
}
1636

1637
static inline u32 EncodeVdJUk1(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, u8 ui1) {
1638
    _assert_msg_(IsVPR(vd), "VdJUk1 instruction vd must be VPR");
1639
    _assert_msg_(IsGPR(rj), "VdJUk1 instruction rj must be GPR");
1640
    return (u32)opcode | ((u32)(ui1 & 0x1) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1641
}
1642

1643
static inline u32 EncodeVdJUk2(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, u8 ui2) {
1644
    _assert_msg_(IsVPR(vd), "VdJUk2 instruction vd must be VPR");
1645
    _assert_msg_(IsGPR(rj), "VdJUk2 instruction rj must be GPR");
1646
    return (u32)opcode | ((u32)(ui2 & 0x3) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1647
}
1648

1649
static inline u32 EncodeVdJUk3(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, u8 ui3) {
1650
    _assert_msg_(IsVPR(vd), "VdJUk3 instruction vd must be VPR");
1651
    _assert_msg_(IsGPR(rj), "VdJUk3 instruction rj must be GPR");
1652
    return (u32)opcode | ((u32)(ui3 & 0x7) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1653
}
1654

1655
static inline u32 EncodeVdJUk4(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, u8 ui4) {
1656
    _assert_msg_(IsVPR(vd), "VdJUk4 instruction vd must be VPR");
1657
    _assert_msg_(IsGPR(rj), "VdJUk4 instruction rj must be GPR");
1658
    return (u32)opcode | ((u32)(ui4 & 0xF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd);
1659
}
1660

1661
static inline u32 EncodeDVjUk1(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg vj, u8 ui1) {
1662
    _assert_msg_(IsGPR(rd), "DVjUk1 instruction rd must be GPR");
1663
    _assert_msg_(IsVPR(vj), "DVjUk1 instruction vj must be VPR");
1664
    return (u32)opcode | ((u32)(ui1 & 0x1) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(rd);
1665
}
1666

1667
static inline u32 EncodeDVjUk2(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg vj, u8 ui2) {
1668
    _assert_msg_(IsGPR(rd), "DVjUk2 instruction rd must be GPR");
1669
    _assert_msg_(IsVPR(vj), "DVjUk2 instruction vj must be VPR");
1670
    return (u32)opcode | ((u32)(ui2 & 0x3) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(rd);
1671
}
1672

1673
static inline u32 EncodeDVjUk3(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg vj, u8 ui3) {
1674
    _assert_msg_(IsGPR(rd), "DVjUk3 instruction rd must be GPR");
1675
    _assert_msg_(IsVPR(vj), "DVjUk3 instruction vj must be VPR");
1676
    return (u32)opcode | ((u32)(ui3 & 0x7) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(rd);
1677
}
1678

1679
static inline u32 EncodeDVjUk4(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg vj, u8 ui4) {
1680
    _assert_msg_(IsGPR(rd), "DVjUk4 instruction rd must be GPR");
1681
    _assert_msg_(IsVPR(vj), "DVjUk4 instruction vj must be VPR");
1682
    return (u32)opcode | ((u32)(ui4 & 0xF) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(rd);
1683
}
1684

1685
static inline u32 EncodeVdSj13(Opcode32 opcode, LoongArch64Reg vd, s16 i13) {
1686
    _assert_msg_(IsVPR(vd), "VdJUk4 instruction vd must be VPR");
1687
    return (u32)opcode | ((u32)(i13 & 0x1FFF) << 5) | (u32)DecodeReg(vd);
1688
}
1689

1690
void LoongArch64Emitter::ReserveCodeSpace(u32 bytes)
1691
{
1692
	for (u32 i = 0; i < bytes / 4; i++)
1693
		BREAK(0);
1694
}
1695

1696
const u8 *LoongArch64Emitter::AlignCode16() {
1697
	int c = int((u64)code_ & 15);
1698
	if (c)
1699
		ReserveCodeSpace(16 - c);
1700
	return code_;
1701
}
1702

1703
const u8 *LoongArch64Emitter::AlignCodePage() {
1704
	int page_size = GetMemoryProtectPageSize();
1705
	int c = int((intptr_t)code_ & ((intptr_t)page_size - 1));
1706
	if (c)
1707
		ReserveCodeSpace(page_size - c);
1708
	return code_;
1709
}
1710

1711
void LoongArch64Emitter::FlushIcache() {
1712
	FlushIcacheSection(lastCacheFlushEnd_, code_);
1713
	lastCacheFlushEnd_ = code_;
1714
}
1715

1716
void LoongArch64Emitter::FlushIcacheSection(const u8 *start, const u8 *end) {
1717
#if PPSSPP_ARCH(LOONGARCH64)
1718
	__builtin___clear_cache((char *)start, (char *)end);
1719
#endif
1720
}
1721

1722
FixupBranch::FixupBranch(FixupBranch &&other) {
1723
	ptr = other.ptr;
1724
	type = other.type;
1725
	other.ptr = nullptr;
1726
}
1727

1728
FixupBranch::~FixupBranch() {
1729
	_assert_msg_(ptr == nullptr, "FixupBranch never set (left infinite loop)");
1730
}
1731

1732
FixupBranch &FixupBranch::operator =(FixupBranch &&other) {
1733
	ptr = other.ptr;
1734
	type = other.type;
1735
	other.ptr = nullptr;
1736
	return *this;
1737
}
1738

1739
void LoongArch64Emitter::SetJumpTarget(FixupBranch &branch) {
1740
	SetJumpTarget(branch, code_);
1741
}
1742

1743
void LoongArch64Emitter::SetJumpTarget(FixupBranch &branch, const void *dst) {
1744
	_assert_msg_(branch.ptr != nullptr, "Invalid FixupBranch (SetJumpTarget twice?)");
1745

1746
	const intptr_t srcp = (intptr_t)branch.ptr;
1747
	const intptr_t dstp = (intptr_t)dst;
1748
	const ptrdiff_t writable_delta = writable_ - code_;
1749
	u32 *writableSrc = (u32 *)(branch.ptr + writable_delta);
1750

1751
	u32 fixup;
1752

1753
	_assert_msg_((dstp & 3) == 0, "Destination should be aligned");
1754

1755
	ptrdiff_t distance = dstp - srcp;
1756
	_assert_msg_((distance & 3) == 0, "Distance should be aligned");
1757
	switch (branch.type) {
1758
	case FixupBranchType::B:
1759
		_assert_msg_(BranchInRange(branch.ptr, dst), "B destination is too far away (%p -> %p)", branch.ptr, dst);
1760
		memcpy(&fixup, writableSrc, sizeof(u32));
1761
		fixup = (fixup & 0xFC0003FF) | EncodeJDSk16ps2(Opcode32::ZERO, R_ZERO, R_ZERO, (s32)distance);
1762
		memcpy(writableSrc, &fixup, sizeof(u32));
1763
		break;
1764

1765
	case FixupBranchType::J:
1766
		_assert_msg_(JumpInRange(branch.ptr, dst), "J destination is too far away (%p -> %p)", branch.ptr, dst);
1767
		memcpy(&fixup, writableSrc, sizeof(u32));
1768
		fixup = (fixup & 0xFC000000) | EncodeSd10k16ps2(Opcode32::ZERO, (s32)distance);
1769
		memcpy(writableSrc, &fixup, sizeof(u32));
1770
		break;
1771

1772
    case FixupBranchType::BZ:
1773
		_assert_msg_(BranchInRange(branch.ptr, dst), "B destination is too far away (%p -> %p)", branch.ptr, dst);
1774
		memcpy(&fixup, writableSrc, sizeof(u32));
1775
		fixup = (fixup & 0xFC0003E0) | EncodeJSd5k16(Opcode32::ZERO, R_ZERO, (s32)distance);
1776
		memcpy(writableSrc, &fixup, sizeof(u32));
1777
		break;
1778
	}
1779

1780
	branch.ptr = nullptr;
1781
}
1782

1783
bool LoongArch64Emitter::BranchInRange(const void *func) const {
1784
	return BranchInRange(code_, func);
1785
}
1786

1787
bool LoongArch64Emitter::BranchZeroInRange(const void *func) const {
1788
	return BranchZeroInRange(code_, func);
1789
}
1790

1791
bool LoongArch64Emitter::JumpInRange(const void *func) const {
1792
	return JumpInRange(code_, func);
1793
}
1794

1795
static inline bool BJInRange(const void *src, const void *dst, int bits) {
1796
	ptrdiff_t distance = (intptr_t)dst - (intptr_t)src;
1797
	// Get rid of bits and sign extend to validate range.
1798
	s32 encodable = SignReduce32((s32)distance, bits);
1799
	return distance == encodable;
1800
}
1801

1802
bool LoongArch64Emitter::BranchInRange(const void *src, const void *dst) const {
1803
	return BJInRange(src, dst, 18);
1804
}
1805

1806
bool LoongArch64Emitter::BranchZeroInRange(const void *src, const void *dst) const {
1807
	return BJInRange(src, dst, 23);
1808
}
1809

1810
bool LoongArch64Emitter::JumpInRange(const void *src, const void *dst) const {
1811
	return BJInRange(src, dst, 28);
1812
}
1813

1814
void LoongArch64Emitter::QuickJump(LoongArch64Reg scratchreg, LoongArch64Reg rd, const u8 *dst) {
1815
	if (!JumpInRange(GetCodePointer(), dst)) {
1816
		int32_t lower = (int32_t)SignReduce64((int64_t)dst, 18);
1817
		static_assert(sizeof(intptr_t) <= sizeof(int64_t));
1818
        LI(scratchreg, dst - lower);
1819
		JIRL(rd, scratchreg, lower);
1820
	} else if (rd == R_RA) {
1821
		BL(dst);
1822
	} else {
1823
        B(dst);
1824
    }
1825
}
1826

1827
void LoongArch64Emitter::SetRegToImmediate(LoongArch64Reg rd, uint64_t value) {
1828
	int64_t svalue = (int64_t)value;
1829
	_assert_msg_(IsGPR(rd), "SetRegToImmediate only supports GPRs");
1830

1831
	if (SignReduce64(svalue, 12) == svalue) {
1832
		// Nice and simple, small immediate fits in a single ADDI against zero.
1833
		ADDI_D(rd, R_ZERO, (s32)svalue);
1834
		return;
1835
	}
1836

1837
	if (svalue <= 0x7fffffffll && svalue >= -0x80000000ll) {
1838
        // Use lu12i.w/ori to load 32-bits immediate.
1839
		LU12I_W(rd, (s32)((svalue & 0xffffffff) >> 12));
1840
		ORI(rd, rd, (s16)(svalue & 0xFFF));
1841
        return;
1842
	} else if (svalue <= 0x7ffffffffffffl && svalue >= -0x8000000000000l) {
1843
        // Use lu12i.w/ori/lu32i.d to load 52-bits immediate.
1844
		LU12I_W(rd, (s32)((svalue & 0xffffffff) >> 12));
1845
		ORI(rd, rd, (s16)(svalue & 0xFFF));
1846
		LU32I_D(rd, (s32)((svalue >> 32) & 0xfffff));
1847
        return;
1848
	}
1849
    // Use lu12i.w/ori/lu32i.d/lu52i.d to load 64-bits immediate.
1850
	LU12I_W(rd, (s32)((svalue & 0xffffffff) >> 12));
1851
	ORI(rd, rd, (s16)(svalue & 0xFFF));
1852
	LU32I_D(rd, (s32)((svalue >> 32) & 0xfffff));
1853
	return LU52I_D(rd, rd, (s16)(svalue >> 52));
1854
}
1855

1856
void LoongArch64Emitter::ADD_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1857
	_assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1858
    Write32(EncodeDJK(Opcode32::ADD_W, rd, rj, rk));
1859
}
1860

1861
void LoongArch64Emitter::ADD_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1862
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1863
    Write32(EncodeDJK(Opcode32::ADD_D, rd, rj, rk));
1864
}
1865

1866
void LoongArch64Emitter::SUB_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1867
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1868
    Write32(EncodeDJK(Opcode32::SUB_W, rd, rj, rk));
1869
}
1870

1871
void LoongArch64Emitter::SUB_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1872
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1873
    Write32(EncodeDJK(Opcode32::SUB_D, rd, rj, rk));
1874
}
1875

1876
void LoongArch64Emitter::ADDI_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
1877
    _assert_msg_(rd != R_ZERO || (rj == R0 && si12 == 0), "%s write to zero is a HINT", __func__); // work as NOP
1878
    Write32(EncodeDJSk12(Opcode32::ADDI_W, rd, rj, si12));
1879
}
1880

1881
void LoongArch64Emitter::ADDI_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
1882
    _assert_msg_(rd != R_ZERO || (rj == R0 && si12 == 0), "%s write to zero is a HINT", __func__); // work as NOP
1883
    Write32(EncodeDJSk12(Opcode32::ADDI_D, rd, rj, si12));
1884
}
1885

1886
void LoongArch64Emitter::ADDU16I_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si16) {
1887
    _assert_msg_(rd != R_ZERO || (rj == R0 && si16 == 0), "%s write to zero is a HINT", __func__); // work as NOP
1888
    Write32(EncodeDJSk16(Opcode32::ADDU16I_D, rd, rj, si16));
1889
}
1890

1891
void LoongArch64Emitter::ALSL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) {
1892
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1893
    _assert_msg_( sa2 >= 1 && sa2 <= 4, "%s shift out of range", __func__);
1894
    Write32(EncodeDJKUa2pp1(Opcode32::ALSL_W, rd, rj, rk, sa2));
1895
}
1896

1897
void LoongArch64Emitter::ALSL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) {
1898
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1899
    _assert_msg_( sa2 >= 1 && sa2 <= 4, "%s shift out of range", __func__);
1900
    Write32(EncodeDJKUa2pp1(Opcode32::ALSL_D, rd, rj, rk, sa2));
1901
}
1902

1903
void LoongArch64Emitter::ALSL_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) {
1904
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1905
    _assert_msg_( sa2 >= 1 && sa2 <= 4, "%s shift out of range", __func__);
1906
    Write32(EncodeDJKUa2pp1(Opcode32::ALSL_WU, rd, rj, rk, sa2));
1907
}
1908

1909
void LoongArch64Emitter::LU12I_W(LoongArch64Reg rd, s32 si20) {
1910
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1911
    Write32(EncodeDSj20(Opcode32::LU12I_W, rd, si20));
1912
}
1913

1914
void LoongArch64Emitter::LU32I_D(LoongArch64Reg rd, s32 si20) {
1915
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1916
    Write32(EncodeDSj20(Opcode32::LU32I_D, rd, si20));
1917
}
1918

1919
void LoongArch64Emitter::LU52I_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
1920
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1921
    Write32(EncodeDJSk12(Opcode32::LU52I_D, rd, rj, si12));
1922
}
1923

1924
void LoongArch64Emitter::SLT(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1925
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1926
    Write32(EncodeDJK(Opcode32::SLT, rd, rj, rk));
1927
}
1928

1929
void LoongArch64Emitter::SLTU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1930
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1931
    Write32(EncodeDJK(Opcode32::SLTU, rd, rj, rk));
1932
}
1933

1934
void LoongArch64Emitter::SLTI(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
1935
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1936
    Write32(EncodeDJSk12(Opcode32::SLTI, rd, rj, si12));
1937
}
1938

1939
void LoongArch64Emitter::SLTUI(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
1940
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1941
    Write32(EncodeDJSk12(Opcode32::SLTUI, rd, rj, si12));
1942
}
1943

1944
void LoongArch64Emitter::PCADDI(LoongArch64Reg rd, s32 si20) {
1945
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1946
    Write32(EncodeDSj20(Opcode32::PCADDI, rd, si20));
1947
}
1948

1949
void LoongArch64Emitter::PCADDU12I(LoongArch64Reg rd, s32 si20) {
1950
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1951
    Write32(EncodeDSj20(Opcode32::PCADDU12I, rd, si20));
1952
}
1953

1954
void LoongArch64Emitter::PCADDU18I(LoongArch64Reg rd, s32 si20) {
1955
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1956
    Write32(EncodeDSj20(Opcode32::PCADDU18I, rd, si20));
1957
}
1958

1959
void LoongArch64Emitter::PCALAU12I(LoongArch64Reg rd, s32 si20) {
1960
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1961
    Write32(EncodeDSj20(Opcode32::PCALAU12I, rd, si20));
1962
}
1963

1964
void LoongArch64Emitter::AND(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1965
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1966
    Write32(EncodeDJK(Opcode32::AND, rd, rj, rk));
1967
}
1968

1969
void LoongArch64Emitter::OR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1970
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1971
    Write32(EncodeDJK(Opcode32::OR, rd, rj, rk));
1972
}
1973

1974
void LoongArch64Emitter::NOR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1975
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1976
    Write32(EncodeDJK(Opcode32::NOR, rd, rj, rk));
1977
}
1978

1979
void LoongArch64Emitter::XOR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1980
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1981
    Write32(EncodeDJK(Opcode32::XOR, rd, rj, rk));
1982
}
1983

1984
void LoongArch64Emitter::ANDN(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1985
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1986
    Write32(EncodeDJK(Opcode32::ANDN, rd, rj, rk));
1987
}
1988

1989
void LoongArch64Emitter::ORN(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
1990
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
1991
    Write32(EncodeDJK(Opcode32::ORN, rd, rj, rk));
1992
}
1993

1994
void LoongArch64Emitter::ANDI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12) {
1995
    _assert_msg_(rd != R_ZERO || (rj == R0 && ui12 == 0), "%s write to zero is a HINT", __func__); // work as NOP
1996
    Write32(EncodeDJUk12(Opcode32::ANDI, rd, rj, ui12));
1997
}
1998

1999
void LoongArch64Emitter::ORI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12) {
2000
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2001
    Write32(EncodeDJUk12(Opcode32::ORI, rd, rj, ui12));
2002
}
2003

2004
void LoongArch64Emitter::XORI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12) {
2005
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2006
    Write32(EncodeDJUk12(Opcode32::XORI, rd, rj, ui12));
2007
}
2008

2009
void LoongArch64Emitter::MUL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2010
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2011
    Write32(EncodeDJK(Opcode32::MUL_W, rd, rj, rk));
2012
}
2013

2014
void LoongArch64Emitter::MULH_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2015
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2016
    Write32(EncodeDJK(Opcode32::MULH_W, rd, rj, rk));
2017
}
2018

2019
void LoongArch64Emitter::MULH_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2020
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2021
    Write32(EncodeDJK(Opcode32::MULH_WU, rd, rj, rk));
2022
}
2023

2024
void LoongArch64Emitter::MUL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2025
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2026
    Write32(EncodeDJK(Opcode32::MUL_D, rd, rj, rk));
2027
}
2028

2029
void LoongArch64Emitter::MULH_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2030
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2031
    Write32(EncodeDJK(Opcode32::MULH_D, rd, rj, rk));
2032
}
2033

2034
void LoongArch64Emitter::MULH_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2035
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2036
    Write32(EncodeDJK(Opcode32::MULH_DU, rd, rj, rk));
2037
}
2038

2039
void LoongArch64Emitter::MULW_D_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2040
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2041
    Write32(EncodeDJK(Opcode32::MULW_D_W, rd, rj, rk));
2042
}
2043

2044
void LoongArch64Emitter::MULW_D_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2045
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2046
    Write32(EncodeDJK(Opcode32::MULW_D_WU, rd, rj, rk));
2047
}
2048

2049
void LoongArch64Emitter::DIV_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2050
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2051
    Write32(EncodeDJK(Opcode32::DIV_W, rd, rj, rk));
2052
}
2053

2054
void LoongArch64Emitter::MOD_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2055
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2056
    Write32(EncodeDJK(Opcode32::MOD_W, rd, rj, rk));
2057
}
2058

2059
void LoongArch64Emitter::DIV_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2060
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2061
    Write32(EncodeDJK(Opcode32::DIV_WU, rd, rj, rk));
2062
}
2063

2064
void LoongArch64Emitter::MOD_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2065
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2066
    Write32(EncodeDJK(Opcode32::MOD_WU, rd, rj, rk));
2067
}
2068

2069
void LoongArch64Emitter::DIV_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2070
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2071
    Write32(EncodeDJK(Opcode32::DIV_D, rd, rj, rk));
2072
}
2073

2074
void LoongArch64Emitter::MOD_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2075
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2076
    Write32(EncodeDJK(Opcode32::MOD_D, rd, rj, rk));
2077
}
2078

2079
void LoongArch64Emitter::DIV_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2080
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2081
    Write32(EncodeDJK(Opcode32::DIV_DU, rd, rj, rk));
2082
}
2083

2084
void LoongArch64Emitter::MOD_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2085
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2086
    Write32(EncodeDJK(Opcode32::MOD_DU, rd, rj, rk));
2087
}
2088

2089
void LoongArch64Emitter::SLL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2090
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2091
    Write32(EncodeDJK(Opcode32::SLL_W, rd, rj, rk));
2092
}
2093

2094
void LoongArch64Emitter::SRL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2095
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2096
    Write32(EncodeDJK(Opcode32::SRL_W, rd, rj, rk));
2097
}
2098

2099
void LoongArch64Emitter::SRA_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2100
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2101
    Write32(EncodeDJK(Opcode32::SRA_W, rd, rj, rk));
2102
}
2103

2104
void LoongArch64Emitter::ROTR_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2105
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2106
    Write32(EncodeDJK(Opcode32::ROTR_W, rd, rj, rk));
2107
}
2108

2109
void LoongArch64Emitter::SLLI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) {
2110
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2111
    Write32(EncodeDJUk5(Opcode32::SLLI_W, rd, rj, ui5));
2112
}
2113

2114
void LoongArch64Emitter::SRLI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) {
2115
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2116
    Write32(EncodeDJUk5(Opcode32::SRLI_W, rd, rj, ui5));
2117
}
2118

2119
void LoongArch64Emitter::SRAI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) {
2120
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2121
    Write32(EncodeDJUk5(Opcode32::SRAI_W, rd, rj, ui5));
2122
}
2123

2124
void LoongArch64Emitter::ROTRI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) {
2125
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2126
    Write32(EncodeDJUk5(Opcode32::ROTRI_W, rd, rj, ui5));
2127
}
2128

2129
void LoongArch64Emitter::SLL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2130
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2131
    Write32(EncodeDJK(Opcode32::SLL_D, rd, rj, rk));
2132
}
2133

2134
void LoongArch64Emitter::SRL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2135
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2136
    Write32(EncodeDJK(Opcode32::SRL_D, rd, rj, rk));
2137
}
2138

2139
void LoongArch64Emitter::SRA_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2140
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2141
    Write32(EncodeDJK(Opcode32::SRA_D, rd, rj, rk));
2142
}
2143

2144
void LoongArch64Emitter::ROTR_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2145
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2146
    Write32(EncodeDJK(Opcode32::ROTR_D, rd, rj, rk));
2147
}
2148

2149
void LoongArch64Emitter::SLLI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) {
2150
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2151
    Write32(EncodeDJUk6(Opcode32::SLLI_D, rd, rj, ui6));
2152
}
2153

2154
void LoongArch64Emitter::SRLI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) {
2155
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2156
    Write32(EncodeDJUk6(Opcode32::SRLI_D, rd, rj, ui6));
2157
}
2158

2159
void LoongArch64Emitter::SRAI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) {
2160
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2161
    Write32(EncodeDJUk6(Opcode32::SRAI_D, rd, rj, ui6));
2162
}
2163

2164
void LoongArch64Emitter::ROTRI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) {
2165
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2166
    Write32(EncodeDJUk6(Opcode32::ROTRI_D, rd, rj, ui6));
2167
}
2168

2169
void LoongArch64Emitter::EXT_W_B(LoongArch64Reg rd, LoongArch64Reg rj) {
2170
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2171
    Write32(EncodeDJ(Opcode32::EXT_W_B, rd, rj));
2172
}
2173

2174
void LoongArch64Emitter::EXT_W_H(LoongArch64Reg rd, LoongArch64Reg rj) {
2175
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2176
    Write32(EncodeDJ(Opcode32::EXT_W_H, rd, rj));
2177
}
2178

2179
void LoongArch64Emitter::CLO_W(LoongArch64Reg rd, LoongArch64Reg rj) {
2180
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2181
    Write32(EncodeDJ(Opcode32::CLO_W, rd, rj));
2182
}
2183

2184
void LoongArch64Emitter::CLO_D(LoongArch64Reg rd, LoongArch64Reg rj) {
2185
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2186
    Write32(EncodeDJ(Opcode32::CLO_D, rd, rj));
2187
}
2188

2189
void LoongArch64Emitter::CLZ_W(LoongArch64Reg rd, LoongArch64Reg rj) {
2190
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2191
    Write32(EncodeDJ(Opcode32::CLZ_W, rd, rj));
2192
}
2193

2194
void LoongArch64Emitter::CLZ_D(LoongArch64Reg rd, LoongArch64Reg rj) {
2195
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2196
    Write32(EncodeDJ(Opcode32::CLZ_D, rd, rj));
2197
}
2198

2199
void LoongArch64Emitter::CTO_W(LoongArch64Reg rd, LoongArch64Reg rj) {
2200
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2201
    Write32(EncodeDJ(Opcode32::CTO_W, rd, rj));
2202
}
2203

2204
void LoongArch64Emitter::CTO_D(LoongArch64Reg rd, LoongArch64Reg rj) {
2205
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2206
    Write32(EncodeDJ(Opcode32::CTO_D, rd, rj));
2207
}
2208

2209
void LoongArch64Emitter::CTZ_W(LoongArch64Reg rd, LoongArch64Reg rj) {
2210
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2211
    Write32(EncodeDJ(Opcode32::CTZ_W, rd, rj));
2212
}
2213

2214
void LoongArch64Emitter::CTZ_D(LoongArch64Reg rd, LoongArch64Reg rj) {
2215
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2216
    Write32(EncodeDJ(Opcode32::CTZ_D, rd, rj));
2217
}
2218

2219
void LoongArch64Emitter::BYTEPICK_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) {
2220
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2221
    Write32(EncodeDJKUa2(Opcode32::BYTEPICK_W, rd, rj, rk, sa2));
2222
}
2223

2224
void LoongArch64Emitter::BYTEPICK_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa3) {
2225
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2226
    Write32(EncodeDJKUa2(Opcode32::BYTEPICK_D, rd, rj, rk, sa3));
2227
}
2228

2229
void LoongArch64Emitter::REVB_2H(LoongArch64Reg rd, LoongArch64Reg rj) {
2230
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2231
    Write32(EncodeDJ(Opcode32::REVB_2H, rd, rj));
2232
}
2233

2234
void LoongArch64Emitter::REVB_4H(LoongArch64Reg rd, LoongArch64Reg rj) {
2235
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2236
    Write32(EncodeDJ(Opcode32::REVB_4H, rd, rj));
2237
}
2238

2239
void LoongArch64Emitter::REVB_2W(LoongArch64Reg rd, LoongArch64Reg rj) {
2240
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2241
    Write32(EncodeDJ(Opcode32::REVB_2W, rd, rj));
2242
}
2243

2244
void LoongArch64Emitter::REVB_D(LoongArch64Reg rd, LoongArch64Reg rj) {
2245
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2246
    Write32(EncodeDJ(Opcode32::REVB_D, rd, rj));
2247
}
2248

2249
void LoongArch64Emitter::BITREV_4B(LoongArch64Reg rd, LoongArch64Reg rj) {
2250
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2251
    Write32(EncodeDJ(Opcode32::BITREV_4B, rd, rj));
2252
}
2253

2254
void LoongArch64Emitter::BITREV_8B(LoongArch64Reg rd, LoongArch64Reg rj) {
2255
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2256
    Write32(EncodeDJ(Opcode32::BITREV_8B, rd, rj));
2257
}
2258

2259
void LoongArch64Emitter::BITREV_W(LoongArch64Reg rd, LoongArch64Reg rj) {
2260
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2261
    Write32(EncodeDJ(Opcode32::BITREV_W, rd, rj));
2262
}
2263

2264
void LoongArch64Emitter::BITREV_D(LoongArch64Reg rd, LoongArch64Reg rj) {
2265
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2266
    Write32(EncodeDJ(Opcode32::BITREV_D, rd, rj));
2267
}
2268

2269
void LoongArch64Emitter::BSTRINS_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbw, u8 lsbw) {
2270
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2271
    Write32(EncodeDJUk5Um5(Opcode32::BSTRINS_W, rd, rj, msbw, lsbw));
2272
}
2273

2274
void LoongArch64Emitter::BSTRINS_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbd, u8 lsbd) {
2275
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2276
    Write32(EncodeDJUk6Um6(Opcode32::BSTRINS_D, rd, rj, msbd, lsbd));
2277
}
2278

2279
void LoongArch64Emitter::BSTRPICK_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbw, u8 lsbw) {
2280
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2281
    Write32(EncodeDJUk5Um5(Opcode32::BSTRPICK_W, rd, rj, msbw, lsbw));
2282
}
2283

2284
void LoongArch64Emitter::BSTRPICK_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbd, u8 lsbd) {
2285
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2286
    Write32(EncodeDJUk6Um6(Opcode32::BSTRPICK_D, rd, rj, msbd, lsbd));
2287
}
2288

2289
void LoongArch64Emitter::MASKEQZ(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2290
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2291
    Write32(EncodeDJK(Opcode32::MASKEQZ, rd, rj, rk));
2292
}
2293

2294
void LoongArch64Emitter::MASKNEZ(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2295
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2296
    Write32(EncodeDJK(Opcode32::MASKNEZ, rd, rj, rk));
2297
}
2298

2299
void LoongArch64Emitter::BEQ(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) {
2300
    _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2301
    _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2302
	ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2303
	Write32(EncodeJDSk16ps2(Opcode32::BEQ, rj, rd, (s32)distance));
2304
}
2305

2306
void LoongArch64Emitter::BNE(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) {
2307
    _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2308
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2309
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2310
	Write32(EncodeJDSk16ps2(Opcode32::BNE, rj, rd, (s32)distance));
2311
}
2312

2313
void LoongArch64Emitter::BLT(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) {
2314
    _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2315
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2316
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2317
	Write32(EncodeJDSk16ps2(Opcode32::BLT, rj, rd, (s32)distance));
2318
}
2319

2320
void LoongArch64Emitter::BGE(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) {
2321
    _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2322
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2323
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2324
	Write32(EncodeJDSk16ps2(Opcode32::BGE, rj, rd, (s32)distance));
2325
}
2326

2327
void LoongArch64Emitter::BLTU(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) {
2328
    _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2329
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2330
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2331
	Write32(EncodeJDSk16ps2(Opcode32::BLTU, rj, rd, (s32)distance));
2332
}
2333

2334
void LoongArch64Emitter::BGEU(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) {
2335
    _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2336
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2337
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2338
	Write32(EncodeJDSk16ps2(Opcode32::BGEU, rj, rd, (s32)distance));
2339
}
2340

2341
FixupBranch LoongArch64Emitter::BEQ(LoongArch64Reg rj, LoongArch64Reg rd) {
2342
	FixupBranch fixup{ GetCodePointer(), FixupBranchType::B };
2343
	Write32(EncodeJDSk16ps2(Opcode32::BEQ, rj, rd, 0));
2344
	return fixup;
2345
}
2346

2347
FixupBranch LoongArch64Emitter::BNE(LoongArch64Reg rj, LoongArch64Reg rd) {
2348
	FixupBranch fixup{ GetCodePointer(), FixupBranchType::B };
2349
	Write32(EncodeJDSk16ps2(Opcode32::BNE, rj, rd, 0));
2350
	return fixup;
2351
}
2352

2353
FixupBranch LoongArch64Emitter::BLT(LoongArch64Reg rj, LoongArch64Reg rd) {
2354
	FixupBranch fixup{ GetCodePointer(), FixupBranchType::B };
2355
	Write32(EncodeJDSk16ps2(Opcode32::BLT, rj, rd, 0));
2356
	return fixup;
2357
}
2358

2359
FixupBranch LoongArch64Emitter::BGE(LoongArch64Reg rj, LoongArch64Reg rd) {
2360
	FixupBranch fixup{ GetCodePointer(), FixupBranchType::B };
2361
	Write32(EncodeJDSk16ps2(Opcode32::BGE, rj, rd, 0));
2362
	return fixup;
2363
}
2364

2365
FixupBranch LoongArch64Emitter::BLTU(LoongArch64Reg rj, LoongArch64Reg rd) {
2366
	FixupBranch fixup{ GetCodePointer(), FixupBranchType::B };
2367
	Write32(EncodeJDSk16ps2(Opcode32::BLTU, rj, rd, 0));
2368
	return fixup;
2369
}
2370

2371
FixupBranch LoongArch64Emitter::BGEU(LoongArch64Reg rj, LoongArch64Reg rd) {
2372
	FixupBranch fixup{ GetCodePointer(), FixupBranchType::B };
2373
	Write32(EncodeJDSk16ps2(Opcode32::BGEU, rj, rd, 0));
2374
	return fixup;
2375
}
2376

2377
void LoongArch64Emitter::BEQZ(LoongArch64Reg rj, const void *dst) {
2378
    _assert_msg_(BranchZeroInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2379
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2380
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2381
	Write32(EncodeJSd5k16(Opcode32::BEQZ, rj, (s32)distance));
2382
}
2383

2384
void LoongArch64Emitter::BNEZ(LoongArch64Reg rj, const void *dst) {
2385
    _assert_msg_(BranchZeroInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2386
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2387
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2388
	Write32(EncodeJSd5k16(Opcode32::BNEZ, rj, (s32)distance));
2389
}
2390

2391
FixupBranch LoongArch64Emitter::BEQZ(LoongArch64Reg rj) {
2392
    FixupBranch fixup{ GetCodePointer(), FixupBranchType::BZ };
2393
	Write32(EncodeJSd5k16(Opcode32::BEQZ, rj, 0));
2394
	return fixup;
2395
}
2396

2397
FixupBranch LoongArch64Emitter::BNEZ(LoongArch64Reg rj) {
2398
    FixupBranch fixup{ GetCodePointer(), FixupBranchType::BZ };
2399
	Write32(EncodeJSd5k16(Opcode32::BNEZ, rj, 0));
2400
	return fixup;
2401
}
2402

2403
void LoongArch64Emitter::B(const void *dst) {
2404
    _assert_msg_(JumpInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2405
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2406
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2407
    Write32(EncodeSd10k16ps2(Opcode32::B, (s32)distance));
2408
}
2409

2410
void LoongArch64Emitter::BL(const void *dst) {
2411
    _assert_msg_(JumpInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst);
2412
	_assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__);
2413
    ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer();
2414
    Write32(EncodeSd10k16ps2(Opcode32::BL, (s32)distance));
2415
}
2416

2417
FixupBranch LoongArch64Emitter::B() {
2418
    FixupBranch fixup{ GetCodePointer(), FixupBranchType::J };
2419
	Write32(EncodeSd10k16ps2(Opcode32::B, 0));
2420
	return fixup;
2421
}
2422

2423
FixupBranch LoongArch64Emitter::BL() {
2424
    FixupBranch fixup{ GetCodePointer(), FixupBranchType::J };
2425
	Write32(EncodeSd10k16ps2(Opcode32::BL, 0));
2426
	return fixup;
2427
}
2428

2429
void LoongArch64Emitter::JIRL(LoongArch64Reg rd, LoongArch64Reg rj, s32 offs16) {
2430
    Write32(EncodeDJSk16ps2(Opcode32::JIRL, rd, rj, offs16));
2431
}
2432

2433
void LoongArch64Emitter::LD_B(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2434
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2435
    Write32(EncodeDJSk12(Opcode32::LD_B, rd, rj, si12));
2436
}
2437

2438
void LoongArch64Emitter::LD_H(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2439
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2440
    Write32(EncodeDJSk12(Opcode32::LD_H, rd, rj, si12));
2441
}
2442

2443
void LoongArch64Emitter::LD_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2444
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2445
    Write32(EncodeDJSk12(Opcode32::LD_W, rd, rj, si12));
2446
}
2447

2448
void LoongArch64Emitter::LD_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2449
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2450
    Write32(EncodeDJSk12(Opcode32::LD_D, rd, rj, si12));
2451
}
2452

2453
void LoongArch64Emitter::LD_BU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2454
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2455
    Write32(EncodeDJSk12(Opcode32::LD_BU, rd, rj, si12));
2456
}
2457

2458
void LoongArch64Emitter::LD_HU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2459
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2460
    Write32(EncodeDJSk12(Opcode32::LD_HU, rd, rj, si12));
2461
}
2462

2463
void LoongArch64Emitter::LD_WU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2464
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2465
    Write32(EncodeDJSk12(Opcode32::LD_WU, rd, rj, si12));
2466
}
2467

2468
void LoongArch64Emitter::ST_B(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2469
    Write32(EncodeDJSk12(Opcode32::ST_B, rd, rj, si12));
2470
}
2471

2472
void LoongArch64Emitter::ST_H(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2473
    Write32(EncodeDJSk12(Opcode32::ST_H, rd, rj, si12));
2474
}
2475

2476
void LoongArch64Emitter::ST_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2477
    Write32(EncodeDJSk12(Opcode32::ST_W, rd, rj, si12));
2478
}
2479

2480
void LoongArch64Emitter::ST_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) {
2481
    Write32(EncodeDJSk12(Opcode32::ST_D, rd, rj, si12));
2482
}
2483

2484
void LoongArch64Emitter::LDX_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2485
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2486
    Write32(EncodeDJK(Opcode32::LDX_B, rd, rj, rk));
2487
}
2488

2489
void LoongArch64Emitter::LDX_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2490
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2491
    Write32(EncodeDJK(Opcode32::LDX_H, rd, rj, rk));
2492
}
2493

2494
void LoongArch64Emitter::LDX_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2495
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2496
    Write32(EncodeDJK(Opcode32::LDX_W, rd, rj, rk));
2497
}
2498

2499
void LoongArch64Emitter::LDX_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2500
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2501
    Write32(EncodeDJK(Opcode32::LDX_D, rd, rj, rk));
2502
}
2503

2504
void LoongArch64Emitter::LDX_BU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2505
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2506
    Write32(EncodeDJK(Opcode32::LDX_BU, rd, rj, rk));
2507
}
2508

2509
void LoongArch64Emitter::LDX_HU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2510
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2511
    Write32(EncodeDJK(Opcode32::LDX_HU, rd, rj, rk));
2512
}
2513

2514
void LoongArch64Emitter::LDX_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2515
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2516
    Write32(EncodeDJK(Opcode32::LDX_WU, rd, rj, rk));
2517
}
2518

2519
void LoongArch64Emitter::STX_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2520
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2521
    Write32(EncodeDJK(Opcode32::STX_B, rd, rj, rk));
2522
}
2523

2524
void LoongArch64Emitter::STX_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2525
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2526
    Write32(EncodeDJK(Opcode32::STX_H, rd, rj, rk));
2527
}
2528

2529
void LoongArch64Emitter::STX_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2530
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2531
    Write32(EncodeDJK(Opcode32::STX_W, rd, rj, rk));
2532
}
2533

2534
void LoongArch64Emitter::STX_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2535
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2536
    Write32(EncodeDJK(Opcode32::STX_D, rd, rj, rk));
2537
}
2538

2539
void LoongArch64Emitter::LDPTR_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) {
2540
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2541
    Write32(EncodeDJSk14ps2(Opcode32::LDPTR_W, rd, rj, si14));
2542
}
2543

2544
void LoongArch64Emitter::LDPTR_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) {
2545
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2546
    Write32(EncodeDJSk14ps2(Opcode32::LDPTR_W, rd, rj, si14));
2547
}
2548

2549
void LoongArch64Emitter::STPTR_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) {
2550
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2551
    Write32(EncodeDJSk14ps2(Opcode32::LDPTR_W, rd, rj, si14));
2552
}
2553

2554
void LoongArch64Emitter::STPTR_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) {
2555
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2556
    Write32(EncodeDJSk14ps2(Opcode32::LDPTR_W, rd, rj, si14));
2557
}
2558

2559
void LoongArch64Emitter::PRELD(u32 hint, LoongArch64Reg rj, s16 si12) {
2560
    _assert_msg_(rj != R_ZERO, "%s load from zero is a HINT", __func__);
2561
    _assert_msg_(hint == 0 || hint == 8, "%s hint represents a NOP", __func__);
2562
    Write32(EncodeUd5JSk12(Opcode32::PRELD, hint, rj, si12));
2563
}
2564

2565
void LoongArch64Emitter::PRELDX(u32 hint, LoongArch64Reg rj, LoongArch64Reg rk) {
2566
    _assert_msg_(rj != R_ZERO, "%s load from zero is a HINT", __func__);
2567
    _assert_msg_(hint == 0 || hint == 8, "%s hint represents a NOP", __func__);
2568
    Write32(EncodeUd5JK(Opcode32::PRELDX, hint, rj, rk));
2569
}
2570

2571
void LoongArch64Emitter::LDGT_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2572
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2573
    Write32(EncodeDJK(Opcode32::LDGT_B, rd, rj, rk));
2574
}
2575

2576
void LoongArch64Emitter::LDGT_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2577
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2578
    Write32(EncodeDJK(Opcode32::LDGT_H, rd, rj, rk));
2579
}
2580

2581
void LoongArch64Emitter::LDGT_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2582
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2583
    Write32(EncodeDJK(Opcode32::LDGT_W, rd, rj, rk));
2584
}
2585

2586
void LoongArch64Emitter::LDGT_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2587
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2588
    Write32(EncodeDJK(Opcode32::LDGT_D, rd, rj, rk));
2589
}
2590

2591
void LoongArch64Emitter::LDLE_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2592
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2593
    Write32(EncodeDJK(Opcode32::LDLE_B, rd, rj, rk));
2594
}
2595

2596
void LoongArch64Emitter::LDLE_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2597
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2598
    Write32(EncodeDJK(Opcode32::LDLE_H, rd, rj, rk));
2599
}
2600

2601
void LoongArch64Emitter::LDLE_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2602
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2603
    Write32(EncodeDJK(Opcode32::LDLE_W, rd, rj, rk));
2604
}
2605

2606
void LoongArch64Emitter::LDLE_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2607
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2608
    Write32(EncodeDJK(Opcode32::LDLE_D, rd, rj, rk));
2609
}
2610

2611
void LoongArch64Emitter::STGT_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2612
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2613
    Write32(EncodeDJK(Opcode32::STGT_B, rd, rj, rk));
2614
}
2615

2616
void LoongArch64Emitter::STGT_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2617
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2618
    Write32(EncodeDJK(Opcode32::STGT_H, rd, rj, rk));
2619
}
2620

2621
void LoongArch64Emitter::STGT_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2622
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2623
    Write32(EncodeDJK(Opcode32::STGT_W, rd, rj, rk));
2624
}
2625

2626
void LoongArch64Emitter::STGT_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2627
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2628
    Write32(EncodeDJK(Opcode32::STGT_D, rd, rj, rk));
2629
}
2630

2631
void LoongArch64Emitter::STLE_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2632
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2633
    Write32(EncodeDJK(Opcode32::STLE_B, rd, rj, rk));
2634
}
2635

2636
void LoongArch64Emitter::STLE_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2637
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2638
    Write32(EncodeDJK(Opcode32::STLE_H, rd, rj, rk));
2639
}
2640

2641
void LoongArch64Emitter::STLE_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2642
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2643
    Write32(EncodeDJK(Opcode32::STLE_W, rd, rj, rk));
2644
}
2645

2646
void LoongArch64Emitter::STLE_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) {
2647
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2648
    Write32(EncodeDJK(Opcode32::STLE_D, rd, rj, rk));
2649
}
2650

2651
void LoongArch64Emitter::AMSWAP_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2652
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2653
    Write32(EncodeDKJ(Opcode32::AMSWAP_W, rd, rk, rj));
2654
}
2655

2656
void LoongArch64Emitter::AMSWAP_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2657
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2658
    Write32(EncodeDKJ(Opcode32::AMSWAP_DB_W, rd, rk, rj));
2659
}
2660

2661
void LoongArch64Emitter::AMSWAP_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2662
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2663
    Write32(EncodeDKJ(Opcode32::AMSWAP_D, rd, rk, rj));
2664
}
2665

2666
void LoongArch64Emitter::AMSWAP_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2667
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2668
    Write32(EncodeDKJ(Opcode32::AMSWAP_DB_D, rd, rk, rj));
2669
}
2670

2671
void LoongArch64Emitter::AMADD_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2672
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2673
    Write32(EncodeDKJ(Opcode32::AMADD_W, rd, rk, rj));
2674
}
2675

2676
void LoongArch64Emitter::AMADD_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2677
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2678
    Write32(EncodeDKJ(Opcode32::AMADD_DB_W, rd, rk, rj));
2679
}
2680

2681
void LoongArch64Emitter::AMADD_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2682
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2683
    Write32(EncodeDKJ(Opcode32::AMADD_D, rd, rk, rj));
2684
}
2685

2686
void LoongArch64Emitter::AMADD_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2687
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2688
    Write32(EncodeDKJ(Opcode32::AMADD_DB_D, rd, rk, rj));
2689
}
2690

2691
void LoongArch64Emitter::AMAND_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2692
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2693
    Write32(EncodeDKJ(Opcode32::AMAND_W, rd, rk, rj));
2694
}
2695

2696
void LoongArch64Emitter::AMAND_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2697
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2698
    Write32(EncodeDKJ(Opcode32::AMAND_DB_W, rd, rk, rj));
2699
}
2700

2701
void LoongArch64Emitter::AMAND_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2702
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2703
    Write32(EncodeDKJ(Opcode32::AMAND_D, rd, rk, rj));
2704
}
2705

2706
void LoongArch64Emitter::AMAND_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2707
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2708
    Write32(EncodeDKJ(Opcode32::AMAND_DB_D, rd, rk, rj));
2709
}
2710

2711
void LoongArch64Emitter::AMOR_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2712
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2713
    Write32(EncodeDKJ(Opcode32::AMOR_W, rd, rk, rj));
2714
}
2715

2716
void LoongArch64Emitter::AMOR_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2717
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2718
    Write32(EncodeDKJ(Opcode32::AMOR_DB_W, rd, rk, rj));
2719
}
2720

2721
void LoongArch64Emitter::AMOR_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2722
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2723
    Write32(EncodeDKJ(Opcode32::AMOR_D, rd, rk, rj));
2724
}
2725

2726
void LoongArch64Emitter::AMOR_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2727
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2728
    Write32(EncodeDKJ(Opcode32::AMOR_DB_D, rd, rk, rj));
2729
}
2730

2731
void LoongArch64Emitter::AMXOR_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2732
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2733
    Write32(EncodeDKJ(Opcode32::AMXOR_W, rd, rk, rj));
2734
}
2735

2736
void LoongArch64Emitter::AMXOR_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2737
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2738
    Write32(EncodeDKJ(Opcode32::AMXOR_DB_W, rd, rk, rj));
2739
}
2740

2741
void LoongArch64Emitter::AMXOR_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2742
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2743
    Write32(EncodeDKJ(Opcode32::AMXOR_D, rd, rk, rj));
2744
}
2745

2746
void LoongArch64Emitter::AMXOR_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2747
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2748
    Write32(EncodeDKJ(Opcode32::AMXOR_DB_D, rd, rk, rj));
2749
}
2750

2751
void LoongArch64Emitter::AMMAX_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2752
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2753
    Write32(EncodeDKJ(Opcode32::AMMAX_W, rd, rk, rj));
2754
}
2755

2756
void LoongArch64Emitter::AMMAX_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2757
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2758
    Write32(EncodeDKJ(Opcode32::AMMAX_DB_W, rd, rk, rj));
2759
}
2760

2761
void LoongArch64Emitter::AMMAX_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2762
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2763
    Write32(EncodeDKJ(Opcode32::AMMAX_D, rd, rk, rj));
2764
}
2765

2766
void LoongArch64Emitter::AMMAX_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2767
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2768
    Write32(EncodeDKJ(Opcode32::AMMAX_DB_D, rd, rk, rj));
2769
}
2770

2771
void LoongArch64Emitter::AMMIN_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2772
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2773
    Write32(EncodeDKJ(Opcode32::AMMIN_W, rd, rk, rj));
2774
}
2775

2776
void LoongArch64Emitter::AMMIN_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2777
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2778
    Write32(EncodeDKJ(Opcode32::AMMIN_DB_W, rd, rk, rj));
2779
}
2780

2781
void LoongArch64Emitter::AMMIN_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2782
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2783
    Write32(EncodeDKJ(Opcode32::AMMIN_D, rd, rk, rj));
2784
}
2785

2786
void LoongArch64Emitter::AMMIN_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2787
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2788
    Write32(EncodeDKJ(Opcode32::AMMIN_DB_D, rd, rk, rj));
2789
}
2790

2791
void LoongArch64Emitter::AMMAX_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2792
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2793
    Write32(EncodeDKJ(Opcode32::AMMAX_WU, rd, rk, rj));
2794
}
2795

2796
void LoongArch64Emitter::AMMAX_DB_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2797
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2798
    Write32(EncodeDKJ(Opcode32::AMMAX_DB_WU, rd, rk, rj));
2799
}
2800

2801
void LoongArch64Emitter::AMMAX_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2802
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2803
    Write32(EncodeDKJ(Opcode32::AMMAX_DU, rd, rk, rj));
2804
}
2805

2806
void LoongArch64Emitter::AMMAX_DB_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2807
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2808
    Write32(EncodeDKJ(Opcode32::AMMAX_DB_DU, rd, rk, rj));
2809
}
2810

2811
void LoongArch64Emitter::AMMIN_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2812
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2813
    Write32(EncodeDKJ(Opcode32::AMMIN_WU, rd, rk, rj));
2814
}
2815

2816
void LoongArch64Emitter::AMMIN_DB_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2817
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2818
    Write32(EncodeDKJ(Opcode32::AMMIN_DB_WU, rd, rk, rj));
2819
}
2820

2821
void LoongArch64Emitter::AMMIN_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2822
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2823
    Write32(EncodeDKJ(Opcode32::AMMIN_DU, rd, rk, rj));
2824
}
2825

2826
void LoongArch64Emitter::AMMIN_DB_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2827
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2828
    Write32(EncodeDKJ(Opcode32::AMMIN_DB_DU, rd, rk, rj));
2829
}
2830

2831
void LoongArch64Emitter::AMSWAP_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2832
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2833
    Write32(EncodeDKJ(Opcode32::AMSWAP_B, rd, rk, rj));
2834
}
2835

2836
void LoongArch64Emitter::AMSWAP_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2837
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2838
    Write32(EncodeDKJ(Opcode32::AMSWAP_DB_B, rd, rk, rj));
2839
}
2840

2841
void LoongArch64Emitter::AMSWAP_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2842
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2843
    Write32(EncodeDKJ(Opcode32::AMSWAP_H, rd, rk, rj));
2844
}
2845

2846
void LoongArch64Emitter::AMSWAP_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2847
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2848
    Write32(EncodeDKJ(Opcode32::AMSWAP_DB_H, rd, rk, rj));
2849
}
2850

2851
void LoongArch64Emitter::AMADD_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2852
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2853
    Write32(EncodeDKJ(Opcode32::AMADD_B, rd, rk, rj));
2854
}
2855

2856
void LoongArch64Emitter::AMADD_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2857
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2858
    Write32(EncodeDKJ(Opcode32::AMADD_DB_B, rd, rk, rj));
2859
}
2860

2861
void LoongArch64Emitter::AMADD_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2862
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2863
    Write32(EncodeDKJ(Opcode32::AMADD_H, rd, rk, rj));
2864
}
2865

2866
void LoongArch64Emitter::AMADD_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2867
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2868
    Write32(EncodeDKJ(Opcode32::AMADD_DB_H, rd, rk, rj));
2869
}
2870

2871
void LoongArch64Emitter::AMCAS_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2872
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2873
    Write32(EncodeDKJ(Opcode32::AMCAS_B, rd, rk, rj));
2874
}
2875

2876
void LoongArch64Emitter::AMCAS_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2877
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2878
    Write32(EncodeDKJ(Opcode32::AMCAS_DB_B, rd, rk, rj));
2879
}
2880

2881
void LoongArch64Emitter::AMCAS_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2882
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2883
    Write32(EncodeDKJ(Opcode32::AMCAS_H, rd, rk, rj));
2884
}
2885

2886
void LoongArch64Emitter::AMCAS_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2887
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2888
    Write32(EncodeDKJ(Opcode32::AMCAS_DB_H, rd, rk, rj));
2889
}
2890

2891
void LoongArch64Emitter::AMCAS_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2892
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2893
    Write32(EncodeDKJ(Opcode32::AMCAS_W, rd, rk, rj));
2894
}
2895

2896
void LoongArch64Emitter::AMCAS_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2897
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2898
    Write32(EncodeDKJ(Opcode32::AMCAS_DB_W, rd, rk, rj));
2899
}
2900

2901
void LoongArch64Emitter::AMCAS_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2902
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2903
    Write32(EncodeDKJ(Opcode32::AMCAS_D, rd, rk, rj));
2904
}
2905

2906
void LoongArch64Emitter::AMCAS_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2907
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2908
    Write32(EncodeDKJ(Opcode32::AMCAS_DB_D, rd, rk, rj));
2909
}
2910

2911
void LoongArch64Emitter::CRC_W_B_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2912
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2913
    Write32(EncodeDKJ(Opcode32::CRC_W_B_W, rd, rk, rj));
2914
}
2915

2916
void LoongArch64Emitter::CRC_W_H_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2917
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2918
    Write32(EncodeDKJ(Opcode32::CRC_W_H_W, rd, rk, rj));
2919
}
2920

2921
void LoongArch64Emitter::CRC_W_W_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2922
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2923
    Write32(EncodeDKJ(Opcode32::CRC_W_W_W, rd, rk, rj));
2924
}
2925

2926
void LoongArch64Emitter::CRC_W_D_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2927
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2928
    Write32(EncodeDKJ(Opcode32::CRC_W_D_W, rd, rk, rj));
2929
}
2930

2931
void LoongArch64Emitter::CRCC_W_B_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2932
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2933
    Write32(EncodeDKJ(Opcode32::CRCC_W_B_W, rd, rk, rj));
2934
}
2935

2936
void LoongArch64Emitter::CRCC_W_H_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2937
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2938
    Write32(EncodeDKJ(Opcode32::CRCC_W_H_W, rd, rk, rj));
2939
}
2940

2941
void LoongArch64Emitter::CRCC_W_W_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2942
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2943
    Write32(EncodeDKJ(Opcode32::CRCC_W_W_W, rd, rk, rj));
2944
}
2945

2946
void LoongArch64Emitter::CRCC_W_D_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) {
2947
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2948
    Write32(EncodeDKJ(Opcode32::CRCC_W_D_W, rd, rk, rj));
2949
}
2950

2951
void LoongArch64Emitter::SYSCALL(u16 code) {
2952
    Write32(EncodeUd15(Opcode32::SYSCALL, code));
2953
}
2954

2955
void LoongArch64Emitter::BREAK(u16 code) {
2956
    Write32(EncodeUd15(Opcode32::BREAK, code));
2957
}
2958

2959
void LoongArch64Emitter::ASRTLE_D(LoongArch64Reg rj, LoongArch64Reg rk) {
2960
    Write32(EncodeJK(Opcode32::ASRTLE_D, rj, rk));
2961
}
2962

2963
void LoongArch64Emitter::ASRTGT_D(LoongArch64Reg rj, LoongArch64Reg rk) {
2964
    Write32(EncodeJK(Opcode32::ASRTGT_D, rj, rk));
2965
}
2966

2967
void LoongArch64Emitter::RDTIMEL_W(LoongArch64Reg rd, LoongArch64Reg rj) {
2968
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2969
    Write32(EncodeDJ(Opcode32::RDTIMEL_W, rd, rj));
2970
}
2971

2972
void LoongArch64Emitter::RDTIMEH_W(LoongArch64Reg rd, LoongArch64Reg rj) {
2973
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2974
    Write32(EncodeDJ(Opcode32::RDTIMEH_W, rd, rj));
2975
}
2976

2977
void LoongArch64Emitter::RDTIME_D(LoongArch64Reg rd, LoongArch64Reg rj) {
2978
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2979
    Write32(EncodeDJ(Opcode32::RDTIME_D, rd, rj));
2980
}
2981

2982
void LoongArch64Emitter::CPUCFG(LoongArch64Reg rd, LoongArch64Reg rj) {
2983
    _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__);
2984
    Write32(EncodeDJ(Opcode32::CPUCFG, rd, rj));
2985
}
2986

2987
void LoongArch64Emitter::FADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
2988
    Write32(EncodeFdFjFk(Opcode32::FADD_S, fd, fj, fk));
2989
}
2990

2991
void LoongArch64Emitter::FADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
2992
    Write32(EncodeFdFjFk(Opcode32::FADD_D, fd, fj, fk));
2993
}
2994

2995
void LoongArch64Emitter::FSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
2996
    Write32(EncodeFdFjFk(Opcode32::FSUB_S, fd, fj, fk));
2997
}
2998

2999
void LoongArch64Emitter::FSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3000
    Write32(EncodeFdFjFk(Opcode32::FSUB_D, fd, fj, fk));
3001
}
3002

3003
void LoongArch64Emitter::FMUL_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3004
    Write32(EncodeFdFjFk(Opcode32::FMUL_S, fd, fj, fk));
3005
}
3006

3007
void LoongArch64Emitter::FMUL_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3008
    Write32(EncodeFdFjFk(Opcode32::FMUL_D, fd, fj, fk));
3009
}
3010

3011
void LoongArch64Emitter::FDIV_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3012
    Write32(EncodeFdFjFk(Opcode32::FDIV_S, fd, fj, fk));
3013
}
3014

3015
void LoongArch64Emitter::FDIV_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3016
    Write32(EncodeFdFjFk(Opcode32::FDIV_D, fd, fj, fk));
3017
}
3018

3019
void LoongArch64Emitter::FMADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
3020
    Write32(EncodeFdFjFkFa(Opcode32::FMADD_S, fd, fj, fk, fa));
3021
}
3022

3023
void LoongArch64Emitter::FMADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
3024
    Write32(EncodeFdFjFkFa(Opcode32::FMADD_D, fd, fj, fk, fa));
3025
}
3026

3027
void LoongArch64Emitter::FMSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
3028
    Write32(EncodeFdFjFkFa(Opcode32::FMSUB_S, fd, fj, fk, fa));
3029
}
3030

3031
void LoongArch64Emitter::FMSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
3032
    Write32(EncodeFdFjFkFa(Opcode32::FMSUB_D, fd, fj, fk, fa));
3033
}
3034

3035
void LoongArch64Emitter::FNMADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
3036
    Write32(EncodeFdFjFkFa(Opcode32::FNMADD_S, fd, fj, fk, fa));
3037
}
3038

3039
void LoongArch64Emitter::FNMADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
3040
    Write32(EncodeFdFjFkFa(Opcode32::FNMADD_D, fd, fj, fk, fa));
3041
}
3042

3043
void LoongArch64Emitter::FNMSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
3044
    Write32(EncodeFdFjFkFa(Opcode32::FNMSUB_S, fd, fj, fk, fa));
3045
}
3046

3047
void LoongArch64Emitter::FNMSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) {
3048
    Write32(EncodeFdFjFkFa(Opcode32::FNMSUB_D, fd, fj, fk, fa));
3049
}
3050

3051
void LoongArch64Emitter::FMAX_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3052
    Write32(EncodeFdFjFk(Opcode32::FMAX_S, fd, fj, fk));
3053
}
3054

3055
void LoongArch64Emitter::FMAX_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3056
    Write32(EncodeFdFjFk(Opcode32::FMAX_D, fd, fj, fk));
3057
}
3058

3059
void LoongArch64Emitter::FMIN_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3060
    Write32(EncodeFdFjFk(Opcode32::FMIN_S, fd, fj, fk));
3061
}
3062

3063
void LoongArch64Emitter::FMIN_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3064
    Write32(EncodeFdFjFk(Opcode32::FMIN_D, fd, fj, fk));
3065
}
3066

3067
void LoongArch64Emitter::FMAXA_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3068
    Write32(EncodeFdFjFk(Opcode32::FMAXA_S, fd, fj, fk));
3069
}
3070

3071
void LoongArch64Emitter::FMAXA_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3072
    Write32(EncodeFdFjFk(Opcode32::FMAXA_D, fd, fj, fk));
3073
}
3074

3075
void LoongArch64Emitter::FMINA_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3076
    Write32(EncodeFdFjFk(Opcode32::FMINA_S, fd, fj, fk));
3077
}
3078

3079
void LoongArch64Emitter::FMINA_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3080
    Write32(EncodeFdFjFk(Opcode32::FMINA_D, fd, fj, fk));
3081
}
3082

3083
void LoongArch64Emitter::FABS_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3084
    Write32(EncodeFdFj(Opcode32::FABS_S, fd, fj));
3085
}
3086

3087
void LoongArch64Emitter::FABS_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3088
    Write32(EncodeFdFj(Opcode32::FABS_D, fd, fj));
3089
}
3090

3091
void LoongArch64Emitter::FNEG_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3092
    Write32(EncodeFdFj(Opcode32::FNEG_S, fd, fj));
3093
}
3094

3095
void LoongArch64Emitter::FNEG_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3096
    Write32(EncodeFdFj(Opcode32::FNEG_D, fd, fj));
3097
}
3098

3099
void LoongArch64Emitter::FSQRT_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3100
    Write32(EncodeFdFj(Opcode32::FSQRT_S, fd, fj));
3101
}
3102

3103
void LoongArch64Emitter::FSQRT_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3104
    Write32(EncodeFdFj(Opcode32::FSQRT_D, fd, fj));
3105
}
3106

3107
void LoongArch64Emitter::FRECIP_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3108
    Write32(EncodeFdFj(Opcode32::FRECIP_S, fd, fj));
3109
}
3110

3111
void LoongArch64Emitter::FRECIP_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3112
    Write32(EncodeFdFj(Opcode32::FRECIP_D, fd, fj));
3113
}
3114

3115
void LoongArch64Emitter::FRSQRT_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3116
    Write32(EncodeFdFj(Opcode32::FRSQRT_S, fd, fj));
3117
}
3118

3119
void LoongArch64Emitter::FRSQRT_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3120
    Write32(EncodeFdFj(Opcode32::FRSQRT_D, fd, fj));
3121
}
3122

3123
void LoongArch64Emitter::FSCALEB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3124
    Write32(EncodeFdFjFk(Opcode32::FSCALEB_S, fd, fj, fk));
3125
}
3126

3127
void LoongArch64Emitter::FSCALEB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3128
    Write32(EncodeFdFjFk(Opcode32::FSCALEB_D, fd, fj, fk));
3129
}
3130

3131
void LoongArch64Emitter::FLOGB_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3132
    Write32(EncodeFdFj(Opcode32::FLOGB_S, fd, fj));
3133
}
3134

3135
void LoongArch64Emitter::FLOGB_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3136
    Write32(EncodeFdFj(Opcode32::FLOGB_D, fd, fj));
3137
}
3138

3139
void LoongArch64Emitter::FCOPYSIGN_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3140
    Write32(EncodeFdFjFk(Opcode32::FCOPYSIGN_S, fd, fj, fk));
3141
}
3142

3143
void LoongArch64Emitter::FCOPYSIGN_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) {
3144
    Write32(EncodeFdFjFk(Opcode32::FCOPYSIGN_D, fd, fj, fk));
3145
}
3146

3147
void LoongArch64Emitter::FCLASS_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3148
    Write32(EncodeFdFj(Opcode32::FCLASS_S, fd, fj));
3149
}
3150

3151
void LoongArch64Emitter::FCLASS_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3152
    Write32(EncodeFdFj(Opcode32::FCLASS_D, fd, fj));
3153
}
3154

3155
void LoongArch64Emitter::FRECIPE_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3156
    Write32(EncodeFdFj(Opcode32::FRECIPE_S, fd, fj));
3157
}
3158

3159
void LoongArch64Emitter::FRECIPE_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3160
    Write32(EncodeFdFj(Opcode32::FRECIPE_D, fd, fj));
3161
}
3162

3163
void LoongArch64Emitter::FRSQRTE_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3164
    Write32(EncodeFdFj(Opcode32::FRSQRTE_S, fd, fj));
3165
}
3166

3167
void LoongArch64Emitter::FRSQRTE_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3168
    Write32(EncodeFdFj(Opcode32::FRSQRTE_D, fd, fj));
3169
}
3170

3171
void LoongArch64Emitter::FCMP_COND_S(LoongArch64CFR cd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Fcond cond) {
3172
    Write32(EncodeCdFjFkFcond(Opcode32::FCMP_COND_S, cd, fj, fk, cond));
3173
}
3174

3175
void LoongArch64Emitter::FCMP_COND_D(LoongArch64CFR cd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Fcond cond) {
3176
    Write32(EncodeCdFjFkFcond(Opcode32::FCMP_COND_D, cd, fj, fk, cond));
3177
}
3178

3179
void LoongArch64Emitter::FCVT_S_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3180
    Write32(EncodeFdFj(Opcode32::FCVT_S_D, fd, fj));
3181
}
3182

3183
void LoongArch64Emitter::FCVT_D_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3184
    Write32(EncodeFdFj(Opcode32::FCVT_D_S, fd, fj));
3185
}
3186

3187
void LoongArch64Emitter::FFINT_S_W(LoongArch64Reg fd, LoongArch64Reg fj) {
3188
    Write32(EncodeFdFj(Opcode32::FFINT_S_W, fd, fj));
3189
}
3190

3191
void LoongArch64Emitter::FFINT_S_L(LoongArch64Reg fd, LoongArch64Reg fj) {
3192
    Write32(EncodeFdFj(Opcode32::FFINT_S_L, fd, fj));
3193
}
3194

3195
void LoongArch64Emitter::FFINT_D_W(LoongArch64Reg fd, LoongArch64Reg fj) {
3196
    Write32(EncodeFdFj(Opcode32::FFINT_D_W, fd, fj));
3197
}
3198

3199
void LoongArch64Emitter::FFINT_D_L(LoongArch64Reg fd, LoongArch64Reg fj) {
3200
    Write32(EncodeFdFj(Opcode32::FFINT_D_L, fd, fj));
3201
}
3202

3203
void LoongArch64Emitter::FTINT_W_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3204
    Write32(EncodeFdFj(Opcode32::FTINT_W_S, fd, fj));
3205
}
3206

3207
void LoongArch64Emitter::FTINT_W_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3208
    Write32(EncodeFdFj(Opcode32::FTINT_W_D, fd, fj));
3209
}
3210

3211
void LoongArch64Emitter::FTINT_L_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3212
    Write32(EncodeFdFj(Opcode32::FTINT_L_S, fd, fj));
3213
}
3214

3215
void LoongArch64Emitter::FTINT_L_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3216
    Write32(EncodeFdFj(Opcode32::FTINT_L_D, fd, fj));
3217
}
3218

3219
void LoongArch64Emitter::FTINTRM_W_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3220
    Write32(EncodeFdFj(Opcode32::FTINTRM_W_S, fd, fj));
3221
}
3222

3223
void LoongArch64Emitter::FTINTRM_W_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3224
    Write32(EncodeFdFj(Opcode32::FTINTRM_W_D, fd, fj));
3225
}
3226

3227
void LoongArch64Emitter::FTINTRM_L_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3228
    Write32(EncodeFdFj(Opcode32::FTINTRM_L_S, fd, fj));
3229
}
3230

3231
void LoongArch64Emitter::FTINTRM_L_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3232
    Write32(EncodeFdFj(Opcode32::FTINTRM_L_D, fd, fj));
3233
}
3234

3235
void LoongArch64Emitter::FTINTRP_W_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3236
    Write32(EncodeFdFj(Opcode32::FTINTRP_W_S, fd, fj));
3237
}
3238

3239
void LoongArch64Emitter::FTINTRP_W_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3240
    Write32(EncodeFdFj(Opcode32::FTINTRP_W_D, fd, fj));
3241
}
3242

3243
void LoongArch64Emitter::FTINTRP_L_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3244
    Write32(EncodeFdFj(Opcode32::FTINTRP_L_S, fd, fj));
3245
}
3246

3247
void LoongArch64Emitter::FTINTRP_L_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3248
    Write32(EncodeFdFj(Opcode32::FTINTRP_L_D, fd, fj));
3249
}
3250

3251
void LoongArch64Emitter::FTINTRZ_W_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3252
    Write32(EncodeFdFj(Opcode32::FTINTRZ_W_S, fd, fj));
3253
}
3254

3255
void LoongArch64Emitter::FTINTRZ_W_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3256
    Write32(EncodeFdFj(Opcode32::FTINTRZ_W_D, fd, fj));
3257
}
3258

3259
void LoongArch64Emitter::FTINTRZ_L_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3260
    Write32(EncodeFdFj(Opcode32::FTINTRZ_L_S, fd, fj));
3261
}
3262

3263
void LoongArch64Emitter::FTINTRZ_L_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3264
    Write32(EncodeFdFj(Opcode32::FTINTRZ_L_D, fd, fj));
3265
}
3266

3267
void LoongArch64Emitter::FTINTRNE_W_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3268
    Write32(EncodeFdFj(Opcode32::FTINTRNE_W_S, fd, fj));
3269
}
3270

3271
void LoongArch64Emitter::FTINTRNE_W_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3272
    Write32(EncodeFdFj(Opcode32::FTINTRNE_W_D, fd, fj));
3273
}
3274

3275
void LoongArch64Emitter::FTINTRNE_L_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3276
    Write32(EncodeFdFj(Opcode32::FTINTRNE_L_S, fd, fj));
3277
}
3278

3279
void LoongArch64Emitter::FTINTRNE_L_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3280
    Write32(EncodeFdFj(Opcode32::FTINTRNE_L_D, fd, fj));
3281
}
3282

3283
void LoongArch64Emitter::FRINT_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3284
    Write32(EncodeFdFj(Opcode32::FRINT_S, fd, fj));
3285
}
3286

3287
void LoongArch64Emitter::FRINT_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3288
    Write32(EncodeFdFj(Opcode32::FRINT_D, fd, fj));
3289
}
3290

3291
void LoongArch64Emitter::FMOV_S(LoongArch64Reg fd, LoongArch64Reg fj) {
3292
    Write32(EncodeFdFj(Opcode32::FMOV_S, fd, fj));
3293
}
3294

3295
void LoongArch64Emitter::FMOV_D(LoongArch64Reg fd, LoongArch64Reg fj) {
3296
    Write32(EncodeFdFj(Opcode32::FMOV_D, fd, fj));
3297
}
3298

3299
void LoongArch64Emitter::FSEL(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64CFR ca) {
3300
    Write32(EncodeFdFjFkCa(Opcode32::FSEL, fd, fj, fk, ca));
3301
}
3302

3303
void LoongArch64Emitter::MOVGR2FR_W(LoongArch64Reg fd, LoongArch64Reg rj) {
3304
    Write32(EncodeFdJ(Opcode32::MOVGR2FR_W, fd, rj));
3305
}
3306

3307
void LoongArch64Emitter::MOVGR2FR_D(LoongArch64Reg fd, LoongArch64Reg rj) {
3308
    Write32(EncodeFdJ(Opcode32::MOVGR2FR_D, fd, rj));
3309
}
3310

3311
void LoongArch64Emitter::MOVGR2FRH_W(LoongArch64Reg fd, LoongArch64Reg rj) {
3312
    Write32(EncodeFdJ(Opcode32::MOVGR2FRH_W, fd, rj));
3313
}
3314

3315
void LoongArch64Emitter::MOVFR2GR_S(LoongArch64Reg rd, LoongArch64Reg fj) {
3316
    Write32(EncodeDFj(Opcode32::MOVFR2GR_S, rd, fj));
3317
}
3318

3319
void LoongArch64Emitter::MOVFR2GR_D(LoongArch64Reg rd, LoongArch64Reg fj) {
3320
    Write32(EncodeDFj(Opcode32::MOVFR2GR_D, rd, fj));
3321
}
3322

3323
void LoongArch64Emitter::MOVFRH2GR_S(LoongArch64Reg rd, LoongArch64Reg fj) {
3324
    Write32(EncodeDFj(Opcode32::MOVFRH2GR_S, rd, fj));
3325
}
3326

3327
void LoongArch64Emitter::MOVGR2FCSR(LoongArch64FCSR fcsr, LoongArch64Reg rj) {
3328
    Write32(EncodeJUd5(Opcode32::MOVGR2FCSR, fcsr, rj));
3329
}
3330

3331
void LoongArch64Emitter::MOVFCSR2GR(LoongArch64Reg rd, LoongArch64FCSR fcsr) {
3332
    Write32(EncodeDUj5(Opcode32::MOVFCSR2GR, rd, fcsr));
3333
}
3334

3335
void LoongArch64Emitter::MOVFR2CF(LoongArch64CFR cd, LoongArch64Reg fj) {
3336
    Write32(EncodeCdFj(Opcode32::MOVFR2CF, cd, fj));
3337
}
3338

3339
void LoongArch64Emitter::MOVCF2FR(LoongArch64Reg fd, LoongArch64CFR cj) {
3340
    Write32(EncodeFdCj(Opcode32::MOVCF2FR, fd, cj));
3341
}
3342

3343
void LoongArch64Emitter::MOVGR2CF(LoongArch64CFR cd, LoongArch64Reg rj) {
3344
    Write32(EncodeCdJ(Opcode32::MOVGR2CF, cd, rj));
3345
}
3346

3347
void LoongArch64Emitter::MOVCF2GR(LoongArch64Reg rd, LoongArch64CFR cj) {
3348
    Write32(EncodeDCj(Opcode32::MOVCF2GR, rd, cj));
3349
}
3350

3351
void LoongArch64Emitter::BCEQZ(LoongArch64CFR cj, s32 offs21) {
3352
    Write32(EncodeCjSd5k16ps2(Opcode32::BCEQZ, cj, offs21));
3353
}
3354

3355
void LoongArch64Emitter::BCNEZ(LoongArch64CFR cj, s32 offs21) {
3356
    Write32(EncodeCjSd5k16ps2(Opcode32::BCNEZ, cj, offs21));
3357
}
3358

3359
void LoongArch64Emitter::FLD_S(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) {
3360
    Write32(EncodeFdJSk12(Opcode32::FLD_S, fd, rj, si12));
3361
}
3362

3363
void LoongArch64Emitter::FLD_D(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) {
3364
    Write32(EncodeFdJSk12(Opcode32::FLD_D, fd, rj, si12));
3365
}
3366

3367
void LoongArch64Emitter::FST_S(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) {
3368
    Write32(EncodeFdJSk12(Opcode32::FST_S, fd, rj, si12));
3369
}
3370

3371
void LoongArch64Emitter::FST_D(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) {
3372
    Write32(EncodeFdJSk12(Opcode32::FST_D, fd, rj, si12));
3373
}
3374

3375
void LoongArch64Emitter::FLDX_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3376
    Write32(EncodeFdJK(Opcode32::FLDX_S, fd, rj, rk));
3377
}
3378

3379
void LoongArch64Emitter::FLDX_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3380
    Write32(EncodeFdJK(Opcode32::FLDX_D, fd, rj, rk));
3381
}
3382

3383
void LoongArch64Emitter::FSTX_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3384
    Write32(EncodeFdJK(Opcode32::FSTX_S, fd, rj, rk));
3385
}
3386

3387
void LoongArch64Emitter::FSTX_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3388
    Write32(EncodeFdJK(Opcode32::FSTX_D, fd, rj, rk));
3389
}
3390

3391
void LoongArch64Emitter::FLDGT_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3392
    Write32(EncodeFdJK(Opcode32::FLDGT_S, fd, rj, rk));
3393
}
3394

3395
void LoongArch64Emitter::FLDGT_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3396
    Write32(EncodeFdJK(Opcode32::FLDGT_D, fd, rj, rk));
3397
}
3398

3399
void LoongArch64Emitter::FLDLE_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3400
    Write32(EncodeFdJK(Opcode32::FLDLE_S, fd, rj, rk));
3401
}
3402

3403
void LoongArch64Emitter::FLDLE_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3404
    Write32(EncodeFdJK(Opcode32::FLDLE_D, fd, rj, rk));
3405
}
3406

3407
void LoongArch64Emitter::FSTGT_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3408
    Write32(EncodeFdJK(Opcode32::FSTGT_S, fd, rj, rk));
3409
}
3410

3411
void LoongArch64Emitter::FSTGT_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3412
    Write32(EncodeFdJK(Opcode32::FSTGT_D, fd, rj, rk));
3413
}
3414

3415
void LoongArch64Emitter::FSTLE_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3416
    Write32(EncodeFdJK(Opcode32::FSTLE_S, fd, rj, rk));
3417
}
3418

3419
void LoongArch64Emitter::FSTLE_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) {
3420
    Write32(EncodeFdJK(Opcode32::FSTLE_D, fd, rj, rk));
3421
}
3422

3423
void LoongArch64Emitter::QuickFLI(int bits, LoongArch64Reg fd, double v, LoongArch64Reg scratchReg) {
3424
	if (bits == 64) {
3425
		LI(scratchReg, v);
3426
		MOVGR2FR_D(fd, scratchReg);
3427
	} else if (bits <= 32) {
3428
		QuickFLI(32, fd, (float)v, scratchReg);
3429
	} else {
3430
		_assert_msg_(false, "Unsupported QuickFLI bits");
3431
	}
3432
}
3433

3434
void LoongArch64Emitter::QuickFLI(int bits, LoongArch64Reg fd, uint32_t pattern, LoongArch64Reg scratchReg) {
3435
	if (bits == 32) {
3436
		LI(scratchReg, (int32_t)pattern);
3437
		MOVGR2FR_W(fd, scratchReg);
3438
	} else {
3439
		_assert_msg_(false, "Unsupported QuickFLI bits");
3440
	}
3441
}
3442

3443
void LoongArch64Emitter::QuickFLI(int bits, LoongArch64Reg fd, float v, LoongArch64Reg scratchReg) {
3444
	if (bits == 64) {
3445
		QuickFLI(32, fd, (double)v, scratchReg);
3446
	} else if (bits == 32) {
3447
		LI(scratchReg, v);
3448
		MOVGR2FR_W(fd, scratchReg);
3449
	} else {
3450
		_assert_msg_(false, "Unsupported QuickFLI bits");
3451
	}
3452
}
3453

3454
void LoongArch64Emitter::VFMADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3455
    Write32(EncodeVdVjVkVa(Opcode32::VFMADD_S, vd, vj, vk, va));
3456
}
3457

3458
void LoongArch64Emitter::VFMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3459
	Write32(EncodeVdVjVkVa(Opcode32::VFMADD_D, vd, vj, vk, va));
3460
}
3461

3462
void LoongArch64Emitter::VFMSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3463
	Write32(EncodeVdVjVkVa(Opcode32::VFMSUB_S, vd, vj, vk, va));
3464
}
3465

3466
void LoongArch64Emitter::VFMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3467
	Write32(EncodeVdVjVkVa(Opcode32::VFMSUB_D, vd, vj, vk, va));
3468
}
3469

3470
void LoongArch64Emitter::VFNMADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3471
	Write32(EncodeVdVjVkVa(Opcode32::VFNMADD_S, vd, vj, vk, va));
3472
}
3473

3474
void LoongArch64Emitter::VFNMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3475
	Write32(EncodeVdVjVkVa(Opcode32::VFNMADD_D, vd, vj, vk, va));
3476
}
3477

3478
void LoongArch64Emitter::VFNMSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3479
	Write32(EncodeVdVjVkVa(Opcode32::VFNMSUB_S, vd, vj, vk, va));
3480
}
3481

3482
void LoongArch64Emitter::VFNMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3483
	Write32(EncodeVdVjVkVa(Opcode32::VFNMSUB_D, vd, vj, vk, va));
3484
}
3485

3486
void LoongArch64Emitter::VFCMP_CAF_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3487
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CAF_S, vd, vj, vk));
3488
}
3489

3490
void LoongArch64Emitter::VFCMP_SAF_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3491
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SAF_S, vd, vj, vk));
3492
}
3493

3494
void LoongArch64Emitter::VFCMP_CLT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3495
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CLT_S, vd, vj, vk));
3496
}
3497

3498
void LoongArch64Emitter::VFCMP_SLT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3499
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SLT_S, vd, vj, vk));
3500
}
3501

3502
void LoongArch64Emitter::VFCMP_CEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3503
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CEQ_S, vd, vj, vk));
3504
}
3505

3506
void LoongArch64Emitter::VFCMP_SEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3507
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SEQ_S, vd, vj, vk));
3508
}
3509

3510
void LoongArch64Emitter::VFCMP_CLE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3511
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CLE_S, vd, vj, vk));
3512
}
3513

3514
void LoongArch64Emitter::VFCMP_SLE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3515
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SLE_S, vd, vj, vk));
3516
}
3517

3518
void LoongArch64Emitter::VFCMP_CUN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3519
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CUN_S, vd, vj, vk));
3520
}
3521

3522
void LoongArch64Emitter::VFCMP_SUN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3523
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SUN_S, vd, vj, vk));
3524
}
3525

3526
void LoongArch64Emitter::VFCMP_CULT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3527
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CULT_S, vd, vj, vk));
3528
}
3529

3530
void LoongArch64Emitter::VFCMP_SULT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3531
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SULT_S, vd, vj, vk));
3532
}
3533

3534
void LoongArch64Emitter::VFCMP_CUEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3535
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CUEQ_S, vd, vj, vk));
3536
}
3537

3538
void LoongArch64Emitter::VFCMP_SUEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3539
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SUEQ_S, vd, vj, vk));
3540
}
3541

3542
void LoongArch64Emitter::VFCMP_CULE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3543
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CULE_S, vd, vj, vk));
3544
}
3545

3546
void LoongArch64Emitter::VFCMP_SULE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3547
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SULE_S, vd, vj, vk));
3548
}
3549

3550
void LoongArch64Emitter::VFCMP_CNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3551
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CNE_S, vd, vj, vk));
3552
}
3553

3554
void LoongArch64Emitter::VFCMP_SNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3555
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SNE_S, vd, vj, vk));
3556
}
3557

3558
void LoongArch64Emitter::VFCMP_COR_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3559
	Write32(EncodeVdVjVk(Opcode32::VFCMP_COR_S, vd, vj, vk));
3560
}
3561

3562
void LoongArch64Emitter::VFCMP_SOR_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3563
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SOR_S, vd, vj, vk));
3564
}
3565

3566
void LoongArch64Emitter::VFCMP_CUNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3567
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CUNE_S, vd, vj, vk));
3568
}
3569

3570
void LoongArch64Emitter::VFCMP_SUNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3571
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SUNE_S, vd, vj, vk));
3572
}
3573

3574
void LoongArch64Emitter::VFCMP_CAF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3575
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CAF_D, vd, vj, vk));
3576
}
3577

3578
void LoongArch64Emitter::VFCMP_SAF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3579
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SAF_D, vd, vj, vk));
3580
}
3581

3582
void LoongArch64Emitter::VFCMP_CLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3583
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CLT_D, vd, vj, vk));
3584
}
3585

3586
void LoongArch64Emitter::VFCMP_SLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3587
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SLT_D, vd, vj, vk));
3588
}
3589

3590
void LoongArch64Emitter::VFCMP_CEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3591
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CEQ_D, vd, vj, vk));
3592
}
3593

3594
void LoongArch64Emitter::VFCMP_SEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3595
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SEQ_D, vd, vj, vk));
3596
}
3597

3598
void LoongArch64Emitter::VFCMP_CLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3599
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CLE_D, vd, vj, vk));
3600
}
3601

3602
void LoongArch64Emitter::VFCMP_SLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3603
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SLE_D, vd, vj, vk));
3604
}
3605

3606
void LoongArch64Emitter::VFCMP_CUN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3607
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CUN_D, vd, vj, vk));
3608
}
3609

3610
void LoongArch64Emitter::VFCMP_SUN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3611
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SUN_D, vd, vj, vk));
3612
}
3613

3614
void LoongArch64Emitter::VFCMP_CULT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3615
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CULT_D, vd, vj, vk));
3616
}
3617

3618
void LoongArch64Emitter::VFCMP_SULT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3619
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SULT_D, vd, vj, vk));
3620
}
3621

3622
void LoongArch64Emitter::VFCMP_CUEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3623
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CUEQ_D, vd, vj, vk));
3624
}
3625

3626
void LoongArch64Emitter::VFCMP_SUEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3627
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SUEQ_D, vd, vj, vk));
3628
}
3629

3630
void LoongArch64Emitter::VFCMP_CULE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3631
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CULE_D, vd, vj, vk));
3632
}
3633

3634
void LoongArch64Emitter::VFCMP_SULE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3635
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SULE_D, vd, vj, vk));
3636
}
3637

3638
void LoongArch64Emitter::VFCMP_CNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3639
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CNE_D, vd, vj, vk));
3640
}
3641

3642
void LoongArch64Emitter::VFCMP_SNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3643
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SNE_D, vd, vj, vk));
3644
}
3645

3646
void LoongArch64Emitter::VFCMP_COR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3647
	Write32(EncodeVdVjVk(Opcode32::VFCMP_COR_D, vd, vj, vk));
3648
}
3649

3650
void LoongArch64Emitter::VFCMP_SOR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3651
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SOR_D, vd, vj, vk));
3652
}
3653

3654
void LoongArch64Emitter::VFCMP_CUNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3655
	Write32(EncodeVdVjVk(Opcode32::VFCMP_CUNE_D, vd, vj, vk));
3656
}
3657

3658
void LoongArch64Emitter::VFCMP_SUNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3659
	Write32(EncodeVdVjVk(Opcode32::VFCMP_SUNE_D, vd, vj, vk));
3660
}
3661

3662
void LoongArch64Emitter::VBITSEL_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3663
	Write32(EncodeVdVjVkVa(Opcode32::VBITSEL_V, vd, vj, vk, va));
3664
}
3665

3666
void LoongArch64Emitter::VSHUF_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) {
3667
	Write32(EncodeVdVjVkVa(Opcode32::VSHUF_B, vd, vj, vk, va));
3668
}
3669

3670
void LoongArch64Emitter::VLD(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12) {
3671
	Write32(EncodeVdJSk12(Opcode32::VLD, vd, rj, si12));
3672
}
3673

3674
void LoongArch64Emitter::VST(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12) {
3675
	Write32(EncodeVdJSk12(Opcode32::VST, vd, rj, si12));
3676
}
3677

3678
void LoongArch64Emitter::VLDREPL_D(LoongArch64Reg vd, LoongArch64Reg rj, s16 si9) {
3679
	Write32(EncodeVdJSk9(Opcode32::VLDREPL_D, vd, rj, si9));
3680
}
3681

3682
void LoongArch64Emitter::VLDREPL_W(LoongArch64Reg vd, LoongArch64Reg rj, s16 si10) {
3683
	Write32(EncodeVdJSk10(Opcode32::VLDREPL_W, vd, rj, si10));
3684
}
3685

3686
void LoongArch64Emitter::VLDREPL_H(LoongArch64Reg vd, LoongArch64Reg rj, s16 si11) {
3687
	Write32(EncodeVdJSk11(Opcode32::VLDREPL_H, vd, rj, si11));
3688
}
3689

3690
void LoongArch64Emitter::VLDREPL_B(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12) {
3691
	Write32(EncodeVdJSk12(Opcode32::VLDREPL_B, vd, rj, si12));
3692
}
3693

3694
void LoongArch64Emitter::VSTELM_D(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx1) {
3695
	Write32(EncodeVdJSk8Un1(Opcode32::VSTELM_D, vd, rj, si8, idx1));
3696
}
3697

3698
void LoongArch64Emitter::VSTELM_W(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx2) {
3699
	Write32(EncodeVdJSk8Un2(Opcode32::VSTELM_W, vd, rj, si8, idx2));
3700
}
3701

3702
void LoongArch64Emitter::VSTELM_H(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx3) {
3703
	Write32(EncodeVdJSk8Un3(Opcode32::VSTELM_H, vd, rj, si8, idx3));
3704
}
3705

3706
void LoongArch64Emitter::VSTELM_B(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx4) {
3707
	Write32(EncodeVdJSk8Un4(Opcode32::VSTELM_B, vd, rj, si8, idx4));
3708
}
3709

3710
void LoongArch64Emitter::VLDX(LoongArch64Reg vd, LoongArch64Reg rj, LoongArch64Reg rk) {
3711
    Write32(EncodeVdJK(Opcode32::VLDX, vd, rj, rk));
3712
}
3713

3714
void LoongArch64Emitter::VSTX(LoongArch64Reg vd, LoongArch64Reg rj, LoongArch64Reg rk) {
3715
    Write32(EncodeVdJK(Opcode32::VSTX, vd, rj, rk));
3716
}
3717

3718
void LoongArch64Emitter::VSEQ_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3719
	Write32(EncodeVdVjVk(Opcode32::VSEQ_B, vd, vj, vk));
3720
}
3721

3722
void LoongArch64Emitter::VSEQ_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3723
	Write32(EncodeVdVjVk(Opcode32::VSEQ_H, vd, vj, vk));
3724
}
3725

3726
void LoongArch64Emitter::VSEQ_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3727
	Write32(EncodeVdVjVk(Opcode32::VSEQ_W, vd, vj, vk));
3728
}
3729

3730
void LoongArch64Emitter::VSEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3731
	Write32(EncodeVdVjVk(Opcode32::VSEQ_D, vd, vj, vk));
3732
}
3733

3734
void LoongArch64Emitter::VSLE_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3735
	Write32(EncodeVdVjVk(Opcode32::VSLE_B, vd, vj, vk));
3736
}
3737

3738
void LoongArch64Emitter::VSLE_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3739
	Write32(EncodeVdVjVk(Opcode32::VSLE_H, vd, vj, vk));
3740
}
3741

3742
void LoongArch64Emitter::VSLE_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3743
	Write32(EncodeVdVjVk(Opcode32::VSLE_W, vd, vj, vk));
3744
}
3745

3746
void LoongArch64Emitter::VSLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3747
	Write32(EncodeVdVjVk(Opcode32::VSLE_D, vd, vj, vk));
3748
}
3749

3750
void LoongArch64Emitter::VSLE_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3751
	Write32(EncodeVdVjVk(Opcode32::VSLE_BU, vd, vj, vk));
3752
}
3753

3754
void LoongArch64Emitter::VSLE_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3755
	Write32(EncodeVdVjVk(Opcode32::VSLE_HU, vd, vj, vk));
3756
}
3757

3758
void LoongArch64Emitter::VSLE_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3759
	Write32(EncodeVdVjVk(Opcode32::VSLE_WU, vd, vj, vk));
3760
}
3761

3762
void LoongArch64Emitter::VSLE_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3763
	Write32(EncodeVdVjVk(Opcode32::VSLE_DU, vd, vj, vk));
3764
}
3765

3766
void LoongArch64Emitter::VSLT_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3767
	Write32(EncodeVdVjVk(Opcode32::VSLT_B, vd, vj, vk));
3768
}
3769

3770
void LoongArch64Emitter::VSLT_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3771
	Write32(EncodeVdVjVk(Opcode32::VSLT_H, vd, vj, vk));
3772
}
3773

3774
void LoongArch64Emitter::VSLT_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3775
	Write32(EncodeVdVjVk(Opcode32::VSLT_W, vd, vj, vk));
3776
}
3777

3778
void LoongArch64Emitter::VSLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3779
	Write32(EncodeVdVjVk(Opcode32::VSLT_D, vd, vj, vk));
3780
}
3781

3782
void LoongArch64Emitter::VSLT_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3783
	Write32(EncodeVdVjVk(Opcode32::VSLT_BU, vd, vj, vk));
3784
}
3785

3786
void LoongArch64Emitter::VSLT_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3787
	Write32(EncodeVdVjVk(Opcode32::VSLT_HU, vd, vj, vk));
3788
}
3789

3790
void LoongArch64Emitter::VSLT_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3791
	Write32(EncodeVdVjVk(Opcode32::VSLT_WU, vd, vj, vk));
3792
}
3793

3794
void LoongArch64Emitter::VSLT_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3795
	Write32(EncodeVdVjVk(Opcode32::VSLT_DU, vd, vj, vk));
3796
}
3797

3798
void LoongArch64Emitter::VADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3799
	Write32(EncodeVdVjVk(Opcode32::VADD_B, vd, vj, vk));
3800
}
3801

3802
void LoongArch64Emitter::VADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3803
	Write32(EncodeVdVjVk(Opcode32::VADD_H, vd, vj, vk));
3804
}
3805

3806
void LoongArch64Emitter::VADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3807
	Write32(EncodeVdVjVk(Opcode32::VADD_W, vd, vj, vk));
3808
}
3809

3810
void LoongArch64Emitter::VADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3811
	Write32(EncodeVdVjVk(Opcode32::VADD_D, vd, vj, vk));
3812
}
3813

3814
void LoongArch64Emitter::VSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3815
	Write32(EncodeVdVjVk(Opcode32::VSUB_B, vd, vj, vk));
3816
}
3817

3818
void LoongArch64Emitter::VSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3819
	Write32(EncodeVdVjVk(Opcode32::VSUB_H, vd, vj, vk));
3820
}
3821

3822
void LoongArch64Emitter::VSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3823
	Write32(EncodeVdVjVk(Opcode32::VSUB_W, vd, vj, vk));
3824
}
3825

3826
void LoongArch64Emitter::VSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3827
	Write32(EncodeVdVjVk(Opcode32::VSUB_D, vd, vj, vk));
3828
}
3829

3830
void LoongArch64Emitter::VADDWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3831
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_H_B, vd, vj, vk));
3832
}
3833

3834
void LoongArch64Emitter::VADDWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3835
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_W_H, vd, vj, vk));
3836
}
3837

3838
void LoongArch64Emitter::VADDWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3839
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_D_W, vd, vj, vk));
3840
}
3841

3842
void LoongArch64Emitter::VADDWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3843
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_Q_D, vd, vj, vk));
3844
}
3845

3846
void LoongArch64Emitter::VSUBWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3847
	Write32(EncodeVdVjVk(Opcode32::VSUBWEV_H_B, vd, vj, vk));
3848
}
3849

3850
void LoongArch64Emitter::VSUBWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3851
	Write32(EncodeVdVjVk(Opcode32::VSUBWEV_W_H, vd, vj, vk));
3852
}
3853

3854
void LoongArch64Emitter::VSUBWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3855
	Write32(EncodeVdVjVk(Opcode32::VSUBWEV_D_W, vd, vj, vk));
3856
}
3857

3858
void LoongArch64Emitter::VSUBWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3859
	Write32(EncodeVdVjVk(Opcode32::VSUBWEV_Q_D, vd, vj, vk));
3860
}
3861

3862
void LoongArch64Emitter::VADDWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3863
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_H_B, vd, vj, vk));
3864
}
3865

3866
void LoongArch64Emitter::VADDWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3867
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_W_H, vd, vj, vk));
3868
}
3869

3870
void LoongArch64Emitter::VADDWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3871
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_D_W, vd, vj, vk));
3872
}
3873

3874
void LoongArch64Emitter::VADDWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3875
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_Q_D, vd, vj, vk));
3876
}
3877

3878
void LoongArch64Emitter::VSUBWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3879
	Write32(EncodeVdVjVk(Opcode32::VSUBWOD_H_B, vd, vj, vk));
3880
}
3881

3882
void LoongArch64Emitter::VSUBWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3883
	Write32(EncodeVdVjVk(Opcode32::VSUBWOD_W_H, vd, vj, vk));
3884
}
3885

3886
void LoongArch64Emitter::VSUBWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3887
	Write32(EncodeVdVjVk(Opcode32::VSUBWOD_D_W, vd, vj, vk));
3888
}
3889

3890
void LoongArch64Emitter::VSUBWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3891
	Write32(EncodeVdVjVk(Opcode32::VSUBWOD_Q_D, vd, vj, vk));
3892
}
3893

3894
void LoongArch64Emitter::VADDWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3895
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_H_BU, vd, vj, vk));
3896
}
3897

3898
void LoongArch64Emitter::VADDWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3899
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_W_HU, vd, vj, vk));
3900
}
3901

3902
void LoongArch64Emitter::VADDWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3903
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_D_WU, vd, vj, vk));
3904
}
3905

3906
void LoongArch64Emitter::VADDWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3907
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_Q_DU, vd, vj, vk));
3908
}
3909

3910
void LoongArch64Emitter::VSUBWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3911
	Write32(EncodeVdVjVk(Opcode32::VSUBWEV_H_BU, vd, vj, vk));
3912
}
3913

3914
void LoongArch64Emitter::VSUBWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3915
	Write32(EncodeVdVjVk(Opcode32::VSUBWEV_W_HU, vd, vj, vk));
3916
}
3917

3918
void LoongArch64Emitter::VSUBWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3919
	Write32(EncodeVdVjVk(Opcode32::VSUBWEV_D_WU, vd, vj, vk));
3920
}
3921

3922
void LoongArch64Emitter::VSUBWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3923
	Write32(EncodeVdVjVk(Opcode32::VSUBWEV_Q_DU, vd, vj, vk));
3924
}
3925

3926
void LoongArch64Emitter::VADDWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3927
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_H_BU, vd, vj, vk));
3928
}
3929

3930
void LoongArch64Emitter::VADDWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3931
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_W_HU, vd, vj, vk));
3932
}
3933

3934
void LoongArch64Emitter::VADDWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3935
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_D_WU, vd, vj, vk));
3936
}
3937

3938
void LoongArch64Emitter::VADDWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3939
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_Q_DU, vd, vj, vk));
3940
}
3941

3942
void LoongArch64Emitter::VSUBWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3943
	Write32(EncodeVdVjVk(Opcode32::VSUBWOD_H_BU, vd, vj, vk));
3944
}
3945

3946
void LoongArch64Emitter::VSUBWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3947
	Write32(EncodeVdVjVk(Opcode32::VSUBWOD_W_HU, vd, vj, vk));
3948
}
3949

3950
void LoongArch64Emitter::VSUBWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3951
	Write32(EncodeVdVjVk(Opcode32::VSUBWOD_D_WU, vd, vj, vk));
3952
}
3953

3954
void LoongArch64Emitter::VSUBWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3955
	Write32(EncodeVdVjVk(Opcode32::VSUBWOD_Q_DU, vd, vj, vk));
3956
}
3957

3958
void LoongArch64Emitter::VADDWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3959
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_H_BU_B, vd, vj, vk));
3960
}
3961

3962
void LoongArch64Emitter::VADDWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3963
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_W_HU_H, vd, vj, vk));
3964
}
3965

3966
void LoongArch64Emitter::VADDWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3967
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_D_WU_W, vd, vj, vk));
3968
}
3969

3970
void LoongArch64Emitter::VADDWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3971
	Write32(EncodeVdVjVk(Opcode32::VADDWEV_Q_DU_D, vd, vj, vk));
3972
}
3973

3974
void LoongArch64Emitter::VADDWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3975
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_H_BU_B, vd, vj, vk));
3976
}
3977

3978
void LoongArch64Emitter::VADDWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3979
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_W_HU_H, vd, vj, vk));
3980
}
3981

3982
void LoongArch64Emitter::VADDWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3983
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_D_WU_W, vd, vj, vk));
3984
}
3985

3986
void LoongArch64Emitter::VADDWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3987
	Write32(EncodeVdVjVk(Opcode32::VADDWOD_Q_DU_D, vd, vj, vk));
3988
}
3989

3990
void LoongArch64Emitter::VSADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3991
	Write32(EncodeVdVjVk(Opcode32::VSADD_B, vd, vj, vk));
3992
}
3993

3994
void LoongArch64Emitter::VSADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3995
	Write32(EncodeVdVjVk(Opcode32::VSADD_H, vd, vj, vk));
3996
}
3997

3998
void LoongArch64Emitter::VSADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
3999
	Write32(EncodeVdVjVk(Opcode32::VSADD_W, vd, vj, vk));
4000
}
4001

4002
void LoongArch64Emitter::VSADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4003
	Write32(EncodeVdVjVk(Opcode32::VSADD_D, vd, vj, vk));
4004
}
4005

4006
void LoongArch64Emitter::VSSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4007
	Write32(EncodeVdVjVk(Opcode32::VSSUB_B, vd, vj, vk));
4008
}
4009

4010
void LoongArch64Emitter::VSSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4011
	Write32(EncodeVdVjVk(Opcode32::VSSUB_H, vd, vj, vk));
4012
}
4013

4014
void LoongArch64Emitter::VSSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4015
	Write32(EncodeVdVjVk(Opcode32::VSSUB_W, vd, vj, vk));
4016
}
4017

4018
void LoongArch64Emitter::VSSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4019
	Write32(EncodeVdVjVk(Opcode32::VSSUB_D, vd, vj, vk));
4020
}
4021

4022
void LoongArch64Emitter::VSADD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4023
	Write32(EncodeVdVjVk(Opcode32::VSADD_BU, vd, vj, vk));
4024
}
4025

4026
void LoongArch64Emitter::VSADD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4027
	Write32(EncodeVdVjVk(Opcode32::VSADD_HU, vd, vj, vk));
4028
}
4029

4030
void LoongArch64Emitter::VSADD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4031
	Write32(EncodeVdVjVk(Opcode32::VSADD_WU, vd, vj, vk));
4032
}
4033

4034
void LoongArch64Emitter::VSADD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4035
	Write32(EncodeVdVjVk(Opcode32::VSADD_DU, vd, vj, vk));
4036
}
4037

4038
void LoongArch64Emitter::VSSUB_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4039
	Write32(EncodeVdVjVk(Opcode32::VSSUB_BU, vd, vj, vk));
4040
}
4041

4042
void LoongArch64Emitter::VSSUB_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4043
	Write32(EncodeVdVjVk(Opcode32::VSSUB_HU, vd, vj, vk));
4044
}
4045

4046
void LoongArch64Emitter::VSSUB_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4047
	Write32(EncodeVdVjVk(Opcode32::VSSUB_WU, vd, vj, vk));
4048
}
4049

4050
void LoongArch64Emitter::VSSUB_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4051
	Write32(EncodeVdVjVk(Opcode32::VSSUB_DU, vd, vj, vk));
4052
}
4053

4054
void LoongArch64Emitter::VHADDW_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4055
	Write32(EncodeVdVjVk(Opcode32::VHADDW_H_B, vd, vj, vk));
4056
}
4057

4058
void LoongArch64Emitter::VHADDW_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4059
	Write32(EncodeVdVjVk(Opcode32::VHADDW_W_H, vd, vj, vk));
4060
}
4061

4062
void LoongArch64Emitter::VHADDW_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4063
	Write32(EncodeVdVjVk(Opcode32::VHADDW_D_W, vd, vj, vk));
4064
}
4065

4066
void LoongArch64Emitter::VHADDW_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4067
	Write32(EncodeVdVjVk(Opcode32::VHADDW_Q_D, vd, vj, vk));
4068
}
4069

4070
void LoongArch64Emitter::VHSUBW_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4071
	Write32(EncodeVdVjVk(Opcode32::VHSUBW_H_B, vd, vj, vk));
4072
}
4073

4074
void LoongArch64Emitter::VHSUBW_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4075
	Write32(EncodeVdVjVk(Opcode32::VHSUBW_W_H, vd, vj, vk));
4076
}
4077

4078
void LoongArch64Emitter::VHSUBW_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4079
	Write32(EncodeVdVjVk(Opcode32::VHSUBW_D_W, vd, vj, vk));
4080
}
4081

4082
void LoongArch64Emitter::VHSUBW_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4083
	Write32(EncodeVdVjVk(Opcode32::VHSUBW_Q_D, vd, vj, vk));
4084
}
4085

4086
void LoongArch64Emitter::VHADDW_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4087
	Write32(EncodeVdVjVk(Opcode32::VHADDW_HU_BU, vd, vj, vk));
4088
}
4089

4090
void LoongArch64Emitter::VHADDW_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4091
	Write32(EncodeVdVjVk(Opcode32::VHADDW_WU_HU, vd, vj, vk));
4092
}
4093

4094
void LoongArch64Emitter::VHADDW_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4095
	Write32(EncodeVdVjVk(Opcode32::VHADDW_DU_WU, vd, vj, vk));
4096
}
4097

4098
void LoongArch64Emitter::VHADDW_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4099
	Write32(EncodeVdVjVk(Opcode32::VHADDW_QU_DU, vd, vj, vk));
4100
}
4101

4102
void LoongArch64Emitter::VHSUBW_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4103
	Write32(EncodeVdVjVk(Opcode32::VHSUBW_HU_BU, vd, vj, vk));
4104
}
4105

4106
void LoongArch64Emitter::VHSUBW_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4107
	Write32(EncodeVdVjVk(Opcode32::VHSUBW_WU_HU, vd, vj, vk));
4108
}
4109

4110
void LoongArch64Emitter::VHSUBW_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4111
	Write32(EncodeVdVjVk(Opcode32::VHSUBW_DU_WU, vd, vj, vk));
4112
}
4113

4114
void LoongArch64Emitter::VHSUBW_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4115
	Write32(EncodeVdVjVk(Opcode32::VHSUBW_QU_DU, vd, vj, vk));
4116
}
4117

4118
void LoongArch64Emitter::VADDA_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4119
	Write32(EncodeVdVjVk(Opcode32::VADDA_B, vd, vj, vk));
4120
}
4121

4122
void LoongArch64Emitter::VADDA_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4123
	Write32(EncodeVdVjVk(Opcode32::VADDA_H, vd, vj, vk));
4124
}
4125

4126
void LoongArch64Emitter::VADDA_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4127
	Write32(EncodeVdVjVk(Opcode32::VADDA_W, vd, vj, vk));
4128
}
4129

4130
void LoongArch64Emitter::VADDA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4131
	Write32(EncodeVdVjVk(Opcode32::VADDA_D, vd, vj, vk));
4132
}
4133

4134
void LoongArch64Emitter::VABSD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4135
	Write32(EncodeVdVjVk(Opcode32::VABSD_B, vd, vj, vk));
4136
}
4137

4138
void LoongArch64Emitter::VABSD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4139
	Write32(EncodeVdVjVk(Opcode32::VABSD_H, vd, vj, vk));
4140
}
4141

4142
void LoongArch64Emitter::VABSD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4143
	Write32(EncodeVdVjVk(Opcode32::VABSD_W, vd, vj, vk));
4144
}
4145

4146
void LoongArch64Emitter::VABSD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4147
	Write32(EncodeVdVjVk(Opcode32::VABSD_D, vd, vj, vk));
4148
}
4149

4150
void LoongArch64Emitter::VABSD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4151
	Write32(EncodeVdVjVk(Opcode32::VABSD_BU, vd, vj, vk));
4152
}
4153

4154
void LoongArch64Emitter::VABSD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4155
	Write32(EncodeVdVjVk(Opcode32::VABSD_HU, vd, vj, vk));
4156
}
4157

4158
void LoongArch64Emitter::VABSD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4159
	Write32(EncodeVdVjVk(Opcode32::VABSD_WU, vd, vj, vk));
4160
}
4161

4162
void LoongArch64Emitter::VABSD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4163
	Write32(EncodeVdVjVk(Opcode32::VABSD_DU, vd, vj, vk));
4164
}
4165

4166
void LoongArch64Emitter::VAVG_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4167
	Write32(EncodeVdVjVk(Opcode32::VAVG_B, vd, vj, vk));
4168
}
4169

4170
void LoongArch64Emitter::VAVG_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4171
	Write32(EncodeVdVjVk(Opcode32::VAVG_H, vd, vj, vk));
4172
}
4173

4174
void LoongArch64Emitter::VAVG_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4175
	Write32(EncodeVdVjVk(Opcode32::VAVG_W, vd, vj, vk));
4176
}
4177

4178
void LoongArch64Emitter::VAVG_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4179
	Write32(EncodeVdVjVk(Opcode32::VAVG_D, vd, vj, vk));
4180
}
4181

4182
void LoongArch64Emitter::VAVG_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4183
	Write32(EncodeVdVjVk(Opcode32::VAVG_BU, vd, vj, vk));
4184
}
4185

4186
void LoongArch64Emitter::VAVG_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4187
	Write32(EncodeVdVjVk(Opcode32::VAVG_HU, vd, vj, vk));
4188
}
4189

4190
void LoongArch64Emitter::VAVG_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4191
	Write32(EncodeVdVjVk(Opcode32::VAVG_WU, vd, vj, vk));
4192
}
4193

4194
void LoongArch64Emitter::VAVG_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4195
	Write32(EncodeVdVjVk(Opcode32::VAVG_DU, vd, vj, vk));
4196
}
4197

4198
void LoongArch64Emitter::VAVGR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4199
	Write32(EncodeVdVjVk(Opcode32::VAVGR_B, vd, vj, vk));
4200
}
4201

4202
void LoongArch64Emitter::VAVGR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4203
	Write32(EncodeVdVjVk(Opcode32::VAVGR_H, vd, vj, vk));
4204
}
4205

4206
void LoongArch64Emitter::VAVGR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4207
	Write32(EncodeVdVjVk(Opcode32::VAVGR_W, vd, vj, vk));
4208
}
4209

4210
void LoongArch64Emitter::VAVGR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4211
	Write32(EncodeVdVjVk(Opcode32::VAVGR_D, vd, vj, vk));
4212
}
4213

4214
void LoongArch64Emitter::VAVGR_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4215
	Write32(EncodeVdVjVk(Opcode32::VAVGR_BU, vd, vj, vk));
4216
}
4217

4218
void LoongArch64Emitter::VAVGR_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4219
	Write32(EncodeVdVjVk(Opcode32::VAVGR_HU, vd, vj, vk));
4220
}
4221

4222
void LoongArch64Emitter::VAVGR_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4223
	Write32(EncodeVdVjVk(Opcode32::VAVGR_WU, vd, vj, vk));
4224
}
4225

4226
void LoongArch64Emitter::VAVGR_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4227
	Write32(EncodeVdVjVk(Opcode32::VAVGR_DU, vd, vj, vk));
4228
}
4229

4230
void LoongArch64Emitter::VMAX_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4231
	Write32(EncodeVdVjVk(Opcode32::VMAX_B, vd, vj, vk));
4232
}
4233

4234
void LoongArch64Emitter::VMAX_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4235
	Write32(EncodeVdVjVk(Opcode32::VMAX_H, vd, vj, vk));
4236
}
4237

4238
void LoongArch64Emitter::VMAX_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4239
	Write32(EncodeVdVjVk(Opcode32::VMAX_W, vd, vj, vk));
4240
}
4241

4242
void LoongArch64Emitter::VMAX_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4243
	Write32(EncodeVdVjVk(Opcode32::VMAX_D, vd, vj, vk));
4244
}
4245

4246
void LoongArch64Emitter::VMIN_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4247
	Write32(EncodeVdVjVk(Opcode32::VMIN_B, vd, vj, vk));
4248
}
4249

4250
void LoongArch64Emitter::VMIN_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4251
	Write32(EncodeVdVjVk(Opcode32::VMIN_H, vd, vj, vk));
4252
}
4253

4254
void LoongArch64Emitter::VMIN_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4255
	Write32(EncodeVdVjVk(Opcode32::VMIN_W, vd, vj, vk));
4256
}
4257

4258
void LoongArch64Emitter::VMIN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4259
	Write32(EncodeVdVjVk(Opcode32::VMIN_D, vd, vj, vk));
4260
}
4261

4262
void LoongArch64Emitter::VMAX_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4263
	Write32(EncodeVdVjVk(Opcode32::VMAX_BU, vd, vj, vk));
4264
}
4265

4266
void LoongArch64Emitter::VMAX_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4267
	Write32(EncodeVdVjVk(Opcode32::VMAX_HU, vd, vj, vk));
4268
}
4269

4270
void LoongArch64Emitter::VMAX_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4271
	Write32(EncodeVdVjVk(Opcode32::VMAX_WU, vd, vj, vk));
4272
}
4273

4274
void LoongArch64Emitter::VMAX_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4275
	Write32(EncodeVdVjVk(Opcode32::VMAX_DU, vd, vj, vk));
4276
}
4277

4278
void LoongArch64Emitter::VMIN_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4279
	Write32(EncodeVdVjVk(Opcode32::VMIN_BU, vd, vj, vk));
4280
}
4281

4282
void LoongArch64Emitter::VMIN_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4283
	Write32(EncodeVdVjVk(Opcode32::VMIN_HU, vd, vj, vk));
4284
}
4285

4286
void LoongArch64Emitter::VMIN_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4287
	Write32(EncodeVdVjVk(Opcode32::VMIN_WU, vd, vj, vk));
4288
}
4289

4290
void LoongArch64Emitter::VMIN_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4291
	Write32(EncodeVdVjVk(Opcode32::VMIN_DU, vd, vj, vk));
4292
}
4293

4294
void LoongArch64Emitter::VMUL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4295
	Write32(EncodeVdVjVk(Opcode32::VMUL_B, vd, vj, vk));
4296
}
4297

4298
void LoongArch64Emitter::VMUL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4299
	Write32(EncodeVdVjVk(Opcode32::VMUL_H, vd, vj, vk));
4300
}
4301

4302
void LoongArch64Emitter::VMUL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4303
	Write32(EncodeVdVjVk(Opcode32::VMUL_W, vd, vj, vk));
4304
}
4305

4306
void LoongArch64Emitter::VMUL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4307
	Write32(EncodeVdVjVk(Opcode32::VMUL_D, vd, vj, vk));
4308
}
4309

4310
void LoongArch64Emitter::VMUH_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4311
	Write32(EncodeVdVjVk(Opcode32::VMUH_B, vd, vj, vk));
4312
}
4313

4314
void LoongArch64Emitter::VMUH_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4315
	Write32(EncodeVdVjVk(Opcode32::VMUH_H, vd, vj, vk));
4316
}
4317

4318
void LoongArch64Emitter::VMUH_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4319
	Write32(EncodeVdVjVk(Opcode32::VMUH_W, vd, vj, vk));
4320
}
4321

4322
void LoongArch64Emitter::VMUH_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4323
	Write32(EncodeVdVjVk(Opcode32::VMUH_D, vd, vj, vk));
4324
}
4325

4326
void LoongArch64Emitter::VMUH_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4327
	Write32(EncodeVdVjVk(Opcode32::VMUH_BU, vd, vj, vk));
4328
}
4329

4330
void LoongArch64Emitter::VMUH_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4331
	Write32(EncodeVdVjVk(Opcode32::VMUH_HU, vd, vj, vk));
4332
}
4333

4334
void LoongArch64Emitter::VMUH_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4335
	Write32(EncodeVdVjVk(Opcode32::VMUH_WU, vd, vj, vk));
4336
}
4337

4338
void LoongArch64Emitter::VMUH_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4339
	Write32(EncodeVdVjVk(Opcode32::VMUH_DU, vd, vj, vk));
4340
}
4341

4342
void LoongArch64Emitter::VMULWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4343
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_H_B, vd, vj, vk));
4344
}
4345

4346
void LoongArch64Emitter::VMULWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4347
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_W_H, vd, vj, vk));
4348
}
4349

4350
void LoongArch64Emitter::VMULWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4351
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_D_W, vd, vj, vk));
4352
}
4353

4354
void LoongArch64Emitter::VMULWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4355
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_Q_D, vd, vj, vk));
4356
}
4357

4358
void LoongArch64Emitter::VMULWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4359
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_H_B, vd, vj, vk));
4360
}
4361

4362
void LoongArch64Emitter::VMULWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4363
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_W_H, vd, vj, vk));
4364
}
4365

4366
void LoongArch64Emitter::VMULWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4367
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_D_W, vd, vj, vk));
4368
}
4369

4370
void LoongArch64Emitter::VMULWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4371
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_Q_D, vd, vj, vk));
4372
}
4373

4374
void LoongArch64Emitter::VMULWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4375
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_H_BU, vd, vj, vk));
4376
}
4377

4378
void LoongArch64Emitter::VMULWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4379
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_W_HU, vd, vj, vk));
4380
}
4381

4382
void LoongArch64Emitter::VMULWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4383
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_D_WU, vd, vj, vk));
4384
}
4385

4386
void LoongArch64Emitter::VMULWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4387
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_Q_DU, vd, vj, vk));
4388
}
4389

4390
void LoongArch64Emitter::VMULWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4391
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_H_BU, vd, vj, vk));
4392
}
4393

4394
void LoongArch64Emitter::VMULWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4395
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_W_HU, vd, vj, vk));
4396
}
4397

4398
void LoongArch64Emitter::VMULWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4399
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_D_WU, vd, vj, vk));
4400
}
4401

4402
void LoongArch64Emitter::VMULWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4403
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_Q_DU, vd, vj, vk));
4404
}
4405

4406
void LoongArch64Emitter::VMULWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4407
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_H_BU_B, vd, vj, vk));
4408
}
4409

4410
void LoongArch64Emitter::VMULWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4411
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_W_HU_H, vd, vj, vk));
4412
}
4413

4414
void LoongArch64Emitter::VMULWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4415
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_D_WU_W, vd, vj, vk));
4416
}
4417

4418
void LoongArch64Emitter::VMULWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4419
	Write32(EncodeVdVjVk(Opcode32::VMULWEV_Q_DU_D, vd, vj, vk));
4420
}
4421

4422
void LoongArch64Emitter::VMULWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4423
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_H_BU_B, vd, vj, vk));
4424
}
4425

4426
void LoongArch64Emitter::VMULWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4427
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_W_HU_H, vd, vj, vk));
4428
}
4429

4430
void LoongArch64Emitter::VMULWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4431
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_D_WU_W, vd, vj, vk));
4432
}
4433

4434
void LoongArch64Emitter::VMULWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4435
	Write32(EncodeVdVjVk(Opcode32::VMULWOD_Q_DU_D, vd, vj, vk));
4436
}
4437

4438
void LoongArch64Emitter::VMADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4439
	Write32(EncodeVdVjVk(Opcode32::VMADD_B, vd, vj, vk));
4440
}
4441

4442
void LoongArch64Emitter::VMADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4443
	Write32(EncodeVdVjVk(Opcode32::VMADD_H, vd, vj, vk));
4444
}
4445

4446
void LoongArch64Emitter::VMADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4447
	Write32(EncodeVdVjVk(Opcode32::VMADD_W, vd, vj, vk));
4448
}
4449

4450
void LoongArch64Emitter::VMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4451
	Write32(EncodeVdVjVk(Opcode32::VMADD_D, vd, vj, vk));
4452
}
4453

4454
void LoongArch64Emitter::VMSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4455
	Write32(EncodeVdVjVk(Opcode32::VMSUB_B, vd, vj, vk));
4456
}
4457

4458
void LoongArch64Emitter::VMSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4459
	Write32(EncodeVdVjVk(Opcode32::VMSUB_H, vd, vj, vk));
4460
}
4461

4462
void LoongArch64Emitter::VMSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4463
	Write32(EncodeVdVjVk(Opcode32::VMSUB_W, vd, vj, vk));
4464
}
4465

4466
void LoongArch64Emitter::VMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4467
	Write32(EncodeVdVjVk(Opcode32::VMSUB_D, vd, vj, vk));
4468
}
4469

4470
void LoongArch64Emitter::VMADDWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4471
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_H_B, vd, vj, vk));
4472
}
4473

4474
void LoongArch64Emitter::VMADDWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4475
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_W_H, vd, vj, vk));
4476
}
4477

4478
void LoongArch64Emitter::VMADDWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4479
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_D_W, vd, vj, vk));
4480
}
4481

4482
void LoongArch64Emitter::VMADDWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4483
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_Q_D, vd, vj, vk));
4484
}
4485

4486
void LoongArch64Emitter::VMADDWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4487
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_H_B, vd, vj, vk));
4488
}
4489

4490
void LoongArch64Emitter::VMADDWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4491
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_W_H, vd, vj, vk));
4492
}
4493

4494
void LoongArch64Emitter::VMADDWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4495
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_D_W, vd, vj, vk));
4496
}
4497

4498
void LoongArch64Emitter::VMADDWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4499
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_Q_D, vd, vj, vk));
4500
}
4501

4502
void LoongArch64Emitter::VMADDWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4503
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_H_BU, vd, vj, vk));
4504
}
4505

4506
void LoongArch64Emitter::VMADDWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4507
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_W_HU, vd, vj, vk));
4508
}
4509

4510
void LoongArch64Emitter::VMADDWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4511
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_D_WU, vd, vj, vk));
4512
}
4513

4514
void LoongArch64Emitter::VMADDWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4515
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_Q_DU, vd, vj, vk));
4516
}
4517

4518
void LoongArch64Emitter::VMADDWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4519
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_H_BU, vd, vj, vk));
4520
}
4521

4522
void LoongArch64Emitter::VMADDWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4523
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_W_HU, vd, vj, vk));
4524
}
4525

4526
void LoongArch64Emitter::VMADDWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4527
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_D_WU, vd, vj, vk));
4528
}
4529

4530
void LoongArch64Emitter::VMADDWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4531
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_Q_DU, vd, vj, vk));
4532
}
4533

4534
void LoongArch64Emitter::VMADDWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4535
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_H_BU_B, vd, vj, vk));
4536
}
4537

4538
void LoongArch64Emitter::VMADDWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4539
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_W_HU_H, vd, vj, vk));
4540
}
4541

4542
void LoongArch64Emitter::VMADDWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4543
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_D_WU_W, vd, vj, vk));
4544
}
4545

4546
void LoongArch64Emitter::VMADDWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4547
	Write32(EncodeVdVjVk(Opcode32::VMADDWEV_Q_DU_D, vd, vj, vk));
4548
}
4549

4550
void LoongArch64Emitter::VMADDWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4551
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_H_BU_B, vd, vj, vk));
4552
}
4553

4554
void LoongArch64Emitter::VMADDWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4555
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_W_HU_H, vd, vj, vk));
4556
}
4557

4558
void LoongArch64Emitter::VMADDWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4559
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_D_WU_W, vd, vj, vk));
4560
}
4561

4562
void LoongArch64Emitter::VMADDWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4563
	Write32(EncodeVdVjVk(Opcode32::VMADDWOD_Q_DU_D, vd, vj, vk));
4564
}
4565

4566
void LoongArch64Emitter::VDIV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4567
	Write32(EncodeVdVjVk(Opcode32::VDIV_B, vd, vj, vk));
4568
}
4569

4570
void LoongArch64Emitter::VDIV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4571
	Write32(EncodeVdVjVk(Opcode32::VDIV_H, vd, vj, vk));
4572
}
4573

4574
void LoongArch64Emitter::VDIV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4575
	Write32(EncodeVdVjVk(Opcode32::VDIV_W, vd, vj, vk));
4576
}
4577

4578
void LoongArch64Emitter::VDIV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4579
	Write32(EncodeVdVjVk(Opcode32::VDIV_D, vd, vj, vk));
4580
}
4581

4582
void LoongArch64Emitter::VMOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4583
	Write32(EncodeVdVjVk(Opcode32::VMOD_B, vd, vj, vk));
4584
}
4585

4586
void LoongArch64Emitter::VMOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4587
	Write32(EncodeVdVjVk(Opcode32::VMOD_H, vd, vj, vk));
4588
}
4589

4590
void LoongArch64Emitter::VMOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4591
	Write32(EncodeVdVjVk(Opcode32::VMOD_W, vd, vj, vk));
4592
}
4593

4594
void LoongArch64Emitter::VMOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4595
	Write32(EncodeVdVjVk(Opcode32::VMOD_D, vd, vj, vk));
4596
}
4597

4598
void LoongArch64Emitter::VDIV_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4599
	Write32(EncodeVdVjVk(Opcode32::VDIV_BU, vd, vj, vk));
4600
}
4601

4602
void LoongArch64Emitter::VDIV_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4603
	Write32(EncodeVdVjVk(Opcode32::VDIV_HU, vd, vj, vk));
4604
}
4605

4606
void LoongArch64Emitter::VDIV_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4607
	Write32(EncodeVdVjVk(Opcode32::VDIV_WU, vd, vj, vk));
4608
}
4609

4610
void LoongArch64Emitter::VDIV_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4611
	Write32(EncodeVdVjVk(Opcode32::VDIV_DU, vd, vj, vk));
4612
}
4613

4614
void LoongArch64Emitter::VMOD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4615
	Write32(EncodeVdVjVk(Opcode32::VMOD_BU, vd, vj, vk));
4616
}
4617

4618
void LoongArch64Emitter::VMOD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4619
	Write32(EncodeVdVjVk(Opcode32::VMOD_HU, vd, vj, vk));
4620
}
4621

4622
void LoongArch64Emitter::VMOD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4623
	Write32(EncodeVdVjVk(Opcode32::VMOD_WU, vd, vj, vk));
4624
}
4625

4626
void LoongArch64Emitter::VMOD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4627
	Write32(EncodeVdVjVk(Opcode32::VMOD_DU, vd, vj, vk));
4628
}
4629

4630
void LoongArch64Emitter::VSLL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4631
	Write32(EncodeVdVjVk(Opcode32::VSLL_B, vd, vj, vk));
4632
}
4633

4634
void LoongArch64Emitter::VSLL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4635
	Write32(EncodeVdVjVk(Opcode32::VSLL_H, vd, vj, vk));
4636
}
4637

4638
void LoongArch64Emitter::VSLL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4639
	Write32(EncodeVdVjVk(Opcode32::VSLL_W, vd, vj, vk));
4640
}
4641

4642
void LoongArch64Emitter::VSLL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4643
	Write32(EncodeVdVjVk(Opcode32::VSLL_D, vd, vj, vk));
4644
}
4645

4646
void LoongArch64Emitter::VSRL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4647
	Write32(EncodeVdVjVk(Opcode32::VSRL_B, vd, vj, vk));
4648
}
4649

4650
void LoongArch64Emitter::VSRL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4651
	Write32(EncodeVdVjVk(Opcode32::VSRL_H, vd, vj, vk));
4652
}
4653

4654
void LoongArch64Emitter::VSRL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4655
	Write32(EncodeVdVjVk(Opcode32::VSRL_W, vd, vj, vk));
4656
}
4657

4658
void LoongArch64Emitter::VSRL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4659
	Write32(EncodeVdVjVk(Opcode32::VSRL_D, vd, vj, vk));
4660
}
4661

4662
void LoongArch64Emitter::VSRA_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4663
	Write32(EncodeVdVjVk(Opcode32::VSRA_B, vd, vj, vk));
4664
}
4665

4666
void LoongArch64Emitter::VSRA_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4667
	Write32(EncodeVdVjVk(Opcode32::VSRA_H, vd, vj, vk));
4668
}
4669

4670
void LoongArch64Emitter::VSRA_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4671
	Write32(EncodeVdVjVk(Opcode32::VSRA_W, vd, vj, vk));
4672
}
4673

4674
void LoongArch64Emitter::VSRA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4675
	Write32(EncodeVdVjVk(Opcode32::VSRA_D, vd, vj, vk));
4676
}
4677

4678
void LoongArch64Emitter::VROTR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4679
	Write32(EncodeVdVjVk(Opcode32::VROTR_B, vd, vj, vk));
4680
}
4681

4682
void LoongArch64Emitter::VROTR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4683
	Write32(EncodeVdVjVk(Opcode32::VROTR_H, vd, vj, vk));
4684
}
4685

4686
void LoongArch64Emitter::VROTR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4687
	Write32(EncodeVdVjVk(Opcode32::VROTR_W, vd, vj, vk));
4688
}
4689

4690
void LoongArch64Emitter::VROTR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4691
	Write32(EncodeVdVjVk(Opcode32::VROTR_D, vd, vj, vk));
4692
}
4693

4694
void LoongArch64Emitter::VSRLR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4695
	Write32(EncodeVdVjVk(Opcode32::VSRLR_B, vd, vj, vk));
4696
}
4697

4698
void LoongArch64Emitter::VSRLR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4699
	Write32(EncodeVdVjVk(Opcode32::VSRLR_H, vd, vj, vk));
4700
}
4701

4702
void LoongArch64Emitter::VSRLR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4703
	Write32(EncodeVdVjVk(Opcode32::VSRLR_W, vd, vj, vk));
4704
}
4705

4706
void LoongArch64Emitter::VSRLR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4707
	Write32(EncodeVdVjVk(Opcode32::VSRLR_D, vd, vj, vk));
4708
}
4709

4710
void LoongArch64Emitter::VSRAR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4711
	Write32(EncodeVdVjVk(Opcode32::VSRAR_B, vd, vj, vk));
4712
}
4713

4714
void LoongArch64Emitter::VSRAR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4715
	Write32(EncodeVdVjVk(Opcode32::VSRAR_H, vd, vj, vk));
4716
}
4717

4718
void LoongArch64Emitter::VSRAR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4719
	Write32(EncodeVdVjVk(Opcode32::VSRAR_W, vd, vj, vk));
4720
}
4721

4722
void LoongArch64Emitter::VSRAR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4723
	Write32(EncodeVdVjVk(Opcode32::VSRAR_D, vd, vj, vk));
4724
}
4725

4726
void LoongArch64Emitter::VSRLN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4727
	Write32(EncodeVdVjVk(Opcode32::VSRLN_B_H, vd, vj, vk));
4728
}
4729

4730
void LoongArch64Emitter::VSRLN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4731
	Write32(EncodeVdVjVk(Opcode32::VSRLN_H_W, vd, vj, vk));
4732
}
4733

4734
void LoongArch64Emitter::VSRLN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4735
	Write32(EncodeVdVjVk(Opcode32::VSRLN_W_D, vd, vj, vk));
4736
}
4737

4738
void LoongArch64Emitter::VSRAN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4739
	Write32(EncodeVdVjVk(Opcode32::VSRAN_B_H, vd, vj, vk));
4740
}
4741

4742
void LoongArch64Emitter::VSRAN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4743
	Write32(EncodeVdVjVk(Opcode32::VSRAN_H_W, vd, vj, vk));
4744
}
4745

4746
void LoongArch64Emitter::VSRAN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4747
	Write32(EncodeVdVjVk(Opcode32::VSRAN_W_D, vd, vj, vk));
4748
}
4749

4750
void LoongArch64Emitter::VSRLRN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4751
	Write32(EncodeVdVjVk(Opcode32::VSRLRN_B_H, vd, vj, vk));
4752
}
4753

4754
void LoongArch64Emitter::VSRLRN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4755
	Write32(EncodeVdVjVk(Opcode32::VSRLRN_H_W, vd, vj, vk));
4756
}
4757

4758
void LoongArch64Emitter::VSRLRN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4759
	Write32(EncodeVdVjVk(Opcode32::VSRLRN_W_D, vd, vj, vk));
4760
}
4761

4762
void LoongArch64Emitter::VSRARN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4763
	Write32(EncodeVdVjVk(Opcode32::VSRARN_B_H, vd, vj, vk));
4764
}
4765

4766
void LoongArch64Emitter::VSRARN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4767
	Write32(EncodeVdVjVk(Opcode32::VSRARN_H_W, vd, vj, vk));
4768
}
4769

4770
void LoongArch64Emitter::VSRARN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4771
	Write32(EncodeVdVjVk(Opcode32::VSRARN_W_D, vd, vj, vk));
4772
}
4773

4774
void LoongArch64Emitter::VSSRLN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4775
	Write32(EncodeVdVjVk(Opcode32::VSSRLN_B_H, vd, vj, vk));
4776
}
4777

4778
void LoongArch64Emitter::VSSRLN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4779
	Write32(EncodeVdVjVk(Opcode32::VSSRLN_H_W, vd, vj, vk));
4780
}
4781

4782
void LoongArch64Emitter::VSSRLN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4783
	Write32(EncodeVdVjVk(Opcode32::VSSRLN_W_D, vd, vj, vk));
4784
}
4785

4786
void LoongArch64Emitter::VSSRAN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4787
	Write32(EncodeVdVjVk(Opcode32::VSSRAN_B_H, vd, vj, vk));
4788
}
4789

4790
void LoongArch64Emitter::VSSRAN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4791
	Write32(EncodeVdVjVk(Opcode32::VSSRAN_H_W, vd, vj, vk));
4792
}
4793

4794
void LoongArch64Emitter::VSSRAN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4795
	Write32(EncodeVdVjVk(Opcode32::VSSRAN_W_D, vd, vj, vk));
4796
}
4797

4798
void LoongArch64Emitter::VSSRLRN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4799
	Write32(EncodeVdVjVk(Opcode32::VSSRLRN_B_H, vd, vj, vk));
4800
}
4801

4802
void LoongArch64Emitter::VSSRLRN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4803
	Write32(EncodeVdVjVk(Opcode32::VSSRLRN_H_W, vd, vj, vk));
4804
}
4805

4806
void LoongArch64Emitter::VSSRLRN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4807
	Write32(EncodeVdVjVk(Opcode32::VSSRLRN_W_D, vd, vj, vk));
4808
}
4809

4810
void LoongArch64Emitter::VSSRARN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4811
	Write32(EncodeVdVjVk(Opcode32::VSSRARN_B_H, vd, vj, vk));
4812
}
4813

4814
void LoongArch64Emitter::VSSRARN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4815
	Write32(EncodeVdVjVk(Opcode32::VSSRARN_H_W, vd, vj, vk));
4816
}
4817

4818
void LoongArch64Emitter::VSSRARN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4819
	Write32(EncodeVdVjVk(Opcode32::VSSRARN_W_D, vd, vj, vk));
4820
}
4821

4822
void LoongArch64Emitter::VSSRLN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4823
	Write32(EncodeVdVjVk(Opcode32::VSSRLN_BU_H, vd, vj, vk));
4824
}
4825

4826
void LoongArch64Emitter::VSSRLN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4827
	Write32(EncodeVdVjVk(Opcode32::VSSRLN_HU_W, vd, vj, vk));
4828
}
4829

4830
void LoongArch64Emitter::VSSRLN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4831
	Write32(EncodeVdVjVk(Opcode32::VSSRLN_WU_D, vd, vj, vk));
4832
}
4833

4834
void LoongArch64Emitter::VSSRAN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4835
	Write32(EncodeVdVjVk(Opcode32::VSSRAN_BU_H, vd, vj, vk));
4836
}
4837

4838
void LoongArch64Emitter::VSSRAN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4839
	Write32(EncodeVdVjVk(Opcode32::VSSRAN_HU_W, vd, vj, vk));
4840
}
4841

4842
void LoongArch64Emitter::VSSRAN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4843
	Write32(EncodeVdVjVk(Opcode32::VSSRAN_WU_D, vd, vj, vk));
4844
}
4845

4846
void LoongArch64Emitter::VSSRLRN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4847
	Write32(EncodeVdVjVk(Opcode32::VSSRLRN_BU_H, vd, vj, vk));
4848
}
4849

4850
void LoongArch64Emitter::VSSRLRN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4851
	Write32(EncodeVdVjVk(Opcode32::VSSRLRN_HU_W, vd, vj, vk));
4852
}
4853

4854
void LoongArch64Emitter::VSSRLRN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4855
	Write32(EncodeVdVjVk(Opcode32::VSSRLRN_WU_D, vd, vj, vk));
4856
}
4857

4858
void LoongArch64Emitter::VSSRARN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4859
	Write32(EncodeVdVjVk(Opcode32::VSSRARN_BU_H, vd, vj, vk));
4860
}
4861

4862
void LoongArch64Emitter::VSSRARN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4863
	Write32(EncodeVdVjVk(Opcode32::VSSRARN_HU_W, vd, vj, vk));
4864
}
4865

4866
void LoongArch64Emitter::VSSRARN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4867
	Write32(EncodeVdVjVk(Opcode32::VSSRARN_WU_D, vd, vj, vk));
4868
}
4869

4870
void LoongArch64Emitter::VBITCLR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4871
	Write32(EncodeVdVjVk(Opcode32::VBITCLR_B, vd, vj, vk));
4872
}
4873

4874
void LoongArch64Emitter::VBITCLR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4875
	Write32(EncodeVdVjVk(Opcode32::VBITCLR_H, vd, vj, vk));
4876
}
4877

4878
void LoongArch64Emitter::VBITCLR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4879
	Write32(EncodeVdVjVk(Opcode32::VBITCLR_W, vd, vj, vk));
4880
}
4881

4882
void LoongArch64Emitter::VBITCLR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4883
	Write32(EncodeVdVjVk(Opcode32::VBITCLR_D, vd, vj, vk));
4884
}
4885

4886
void LoongArch64Emitter::VBITSET_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4887
	Write32(EncodeVdVjVk(Opcode32::VBITSET_B, vd, vj, vk));
4888
}
4889

4890
void LoongArch64Emitter::VBITSET_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4891
	Write32(EncodeVdVjVk(Opcode32::VBITSET_H, vd, vj, vk));
4892
}
4893

4894
void LoongArch64Emitter::VBITSET_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4895
	Write32(EncodeVdVjVk(Opcode32::VBITSET_W, vd, vj, vk));
4896
}
4897

4898
void LoongArch64Emitter::VBITSET_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4899
	Write32(EncodeVdVjVk(Opcode32::VBITSET_D, vd, vj, vk));
4900
}
4901

4902
void LoongArch64Emitter::VBITREV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4903
	Write32(EncodeVdVjVk(Opcode32::VBITREV_B, vd, vj, vk));
4904
}
4905

4906
void LoongArch64Emitter::VBITREV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4907
	Write32(EncodeVdVjVk(Opcode32::VBITREV_H, vd, vj, vk));
4908
}
4909

4910
void LoongArch64Emitter::VBITREV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4911
	Write32(EncodeVdVjVk(Opcode32::VBITREV_W, vd, vj, vk));
4912
}
4913

4914
void LoongArch64Emitter::VBITREV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4915
	Write32(EncodeVdVjVk(Opcode32::VBITREV_D, vd, vj, vk));
4916
}
4917

4918
void LoongArch64Emitter::VPACKEV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4919
	Write32(EncodeVdVjVk(Opcode32::VPACKEV_B, vd, vj, vk));
4920
}
4921

4922
void LoongArch64Emitter::VPACKEV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4923
	Write32(EncodeVdVjVk(Opcode32::VPACKEV_H, vd, vj, vk));
4924
}
4925

4926
void LoongArch64Emitter::VPACKEV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4927
	Write32(EncodeVdVjVk(Opcode32::VPACKEV_W, vd, vj, vk));
4928
}
4929

4930
void LoongArch64Emitter::VPACKEV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4931
	Write32(EncodeVdVjVk(Opcode32::VPACKEV_D, vd, vj, vk));
4932
}
4933

4934
void LoongArch64Emitter::VPACKOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4935
	Write32(EncodeVdVjVk(Opcode32::VPACKOD_B, vd, vj, vk));
4936
}
4937

4938
void LoongArch64Emitter::VPACKOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4939
	Write32(EncodeVdVjVk(Opcode32::VPACKOD_H, vd, vj, vk));
4940
}
4941

4942
void LoongArch64Emitter::VPACKOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4943
	Write32(EncodeVdVjVk(Opcode32::VPACKOD_W, vd, vj, vk));
4944
}
4945

4946
void LoongArch64Emitter::VPACKOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4947
	Write32(EncodeVdVjVk(Opcode32::VPACKOD_D, vd, vj, vk));
4948
}
4949

4950
void LoongArch64Emitter::VILVL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4951
	Write32(EncodeVdVjVk(Opcode32::VILVL_B, vd, vj, vk));
4952
}
4953

4954
void LoongArch64Emitter::VILVL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4955
	Write32(EncodeVdVjVk(Opcode32::VILVL_H, vd, vj, vk));
4956
}
4957

4958
void LoongArch64Emitter::VILVL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4959
	Write32(EncodeVdVjVk(Opcode32::VILVL_W, vd, vj, vk));
4960
}
4961

4962
void LoongArch64Emitter::VILVL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4963
	Write32(EncodeVdVjVk(Opcode32::VILVL_D, vd, vj, vk));
4964
}
4965

4966
void LoongArch64Emitter::VILVH_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4967
	Write32(EncodeVdVjVk(Opcode32::VILVH_B, vd, vj, vk));
4968
}
4969

4970
void LoongArch64Emitter::VILVH_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4971
	Write32(EncodeVdVjVk(Opcode32::VILVH_H, vd, vj, vk));
4972
}
4973

4974
void LoongArch64Emitter::VILVH_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4975
	Write32(EncodeVdVjVk(Opcode32::VILVH_W, vd, vj, vk));
4976
}
4977

4978
void LoongArch64Emitter::VILVH_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4979
	Write32(EncodeVdVjVk(Opcode32::VILVH_D, vd, vj, vk));
4980
}
4981

4982
void LoongArch64Emitter::VPICKEV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4983
	Write32(EncodeVdVjVk(Opcode32::VPICKEV_B, vd, vj, vk));
4984
}
4985

4986
void LoongArch64Emitter::VPICKEV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4987
	Write32(EncodeVdVjVk(Opcode32::VPICKEV_H, vd, vj, vk));
4988
}
4989

4990
void LoongArch64Emitter::VPICKEV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4991
	Write32(EncodeVdVjVk(Opcode32::VPICKEV_W, vd, vj, vk));
4992
}
4993

4994
void LoongArch64Emitter::VPICKEV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4995
	Write32(EncodeVdVjVk(Opcode32::VPICKEV_D, vd, vj, vk));
4996
}
4997

4998
void LoongArch64Emitter::VPICKOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
4999
	Write32(EncodeVdVjVk(Opcode32::VPICKOD_B, vd, vj, vk));
5000
}
5001

5002
void LoongArch64Emitter::VPICKOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5003
	Write32(EncodeVdVjVk(Opcode32::VPICKOD_H, vd, vj, vk));
5004
}
5005

5006
void LoongArch64Emitter::VPICKOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5007
	Write32(EncodeVdVjVk(Opcode32::VPICKOD_W, vd, vj, vk));
5008
}
5009

5010
void LoongArch64Emitter::VPICKOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5011
	Write32(EncodeVdVjVk(Opcode32::VPICKOD_D, vd, vj, vk));
5012
}
5013

5014
void LoongArch64Emitter::VREPLVE_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) {
5015
	Write32(EncodeVdVjK(Opcode32::VREPLVE_B, vd, vj, rk));
5016
}
5017

5018
void LoongArch64Emitter::VREPLVE_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) {
5019
	Write32(EncodeVdVjK(Opcode32::VREPLVE_H, vd, vj, rk));
5020
}
5021

5022
void LoongArch64Emitter::VREPLVE_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) {
5023
	Write32(EncodeVdVjK(Opcode32::VREPLVE_W, vd, vj, rk));
5024
}
5025

5026
void LoongArch64Emitter::VREPLVE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) {
5027
	Write32(EncodeVdVjK(Opcode32::VREPLVE_D, vd, vj, rk));
5028
}
5029

5030
void LoongArch64Emitter::VAND_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5031
	Write32(EncodeVdVjVk(Opcode32::VAND_V, vd, vj, vk));
5032
}
5033

5034
void LoongArch64Emitter::VOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5035
	Write32(EncodeVdVjVk(Opcode32::VOR_V, vd, vj, vk));
5036
}
5037

5038
void LoongArch64Emitter::VXOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5039
	Write32(EncodeVdVjVk(Opcode32::VXOR_V, vd, vj, vk));
5040
}
5041

5042
void LoongArch64Emitter::VNOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5043
	Write32(EncodeVdVjVk(Opcode32::VNOR_V, vd, vj, vk));
5044
}
5045

5046
void LoongArch64Emitter::VANDN_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5047
	Write32(EncodeVdVjVk(Opcode32::VANDN_V, vd, vj, vk));
5048
}
5049

5050
void LoongArch64Emitter::VORN_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5051
	Write32(EncodeVdVjVk(Opcode32::VORN_V, vd, vj, vk));
5052
}
5053

5054
void LoongArch64Emitter::VFRSTP_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5055
	Write32(EncodeVdVjVk(Opcode32::VFRSTP_B, vd, vj, vk));
5056
}
5057

5058
void LoongArch64Emitter::VFRSTP_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5059
	Write32(EncodeVdVjVk(Opcode32::VFRSTP_H, vd, vj, vk));
5060
}
5061

5062
void LoongArch64Emitter::VADD_Q(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5063
	Write32(EncodeVdVjVk(Opcode32::VADD_Q, vd, vj, vk));
5064
}
5065

5066
void LoongArch64Emitter::VSUB_Q(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5067
	Write32(EncodeVdVjVk(Opcode32::VSUB_Q, vd, vj, vk));
5068
}
5069

5070
void LoongArch64Emitter::VSIGNCOV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5071
	Write32(EncodeVdVjVk(Opcode32::VSIGNCOV_B, vd, vj, vk));
5072
}
5073

5074
void LoongArch64Emitter::VSIGNCOV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5075
	Write32(EncodeVdVjVk(Opcode32::VSIGNCOV_H, vd, vj, vk));
5076
}
5077

5078
void LoongArch64Emitter::VSIGNCOV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5079
	Write32(EncodeVdVjVk(Opcode32::VSIGNCOV_W, vd, vj, vk));
5080
}
5081

5082
void LoongArch64Emitter::VSIGNCOV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5083
	Write32(EncodeVdVjVk(Opcode32::VSIGNCOV_D, vd, vj, vk));
5084
}
5085

5086
void LoongArch64Emitter::VFADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5087
	Write32(EncodeVdVjVk(Opcode32::VFADD_S, vd, vj, vk));
5088
}
5089

5090
void LoongArch64Emitter::VFADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5091
	Write32(EncodeVdVjVk(Opcode32::VFADD_D, vd, vj, vk));
5092
}
5093

5094
void LoongArch64Emitter::VFSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5095
	Write32(EncodeVdVjVk(Opcode32::VFSUB_S, vd, vj, vk));
5096
}
5097

5098
void LoongArch64Emitter::VFSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5099
	Write32(EncodeVdVjVk(Opcode32::VFSUB_D, vd, vj, vk));
5100
}
5101

5102
void LoongArch64Emitter::VFMUL_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5103
	Write32(EncodeVdVjVk(Opcode32::VFMUL_S, vd, vj, vk));
5104
}
5105

5106
void LoongArch64Emitter::VFMUL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5107
	Write32(EncodeVdVjVk(Opcode32::VFMUL_D, vd, vj, vk));
5108
}
5109

5110
void LoongArch64Emitter::VFDIV_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5111
	Write32(EncodeVdVjVk(Opcode32::VFDIV_S, vd, vj, vk));
5112
}
5113

5114
void LoongArch64Emitter::VFDIV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5115
	Write32(EncodeVdVjVk(Opcode32::VFDIV_D, vd, vj, vk));
5116
}
5117

5118
void LoongArch64Emitter::VFMAX_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5119
	Write32(EncodeVdVjVk(Opcode32::VFMAX_S, vd, vj, vk));
5120
}
5121

5122
void LoongArch64Emitter::VFMAX_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5123
	Write32(EncodeVdVjVk(Opcode32::VFMAX_D, vd, vj, vk));
5124
}
5125

5126
void LoongArch64Emitter::VFMIN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5127
	Write32(EncodeVdVjVk(Opcode32::VFMIN_S, vd, vj, vk));
5128
}
5129

5130
void LoongArch64Emitter::VFMIN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5131
	Write32(EncodeVdVjVk(Opcode32::VFMIN_D, vd, vj, vk));
5132
}
5133

5134
void LoongArch64Emitter::VFMAXA_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5135
	Write32(EncodeVdVjVk(Opcode32::VFMAXA_S, vd, vj, vk));
5136
}
5137

5138
void LoongArch64Emitter::VFMAXA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5139
	Write32(EncodeVdVjVk(Opcode32::VFMAXA_D, vd, vj, vk));
5140
}
5141

5142
void LoongArch64Emitter::VFMINA_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5143
	Write32(EncodeVdVjVk(Opcode32::VFMINA_S, vd, vj, vk));
5144
}
5145

5146
void LoongArch64Emitter::VFMINA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5147
	Write32(EncodeVdVjVk(Opcode32::VFMINA_D, vd, vj, vk));
5148
}
5149

5150
void LoongArch64Emitter::VFCVT_H_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5151
	Write32(EncodeVdVjVk(Opcode32::VFCVT_H_S, vd, vj, vk));
5152
}
5153

5154
void LoongArch64Emitter::VFCVT_S_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5155
	Write32(EncodeVdVjVk(Opcode32::VFCVT_S_D, vd, vj, vk));
5156
}
5157

5158
void LoongArch64Emitter::VFFINT_S_L(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5159
	Write32(EncodeVdVjVk(Opcode32::VFFINT_S_L, vd, vj, vk));
5160
}
5161

5162
void LoongArch64Emitter::VFTINT_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5163
	Write32(EncodeVdVjVk(Opcode32::VFTINT_W_D, vd, vj, vk));
5164
}
5165

5166
void LoongArch64Emitter::VFTINTRM_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5167
	Write32(EncodeVdVjVk(Opcode32::VFTINTRM_W_D, vd, vj, vk));
5168
}
5169

5170
void LoongArch64Emitter::VFTINTRP_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5171
	Write32(EncodeVdVjVk(Opcode32::VFTINTRP_W_D, vd, vj, vk));
5172
}
5173

5174
void LoongArch64Emitter::VFTINTRZ_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5175
	Write32(EncodeVdVjVk(Opcode32::VFTINTRZ_W_D, vd, vj, vk));
5176
}
5177

5178
void LoongArch64Emitter::VFTINTRNE_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5179
	Write32(EncodeVdVjVk(Opcode32::VFTINTRNE_W_D, vd, vj, vk));
5180
}
5181

5182
void LoongArch64Emitter::VSHUF_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5183
	Write32(EncodeVdVjVk(Opcode32::VSHUF_H, vd, vj, vk));
5184
}
5185

5186
void LoongArch64Emitter::VSHUF_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5187
	Write32(EncodeVdVjVk(Opcode32::VSHUF_W, vd, vj, vk));
5188
}
5189

5190
void LoongArch64Emitter::VSHUF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) {
5191
	Write32(EncodeVdVjVk(Opcode32::VSHUF_D, vd, vj, vk));
5192
}
5193

5194
void LoongArch64Emitter::VSEQI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5195
	Write32(EncodeVdVjSk5(Opcode32::VSEQI_B, vd, vj, si5));
5196
}
5197

5198
void LoongArch64Emitter::VSEQI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5199
	Write32(EncodeVdVjSk5(Opcode32::VSEQI_H, vd, vj, si5));
5200
}
5201

5202
void LoongArch64Emitter::VSEQI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5203
	Write32(EncodeVdVjSk5(Opcode32::VSEQI_W, vd, vj, si5));
5204
}
5205

5206
void LoongArch64Emitter::VSEQI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5207
	Write32(EncodeVdVjSk5(Opcode32::VSEQI_D, vd, vj, si5));
5208
}
5209

5210
void LoongArch64Emitter::VSLEI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5211
	Write32(EncodeVdVjSk5(Opcode32::VSLEI_B, vd, vj, si5));
5212
}
5213

5214
void LoongArch64Emitter::VSLEI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5215
	Write32(EncodeVdVjSk5(Opcode32::VSLEI_H, vd, vj, si5));
5216
}
5217

5218
void LoongArch64Emitter::VSLEI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5219
	Write32(EncodeVdVjSk5(Opcode32::VSLEI_W, vd, vj, si5));
5220
}
5221

5222
void LoongArch64Emitter::VSLEI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5223
	Write32(EncodeVdVjSk5(Opcode32::VSLEI_D, vd, vj, si5));
5224
}
5225

5226
void LoongArch64Emitter::VSLEI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5227
	Write32(EncodeVdVjUk5(Opcode32::VSLEI_BU, vd, vj, ui5));
5228
}
5229

5230
void LoongArch64Emitter::VSLEI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5231
	Write32(EncodeVdVjUk5(Opcode32::VSLEI_HU, vd, vj, ui5));
5232
}
5233

5234
void LoongArch64Emitter::VSLEI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5235
	Write32(EncodeVdVjUk5(Opcode32::VSLEI_WU, vd, vj, ui5));
5236
}
5237

5238
void LoongArch64Emitter::VSLEI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5239
	Write32(EncodeVdVjUk5(Opcode32::VSLEI_DU, vd, vj, ui5));
5240
}
5241

5242
void LoongArch64Emitter::VSLTI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5243
	Write32(EncodeVdVjSk5(Opcode32::VSLTI_B, vd, vj, si5));
5244
}
5245

5246
void LoongArch64Emitter::VSLTI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5247
	Write32(EncodeVdVjSk5(Opcode32::VSLTI_H, vd, vj, si5));
5248
}
5249

5250
void LoongArch64Emitter::VSLTI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5251
	Write32(EncodeVdVjSk5(Opcode32::VSLTI_W, vd, vj, si5));
5252
}
5253

5254
void LoongArch64Emitter::VSLTI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5255
	Write32(EncodeVdVjSk5(Opcode32::VSLTI_D, vd, vj, si5));
5256
}
5257

5258
void LoongArch64Emitter::VSLTI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5259
	Write32(EncodeVdVjUk5(Opcode32::VSLTI_BU, vd, vj, ui5));
5260
}
5261

5262
void LoongArch64Emitter::VSLTI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5263
	Write32(EncodeVdVjUk5(Opcode32::VSLTI_HU, vd, vj, ui5));
5264
}
5265

5266
void LoongArch64Emitter::VSLTI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5267
	Write32(EncodeVdVjUk5(Opcode32::VSLTI_WU, vd, vj, ui5));
5268
}
5269

5270
void LoongArch64Emitter::VSLTI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5271
	Write32(EncodeVdVjUk5(Opcode32::VSLTI_DU, vd, vj, ui5));
5272
}
5273

5274
void LoongArch64Emitter::VADDI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5275
	Write32(EncodeVdVjUk5(Opcode32::VADDI_BU, vd, vj, ui5));
5276
}
5277

5278
void LoongArch64Emitter::VADDI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5279
	Write32(EncodeVdVjUk5(Opcode32::VADDI_HU, vd, vj, ui5));
5280
}
5281

5282
void LoongArch64Emitter::VADDI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5283
	Write32(EncodeVdVjUk5(Opcode32::VADDI_WU, vd, vj, ui5));
5284
}
5285

5286
void LoongArch64Emitter::VADDI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5287
	Write32(EncodeVdVjUk5(Opcode32::VADDI_DU, vd, vj, ui5));
5288
}
5289

5290
void LoongArch64Emitter::VSUBI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5291
	Write32(EncodeVdVjUk5(Opcode32::VSUBI_BU, vd, vj, ui5));
5292
}
5293

5294
void LoongArch64Emitter::VSUBI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5295
	Write32(EncodeVdVjUk5(Opcode32::VSUBI_HU, vd, vj, ui5));
5296
}
5297

5298
void LoongArch64Emitter::VSUBI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5299
	Write32(EncodeVdVjUk5(Opcode32::VSUBI_WU, vd, vj, ui5));
5300
}
5301

5302
void LoongArch64Emitter::VSUBI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5303
	Write32(EncodeVdVjUk5(Opcode32::VSUBI_DU, vd, vj, ui5));
5304
}
5305

5306
void LoongArch64Emitter::VBSLL_V(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5307
	Write32(EncodeVdVjUk5(Opcode32::VBSLL_V, vd, vj, ui5));
5308
}
5309

5310
void LoongArch64Emitter::VBSRL_V(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5311
	Write32(EncodeVdVjUk5(Opcode32::VBSRL_V, vd, vj, ui5));
5312
}
5313

5314
void LoongArch64Emitter::VMAXI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5315
	Write32(EncodeVdVjSk5(Opcode32::VMAXI_B, vd, vj, si5));
5316
}
5317

5318
void LoongArch64Emitter::VMAXI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5319
	Write32(EncodeVdVjSk5(Opcode32::VMAXI_H, vd, vj, si5));
5320
}
5321

5322
void LoongArch64Emitter::VMAXI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5323
	Write32(EncodeVdVjSk5(Opcode32::VMAXI_W, vd, vj, si5));
5324
}
5325

5326
void LoongArch64Emitter::VMAXI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5327
	Write32(EncodeVdVjSk5(Opcode32::VMAXI_D, vd, vj, si5));
5328
}
5329

5330
void LoongArch64Emitter::VMINI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5331
	Write32(EncodeVdVjSk5(Opcode32::VMINI_B, vd, vj, si5));
5332
}
5333

5334
void LoongArch64Emitter::VMINI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5335
	Write32(EncodeVdVjSk5(Opcode32::VMINI_H, vd, vj, si5));
5336
}
5337

5338
void LoongArch64Emitter::VMINI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5339
	Write32(EncodeVdVjSk5(Opcode32::VMINI_W, vd, vj, si5));
5340
}
5341

5342
void LoongArch64Emitter::VMINI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) {
5343
	Write32(EncodeVdVjSk5(Opcode32::VMINI_D, vd, vj, si5));
5344
}
5345

5346
void LoongArch64Emitter::VMAXI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5347
	Write32(EncodeVdVjUk5(Opcode32::VMAXI_BU, vd, vj, ui5));
5348
}
5349

5350
void LoongArch64Emitter::VMAXI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5351
	Write32(EncodeVdVjUk5(Opcode32::VMAXI_HU, vd, vj, ui5));
5352
}
5353

5354
void LoongArch64Emitter::VMAXI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5355
	Write32(EncodeVdVjUk5(Opcode32::VMAXI_WU, vd, vj, ui5));
5356
}
5357

5358
void LoongArch64Emitter::VMAXI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5359
	Write32(EncodeVdVjUk5(Opcode32::VMAXI_DU, vd, vj, ui5));
5360
}
5361

5362
void LoongArch64Emitter::VMINI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5363
	Write32(EncodeVdVjUk5(Opcode32::VMINI_BU, vd, vj, ui5));
5364
}
5365

5366
void LoongArch64Emitter::VMINI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5367
	Write32(EncodeVdVjUk5(Opcode32::VMINI_HU, vd, vj, ui5));
5368
}
5369

5370
void LoongArch64Emitter::VMINI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5371
	Write32(EncodeVdVjUk5(Opcode32::VMINI_WU, vd, vj, ui5));
5372
}
5373

5374
void LoongArch64Emitter::VMINI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5375
	Write32(EncodeVdVjUk5(Opcode32::VMINI_DU, vd, vj, ui5));
5376
}
5377

5378
void LoongArch64Emitter::VFRSTPI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5379
	Write32(EncodeVdVjUk5(Opcode32::VFRSTPI_B, vd, vj, ui5));
5380
}
5381

5382
void LoongArch64Emitter::VFRSTPI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5383
	Write32(EncodeVdVjUk5(Opcode32::VFRSTPI_H, vd, vj, ui5));
5384
}
5385

5386
void LoongArch64Emitter::VCLO_B(LoongArch64Reg vd, LoongArch64Reg vj) {
5387
	Write32(EncodeVdVj(Opcode32::VCLO_B, vd, vj));
5388
}
5389

5390
void LoongArch64Emitter::VCLO_H(LoongArch64Reg vd, LoongArch64Reg vj) {
5391
	Write32(EncodeVdVj(Opcode32::VCLO_H, vd, vj));
5392
}
5393

5394
void LoongArch64Emitter::VCLO_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5395
	Write32(EncodeVdVj(Opcode32::VCLO_W, vd, vj));
5396
}
5397

5398
void LoongArch64Emitter::VCLO_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5399
	Write32(EncodeVdVj(Opcode32::VCLO_D, vd, vj));
5400
}
5401

5402
void LoongArch64Emitter::VCLZ_B(LoongArch64Reg vd, LoongArch64Reg vj) {
5403
	Write32(EncodeVdVj(Opcode32::VCLZ_B, vd, vj));
5404
}
5405

5406
void LoongArch64Emitter::VCLZ_H(LoongArch64Reg vd, LoongArch64Reg vj) {
5407
	Write32(EncodeVdVj(Opcode32::VCLZ_H, vd, vj));
5408
}
5409

5410
void LoongArch64Emitter::VCLZ_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5411
	Write32(EncodeVdVj(Opcode32::VCLZ_W, vd, vj));
5412
}
5413

5414
void LoongArch64Emitter::VCLZ_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5415
	Write32(EncodeVdVj(Opcode32::VCLZ_D, vd, vj));
5416
}
5417

5418
void LoongArch64Emitter::VPCNT_B(LoongArch64Reg vd, LoongArch64Reg vj) {
5419
	Write32(EncodeVdVj(Opcode32::VPCNT_B, vd, vj));
5420
}
5421

5422
void LoongArch64Emitter::VPCNT_H(LoongArch64Reg vd, LoongArch64Reg vj) {
5423
	Write32(EncodeVdVj(Opcode32::VPCNT_H, vd, vj));
5424
}
5425

5426
void LoongArch64Emitter::VPCNT_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5427
	Write32(EncodeVdVj(Opcode32::VPCNT_W, vd, vj));
5428
}
5429

5430
void LoongArch64Emitter::VPCNT_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5431
	Write32(EncodeVdVj(Opcode32::VPCNT_D, vd, vj));
5432
}
5433

5434
void LoongArch64Emitter::VNEG_B(LoongArch64Reg vd, LoongArch64Reg vj) {
5435
	Write32(EncodeVdVj(Opcode32::VNEG_B, vd, vj));
5436
}
5437

5438
void LoongArch64Emitter::VNEG_H(LoongArch64Reg vd, LoongArch64Reg vj) {
5439
	Write32(EncodeVdVj(Opcode32::VNEG_H, vd, vj));
5440
}
5441

5442
void LoongArch64Emitter::VNEG_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5443
	Write32(EncodeVdVj(Opcode32::VNEG_W, vd, vj));
5444
}
5445

5446
void LoongArch64Emitter::VNEG_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5447
	Write32(EncodeVdVj(Opcode32::VNEG_D, vd, vj));
5448
}
5449

5450
void LoongArch64Emitter::VMSKLTZ_B(LoongArch64Reg vd, LoongArch64Reg vj) {
5451
	Write32(EncodeVdVj(Opcode32::VMSKLTZ_B, vd, vj));
5452
}
5453

5454
void LoongArch64Emitter::VMSKLTZ_H(LoongArch64Reg vd, LoongArch64Reg vj) {
5455
	Write32(EncodeVdVj(Opcode32::VMSKLTZ_H, vd, vj));
5456
}
5457

5458
void LoongArch64Emitter::VMSKLTZ_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5459
	Write32(EncodeVdVj(Opcode32::VMSKLTZ_W, vd, vj));
5460
}
5461

5462
void LoongArch64Emitter::VMSKLTZ_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5463
	Write32(EncodeVdVj(Opcode32::VMSKLTZ_D, vd, vj));
5464
}
5465

5466
void LoongArch64Emitter::VMSKGEZ_B(LoongArch64Reg vd, LoongArch64Reg vj) {
5467
	Write32(EncodeVdVj(Opcode32::VMSKGEZ_B, vd, vj));
5468
}
5469

5470
void LoongArch64Emitter::VMSKNZ_B(LoongArch64Reg vd, LoongArch64Reg vj) {
5471
	Write32(EncodeVdVj(Opcode32::VMSKNZ_B, vd, vj));
5472
}
5473

5474
void LoongArch64Emitter::VSETEQZ_V(LoongArch64CFR cd, LoongArch64Reg vj) {
5475
	Write32(EncodeCdVj(Opcode32::VSETEQZ_V, cd, vj));
5476
}
5477

5478
void LoongArch64Emitter::VSETNEZ_V(LoongArch64CFR cd, LoongArch64Reg vj) {
5479
	Write32(EncodeCdVj(Opcode32::VSETNEZ_V, cd, vj));
5480
}
5481

5482
void LoongArch64Emitter::VSETANYEQZ_B(LoongArch64CFR cd, LoongArch64Reg vj) {
5483
	Write32(EncodeCdVj(Opcode32::VSETANYEQZ_B, cd, vj));
5484
}
5485

5486
void LoongArch64Emitter::VSETANYEQZ_H(LoongArch64CFR cd, LoongArch64Reg vj) {
5487
	Write32(EncodeCdVj(Opcode32::VSETANYEQZ_H, cd, vj));
5488
}
5489

5490
void LoongArch64Emitter::VSETANYEQZ_W(LoongArch64CFR cd, LoongArch64Reg vj) {
5491
	Write32(EncodeCdVj(Opcode32::VSETANYEQZ_W, cd, vj));
5492
}
5493

5494
void LoongArch64Emitter::VSETANYEQZ_D(LoongArch64CFR cd, LoongArch64Reg vj) {
5495
	Write32(EncodeCdVj(Opcode32::VSETANYEQZ_D, cd, vj));
5496
}
5497

5498
void LoongArch64Emitter::VSETALLNEZ_B(LoongArch64CFR cd, LoongArch64Reg vj) {
5499
	Write32(EncodeCdVj(Opcode32::VSETALLNEZ_B, cd, vj));
5500
}
5501

5502
void LoongArch64Emitter::VSETALLNEZ_H(LoongArch64CFR cd, LoongArch64Reg vj) {
5503
	Write32(EncodeCdVj(Opcode32::VSETALLNEZ_H, cd, vj));
5504
}
5505

5506
void LoongArch64Emitter::VSETALLNEZ_W(LoongArch64CFR cd, LoongArch64Reg vj) {
5507
	Write32(EncodeCdVj(Opcode32::VSETALLNEZ_W, cd, vj));
5508
}
5509

5510
void LoongArch64Emitter::VSETALLNEZ_D(LoongArch64CFR cd, LoongArch64Reg vj) {
5511
	Write32(EncodeCdVj(Opcode32::VSETALLNEZ_D, cd, vj));
5512
}
5513

5514
void LoongArch64Emitter::VFLOGB_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5515
	Write32(EncodeVdVj(Opcode32::VFLOGB_S, vd, vj));
5516
}
5517

5518
void LoongArch64Emitter::VFLOGB_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5519
	Write32(EncodeVdVj(Opcode32::VFLOGB_D, vd, vj));
5520
}
5521

5522
void LoongArch64Emitter::VFCLASS_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5523
	Write32(EncodeVdVj(Opcode32::VFCLASS_S, vd, vj));
5524
}
5525

5526
void LoongArch64Emitter::VFCLASS_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5527
	Write32(EncodeVdVj(Opcode32::VFCLASS_D, vd, vj));
5528
}
5529

5530
void LoongArch64Emitter::VFSQRT_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5531
	Write32(EncodeVdVj(Opcode32::VFSQRT_S, vd, vj));
5532
}
5533

5534
void LoongArch64Emitter::VFSQRT_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5535
	Write32(EncodeVdVj(Opcode32::VFSQRT_D, vd, vj));
5536
}
5537

5538
void LoongArch64Emitter::VFRECIP_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5539
	Write32(EncodeVdVj(Opcode32::VFRECIP_S, vd, vj));
5540
}
5541

5542
void LoongArch64Emitter::VFRECIP_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5543
	Write32(EncodeVdVj(Opcode32::VFRECIP_D, vd, vj));
5544
}
5545

5546
void LoongArch64Emitter::VFRSQRT_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5547
	Write32(EncodeVdVj(Opcode32::VFRSQRT_S, vd, vj));
5548
}
5549

5550
void LoongArch64Emitter::VFRSQRT_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5551
	Write32(EncodeVdVj(Opcode32::VFRSQRT_D, vd, vj));
5552
}
5553

5554
void LoongArch64Emitter::VFRECIPE_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5555
	Write32(EncodeVdVj(Opcode32::VFRECIPE_S, vd, vj));
5556
}
5557

5558
void LoongArch64Emitter::VFRECIPE_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5559
	Write32(EncodeVdVj(Opcode32::VFRECIPE_D, vd, vj));
5560
}
5561

5562
void LoongArch64Emitter::VFRSQRTE_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5563
	Write32(EncodeVdVj(Opcode32::VFRSQRTE_S, vd, vj));
5564
}
5565

5566
void LoongArch64Emitter::VFRSQRTE_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5567
	Write32(EncodeVdVj(Opcode32::VFRSQRTE_D, vd, vj));
5568
}
5569

5570
void LoongArch64Emitter::VFRINT_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5571
	Write32(EncodeVdVj(Opcode32::VFRINT_S, vd, vj));
5572
}
5573

5574
void LoongArch64Emitter::VFRINT_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5575
	Write32(EncodeVdVj(Opcode32::VFRINT_D, vd, vj));
5576
}
5577

5578
void LoongArch64Emitter::VFRINTRM_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5579
	Write32(EncodeVdVj(Opcode32::VFRINTRM_S, vd, vj));
5580
}
5581

5582
void LoongArch64Emitter::VFRINTRM_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5583
	Write32(EncodeVdVj(Opcode32::VFRINTRM_D, vd, vj));
5584
}
5585

5586
void LoongArch64Emitter::VFRINTRP_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5587
	Write32(EncodeVdVj(Opcode32::VFRINTRP_S, vd, vj));
5588
}
5589

5590
void LoongArch64Emitter::VFRINTRP_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5591
	Write32(EncodeVdVj(Opcode32::VFRINTRP_D, vd, vj));
5592
}
5593

5594
void LoongArch64Emitter::VFRINTRZ_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5595
	Write32(EncodeVdVj(Opcode32::VFRINTRZ_S, vd, vj));
5596
}
5597

5598
void LoongArch64Emitter::VFRINTRZ_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5599
	Write32(EncodeVdVj(Opcode32::VFRINTRZ_D, vd, vj));
5600
}
5601

5602
void LoongArch64Emitter::VFRINTRNE_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5603
	Write32(EncodeVdVj(Opcode32::VFRINTRNE_S, vd, vj));
5604
}
5605

5606
void LoongArch64Emitter::VFRINTRNE_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5607
	Write32(EncodeVdVj(Opcode32::VFRINTRNE_D, vd, vj));
5608
}
5609

5610
void LoongArch64Emitter::VFCVTL_S_H(LoongArch64Reg vd, LoongArch64Reg vj) {
5611
	Write32(EncodeVdVj(Opcode32::VFCVTL_S_H, vd, vj));
5612
}
5613

5614
void LoongArch64Emitter::VFCVTH_S_H(LoongArch64Reg vd, LoongArch64Reg vj) {
5615
	Write32(EncodeVdVj(Opcode32::VFCVTH_S_H, vd, vj));
5616
}
5617

5618
void LoongArch64Emitter::VFCVTL_D_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5619
	Write32(EncodeVdVj(Opcode32::VFCVTL_D_S, vd, vj));
5620
}
5621

5622
void LoongArch64Emitter::VFCVTH_D_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5623
	Write32(EncodeVdVj(Opcode32::VFCVTH_D_S, vd, vj));
5624
}
5625

5626
void LoongArch64Emitter::VFFINT_S_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5627
	Write32(EncodeVdVj(Opcode32::VFFINT_S_W, vd, vj));
5628
}
5629

5630
void LoongArch64Emitter::VFFINT_S_WU(LoongArch64Reg vd, LoongArch64Reg vj) {
5631
	Write32(EncodeVdVj(Opcode32::VFFINT_S_WU, vd, vj));
5632
}
5633

5634
void LoongArch64Emitter::VFFINT_D_L(LoongArch64Reg vd, LoongArch64Reg vj) {
5635
	Write32(EncodeVdVj(Opcode32::VFFINT_D_L, vd, vj));
5636
}
5637

5638
void LoongArch64Emitter::VFFINT_D_LU(LoongArch64Reg vd, LoongArch64Reg vj) {
5639
	Write32(EncodeVdVj(Opcode32::VFFINT_D_LU, vd, vj));
5640
}
5641

5642
void LoongArch64Emitter::VFFINTL_D_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5643
	Write32(EncodeVdVj(Opcode32::VFFINTL_D_W, vd, vj));
5644
}
5645

5646
void LoongArch64Emitter::VFFINTH_D_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5647
	Write32(EncodeVdVj(Opcode32::VFFINTH_D_W, vd, vj));
5648
}
5649

5650
void LoongArch64Emitter::VFTINT_W_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5651
	Write32(EncodeVdVj(Opcode32::VFTINT_W_S, vd, vj));
5652
}
5653

5654
void LoongArch64Emitter::VFTINT_L_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5655
	Write32(EncodeVdVj(Opcode32::VFTINT_L_D, vd, vj));
5656
}
5657

5658
void LoongArch64Emitter::VFTINTRM_W_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5659
	Write32(EncodeVdVj(Opcode32::VFTINTRM_W_S, vd, vj));
5660
}
5661

5662
void LoongArch64Emitter::VFTINTRM_L_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5663
	Write32(EncodeVdVj(Opcode32::VFTINTRM_L_D, vd, vj));
5664
}
5665

5666
void LoongArch64Emitter::VFTINTRP_W_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5667
	Write32(EncodeVdVj(Opcode32::VFTINTRP_W_S, vd, vj));
5668
}
5669

5670
void LoongArch64Emitter::VFTINTRP_L_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5671
	Write32(EncodeVdVj(Opcode32::VFTINTRP_L_D, vd, vj));
5672
}
5673

5674
void LoongArch64Emitter::VFTINTRZ_W_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5675
	Write32(EncodeVdVj(Opcode32::VFTINTRZ_W_S, vd, vj));
5676
}
5677

5678
void LoongArch64Emitter::VFTINTRZ_L_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5679
	Write32(EncodeVdVj(Opcode32::VFTINTRZ_L_D, vd, vj));
5680
}
5681

5682
void LoongArch64Emitter::VFTINTRNE_W_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5683
	Write32(EncodeVdVj(Opcode32::VFTINTRNE_W_S, vd, vj));
5684
}
5685

5686
void LoongArch64Emitter::VFTINTRNE_L_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5687
	Write32(EncodeVdVj(Opcode32::VFTINTRNE_L_D, vd, vj));
5688
}
5689

5690
void LoongArch64Emitter::VFTINT_WU_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5691
	Write32(EncodeVdVj(Opcode32::VFTINT_WU_S, vd, vj));
5692
}
5693

5694
void LoongArch64Emitter::VFTINT_LU_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5695
	Write32(EncodeVdVj(Opcode32::VFTINT_LU_D, vd, vj));
5696
}
5697

5698
void LoongArch64Emitter::VFTINTRZ_WU_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5699
	Write32(EncodeVdVj(Opcode32::VFTINTRZ_WU_S, vd, vj));
5700
}
5701

5702
void LoongArch64Emitter::VFTINTRZ_LU_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5703
	Write32(EncodeVdVj(Opcode32::VFTINTRZ_LU_D, vd, vj));
5704
}
5705

5706
void LoongArch64Emitter::VFTINTL_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5707
	Write32(EncodeVdVj(Opcode32::VFTINTL_L_S, vd, vj));
5708
}
5709

5710
void LoongArch64Emitter::VFTINTH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5711
	Write32(EncodeVdVj(Opcode32::VFTINTH_L_S, vd, vj));
5712
}
5713

5714
void LoongArch64Emitter::VFTINTRML_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5715
	Write32(EncodeVdVj(Opcode32::VFTINTRML_L_S, vd, vj));
5716
}
5717

5718
void LoongArch64Emitter::VFTINTRMH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5719
	Write32(EncodeVdVj(Opcode32::VFTINTRMH_L_S, vd, vj));
5720
}
5721

5722
void LoongArch64Emitter::VFTINTRPL_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5723
	Write32(EncodeVdVj(Opcode32::VFTINTRPL_L_S, vd, vj));
5724
}
5725

5726
void LoongArch64Emitter::VFTINTRPH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5727
	Write32(EncodeVdVj(Opcode32::VFTINTRPH_L_S, vd, vj));
5728
}
5729

5730
void LoongArch64Emitter::VFTINTRZL_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5731
	Write32(EncodeVdVj(Opcode32::VFTINTRZL_L_S, vd, vj));
5732
}
5733

5734
void LoongArch64Emitter::VFTINTRZH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5735
	Write32(EncodeVdVj(Opcode32::VFTINTRZH_L_S, vd, vj));
5736
}
5737

5738
void LoongArch64Emitter::VFTINTRNEL_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5739
	Write32(EncodeVdVj(Opcode32::VFTINTRNEL_L_S, vd, vj));
5740
}
5741

5742
void LoongArch64Emitter::VFTINTRNEH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) {
5743
	Write32(EncodeVdVj(Opcode32::VFTINTRNEH_L_S, vd, vj));
5744
}
5745

5746
void LoongArch64Emitter::VEXTH_H_B(LoongArch64Reg vd, LoongArch64Reg vj) {
5747
	Write32(EncodeVdVj(Opcode32::VEXTH_H_B, vd, vj));
5748
}
5749

5750
void LoongArch64Emitter::VEXTH_W_H(LoongArch64Reg vd, LoongArch64Reg vj) {
5751
	Write32(EncodeVdVj(Opcode32::VEXTH_W_H, vd, vj));
5752
}
5753

5754
void LoongArch64Emitter::VEXTH_D_W(LoongArch64Reg vd, LoongArch64Reg vj) {
5755
	Write32(EncodeVdVj(Opcode32::VEXTH_D_W, vd, vj));
5756
}
5757

5758
void LoongArch64Emitter::VEXTH_Q_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5759
	Write32(EncodeVdVj(Opcode32::VEXTH_Q_D, vd, vj));
5760
}
5761

5762
void LoongArch64Emitter::VEXTH_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj) {
5763
	Write32(EncodeVdVj(Opcode32::VEXTH_HU_BU, vd, vj));
5764
}
5765

5766
void LoongArch64Emitter::VEXTH_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj) {
5767
	Write32(EncodeVdVj(Opcode32::VEXTH_WU_HU, vd, vj));
5768
}
5769

5770
void LoongArch64Emitter::VEXTH_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj) {
5771
	Write32(EncodeVdVj(Opcode32::VEXTH_DU_WU, vd, vj));
5772
}
5773

5774
void LoongArch64Emitter::VEXTH_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj) {
5775
	Write32(EncodeVdVj(Opcode32::VEXTH_QU_DU, vd, vj));
5776
}
5777

5778
void LoongArch64Emitter::VREPLGR2VR_B(LoongArch64Reg vd, LoongArch64Reg rj) {
5779
	Write32(EncodeVdJ(Opcode32::VREPLGR2VR_B, vd, rj));
5780
}
5781

5782
void LoongArch64Emitter::VREPLGR2VR_H(LoongArch64Reg vd, LoongArch64Reg rj) {
5783
	Write32(EncodeVdJ(Opcode32::VREPLGR2VR_H, vd, rj));
5784
}
5785

5786
void LoongArch64Emitter::VREPLGR2VR_W(LoongArch64Reg vd, LoongArch64Reg rj) {
5787
	Write32(EncodeVdJ(Opcode32::VREPLGR2VR_W, vd, rj));
5788
}
5789

5790
void LoongArch64Emitter::VREPLGR2VR_D(LoongArch64Reg vd, LoongArch64Reg rj) {
5791
	Write32(EncodeVdJ(Opcode32::VREPLGR2VR_D, vd, rj));
5792
}
5793

5794
void LoongArch64Emitter::VROTRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5795
	Write32(EncodeVdVjUk3(Opcode32::VROTRI_B, vd, vj, ui3));
5796
}
5797

5798
void LoongArch64Emitter::VROTRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5799
	Write32(EncodeVdVjUk4(Opcode32::VROTRI_H, vd, vj, ui4));
5800
}
5801

5802
void LoongArch64Emitter::VROTRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5803
	Write32(EncodeVdVjUk5(Opcode32::VROTRI_W, vd, vj, ui5));
5804
}
5805

5806
void LoongArch64Emitter::VROTRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
5807
	Write32(EncodeVdVjUk6(Opcode32::VROTRI_D, vd, vj, ui6));
5808
}
5809

5810
void LoongArch64Emitter::VSRLRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5811
	Write32(EncodeVdVjUk3(Opcode32::VSRLRI_B, vd, vj, ui3));
5812
}
5813

5814
void LoongArch64Emitter::VSRLRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5815
	Write32(EncodeVdVjUk4(Opcode32::VSRLRI_H, vd, vj, ui4));
5816
}
5817

5818
void LoongArch64Emitter::VSRLRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5819
	Write32(EncodeVdVjUk5(Opcode32::VSRLRI_W, vd, vj, ui5));
5820
}
5821

5822
void LoongArch64Emitter::VSRLRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
5823
	Write32(EncodeVdVjUk6(Opcode32::VSRLRI_D, vd, vj, ui6));
5824
}
5825

5826
void LoongArch64Emitter::VSRARI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5827
	Write32(EncodeVdVjUk3(Opcode32::VSRARI_B, vd, vj, ui3));
5828
}
5829

5830
void LoongArch64Emitter::VSRARI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5831
	Write32(EncodeVdVjUk4(Opcode32::VSRARI_H, vd, vj, ui4));
5832
}
5833

5834
void LoongArch64Emitter::VSRARI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5835
	Write32(EncodeVdVjUk5(Opcode32::VSRARI_W, vd, vj, ui5));
5836
}
5837

5838
void LoongArch64Emitter::VSRARI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
5839
	Write32(EncodeVdVjUk6(Opcode32::VSRARI_D, vd, vj, ui6));
5840
}
5841

5842
void LoongArch64Emitter::VINSGR2VR_B(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui4) {
5843
	Write32(EncodeVdJUk4(Opcode32::VINSGR2VR_B, vd, rj, ui4));
5844
}
5845

5846
void LoongArch64Emitter::VINSGR2VR_H(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui3) {
5847
	Write32(EncodeVdJUk3(Opcode32::VINSGR2VR_H, vd, rj, ui3));
5848
}
5849

5850
void LoongArch64Emitter::VINSGR2VR_W(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui2) {
5851
	Write32(EncodeVdJUk2(Opcode32::VINSGR2VR_W, vd, rj, ui2));
5852
}
5853

5854
void LoongArch64Emitter::VINSGR2VR_D(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui1) {
5855
	Write32(EncodeVdJUk1(Opcode32::VINSGR2VR_D, vd, rj, ui1));
5856
}
5857

5858
void LoongArch64Emitter::VPICKVE2GR_B(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui4) {
5859
	Write32(EncodeDVjUk4(Opcode32::VPICKVE2GR_B, rd, vj, ui4));
5860
}
5861

5862
void LoongArch64Emitter::VPICKVE2GR_H(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui3) {
5863
	Write32(EncodeDVjUk3(Opcode32::VPICKVE2GR_H, rd, vj, ui3));
5864
}
5865

5866
void LoongArch64Emitter::VPICKVE2GR_W(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui2) {
5867
	Write32(EncodeDVjUk2(Opcode32::VPICKVE2GR_W, rd, vj, ui2));
5868
}
5869

5870
void LoongArch64Emitter::VPICKVE2GR_D(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui1) {
5871
	Write32(EncodeDVjUk1(Opcode32::VPICKVE2GR_D, rd, vj, ui1));
5872
}
5873

5874
void LoongArch64Emitter::VPICKVE2GR_BU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui4) {
5875
	Write32(EncodeDVjUk4(Opcode32::VPICKVE2GR_BU, rd, vj, ui4));
5876
}
5877

5878
void LoongArch64Emitter::VPICKVE2GR_HU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui3) {
5879
	Write32(EncodeDVjUk3(Opcode32::VPICKVE2GR_HU, rd, vj, ui3));
5880
}
5881

5882
void LoongArch64Emitter::VPICKVE2GR_WU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui2) {
5883
	Write32(EncodeDVjUk2(Opcode32::VPICKVE2GR_WU, rd, vj, ui2));
5884
}
5885

5886
void LoongArch64Emitter::VPICKVE2GR_DU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui1) {
5887
	Write32(EncodeDVjUk1(Opcode32::VPICKVE2GR_DU, rd, vj, ui1));
5888
}
5889

5890
void LoongArch64Emitter::VREPLVEI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5891
	Write32(EncodeVdVjUk4(Opcode32::VREPLVEI_B, vd, vj, ui4));
5892
}
5893

5894
void LoongArch64Emitter::VREPLVEI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5895
	Write32(EncodeVdVjUk3(Opcode32::VREPLVEI_H, vd, vj, ui3));
5896
}
5897

5898
void LoongArch64Emitter::VREPLVEI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui2) {
5899
	Write32(EncodeVdVjUk2(Opcode32::VREPLVEI_W, vd, vj, ui2));
5900
}
5901

5902
void LoongArch64Emitter::VREPLVEI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui1) {
5903
	Write32(EncodeVdVjUk1(Opcode32::VREPLVEI_D, vd, vj, ui1));
5904
}
5905

5906
void LoongArch64Emitter::VSLLWIL_H_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5907
	Write32(EncodeVdVjUk3(Opcode32::VSLLWIL_H_B, vd, vj, ui3));
5908
}
5909

5910
void LoongArch64Emitter::VSLLWIL_W_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5911
	Write32(EncodeVdVjUk4(Opcode32::VSLLWIL_W_H, vd, vj, ui4));
5912
}
5913

5914
void LoongArch64Emitter::VSLLWIL_D_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5915
	Write32(EncodeVdVjUk5(Opcode32::VSLLWIL_D_W, vd, vj, ui5));
5916
}
5917

5918
void LoongArch64Emitter::VEXTL_Q_D(LoongArch64Reg vd, LoongArch64Reg vj) {
5919
	Write32(EncodeVdVj(Opcode32::VEXTL_Q_D, vd, vj));
5920
}
5921

5922
void LoongArch64Emitter::VSLLWIL_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5923
	Write32(EncodeVdVjUk3(Opcode32::VSLLWIL_HU_BU, vd, vj, ui3));
5924
}
5925

5926
void LoongArch64Emitter::VSLLWIL_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5927
	Write32(EncodeVdVjUk4(Opcode32::VSLLWIL_WU_HU, vd, vj, ui4));
5928
}
5929

5930
void LoongArch64Emitter::VSLLWIL_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5931
	Write32(EncodeVdVjUk5(Opcode32::VSLLWIL_DU_WU, vd, vj, ui5));
5932
}
5933

5934
void LoongArch64Emitter::VEXTL_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj) {
5935
	Write32(EncodeVdVj(Opcode32::VEXTL_QU_DU, vd, vj));
5936
}
5937

5938
void LoongArch64Emitter::VBITCLRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5939
	Write32(EncodeVdVjUk3(Opcode32::VBITCLRI_B, vd, vj, ui3));
5940
}
5941

5942
void LoongArch64Emitter::VBITCLRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5943
	Write32(EncodeVdVjUk4(Opcode32::VBITCLRI_H, vd, vj, ui4));
5944
}
5945

5946
void LoongArch64Emitter::VBITCLRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5947
	Write32(EncodeVdVjUk5(Opcode32::VBITCLRI_W, vd, vj, ui5));
5948
}
5949

5950
void LoongArch64Emitter::VBITCLRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
5951
	Write32(EncodeVdVjUk6(Opcode32::VBITCLRI_D, vd, vj, ui6));
5952
}
5953

5954
void LoongArch64Emitter::VBITSETI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5955
	Write32(EncodeVdVjUk3(Opcode32::VBITSETI_B, vd, vj, ui3));
5956
}
5957

5958
void LoongArch64Emitter::VBITSETI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5959
	Write32(EncodeVdVjUk4(Opcode32::VBITSETI_H, vd, vj, ui4));
5960
}
5961

5962
void LoongArch64Emitter::VBITSETI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5963
	Write32(EncodeVdVjUk5(Opcode32::VBITSETI_W, vd, vj, ui5));
5964
}
5965

5966
void LoongArch64Emitter::VBITSETI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
5967
	Write32(EncodeVdVjUk6(Opcode32::VBITSETI_D, vd, vj, ui6));
5968
}
5969

5970
void LoongArch64Emitter::VBITREVI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5971
	Write32(EncodeVdVjUk3(Opcode32::VBITREVI_B, vd, vj, ui3));
5972
}
5973

5974
void LoongArch64Emitter::VBITREVI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5975
	Write32(EncodeVdVjUk4(Opcode32::VBITREVI_H, vd, vj, ui4));
5976
}
5977

5978
void LoongArch64Emitter::VBITREVI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5979
	Write32(EncodeVdVjUk5(Opcode32::VBITREVI_W, vd, vj, ui5));
5980
}
5981

5982
void LoongArch64Emitter::VBITREVI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
5983
	Write32(EncodeVdVjUk6(Opcode32::VBITREVI_D, vd, vj, ui6));
5984
}
5985

5986
void LoongArch64Emitter::VSAT_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
5987
	Write32(EncodeVdVjUk3(Opcode32::VSAT_B, vd, vj, ui3));
5988
}
5989

5990
void LoongArch64Emitter::VSAT_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
5991
	Write32(EncodeVdVjUk4(Opcode32::VSAT_H, vd, vj, ui4));
5992
}
5993

5994
void LoongArch64Emitter::VSAT_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
5995
	Write32(EncodeVdVjUk5(Opcode32::VSAT_W, vd, vj, ui5));
5996
}
5997

5998
void LoongArch64Emitter::VSAT_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
5999
	Write32(EncodeVdVjUk6(Opcode32::VSAT_D, vd, vj, ui6));
6000
}
6001

6002
void LoongArch64Emitter::VSAT_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
6003
    Write32(EncodeVdVjUk3(Opcode32::VSAT_BU, vd, vj, ui3));
6004
}
6005

6006
void LoongArch64Emitter::VSAT_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6007
    Write32(EncodeVdVjUk4(Opcode32::VSAT_HU, vd, vj, ui4));
6008
}
6009

6010
void LoongArch64Emitter::VSAT_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6011
    Write32(EncodeVdVjUk5(Opcode32::VSAT_WU, vd, vj, ui5));
6012
}
6013

6014
void LoongArch64Emitter::VSAT_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6015
    Write32(EncodeVdVjUk6(Opcode32::VSAT_DU, vd, vj, ui6));
6016
}
6017

6018
void LoongArch64Emitter::VSLLI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
6019
	Write32(EncodeVdVjUk3(Opcode32::VSLLI_B, vd, vj, ui3));
6020
}
6021

6022
void LoongArch64Emitter::VSLLI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6023
	Write32(EncodeVdVjUk4(Opcode32::VSLLI_H, vd, vj, ui4));
6024
}
6025

6026
void LoongArch64Emitter::VSLLI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6027
	Write32(EncodeVdVjUk5(Opcode32::VSLLI_W, vd, vj, ui5));
6028
}
6029

6030
void LoongArch64Emitter::VSLLI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6031
	Write32(EncodeVdVjUk6(Opcode32::VSLLI_D, vd, vj, ui6));
6032
}
6033

6034
void LoongArch64Emitter::VSRLI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
6035
	Write32(EncodeVdVjUk3(Opcode32::VSRLI_B, vd, vj, ui3));
6036
}
6037

6038
void LoongArch64Emitter::VSRLI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6039
	Write32(EncodeVdVjUk4(Opcode32::VSRLI_H, vd, vj, ui4));
6040
}
6041

6042
void LoongArch64Emitter::VSRLI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6043
	Write32(EncodeVdVjUk5(Opcode32::VSRLI_W, vd, vj, ui5));
6044
}
6045

6046
void LoongArch64Emitter::VSRLI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6047
	Write32(EncodeVdVjUk6(Opcode32::VSRLI_D, vd, vj, ui6));
6048
}
6049

6050
void LoongArch64Emitter::VSRAI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) {
6051
	Write32(EncodeVdVjUk3(Opcode32::VSRAI_B, vd, vj, ui3));
6052
}
6053

6054
void LoongArch64Emitter::VSRAI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6055
	Write32(EncodeVdVjUk4(Opcode32::VSRAI_H, vd, vj, ui4));
6056
}
6057

6058
void LoongArch64Emitter::VSRAI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6059
	Write32(EncodeVdVjUk5(Opcode32::VSRAI_W, vd, vj, ui5));
6060
}
6061

6062
void LoongArch64Emitter::VSRAI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6063
	Write32(EncodeVdVjUk6(Opcode32::VSRAI_D, vd, vj, ui6));
6064
}
6065

6066
void LoongArch64Emitter::VSRLNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6067
	Write32(EncodeVdVjUk4(Opcode32::VSRLNI_B_H, vd, vj, ui4));
6068
}
6069

6070
void LoongArch64Emitter::VSRLNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6071
	Write32(EncodeVdVjUk5(Opcode32::VSRLNI_H_W, vd, vj, ui5));
6072
}
6073

6074
void LoongArch64Emitter::VSRLNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6075
	Write32(EncodeVdVjUk6(Opcode32::VSRLNI_W_D, vd, vj, ui6));
6076
}
6077

6078
void LoongArch64Emitter::VSRLNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6079
	Write32(EncodeVdVjUk7(Opcode32::VSRLNI_D_Q, vd, vj, ui7));
6080
}
6081

6082
void LoongArch64Emitter::VSRLRNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6083
	Write32(EncodeVdVjUk4(Opcode32::VSRLRNI_B_H, vd, vj, ui4));
6084
}
6085

6086
void LoongArch64Emitter::VSRLRNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6087
	Write32(EncodeVdVjUk5(Opcode32::VSRLRNI_H_W, vd, vj, ui5));
6088
}
6089

6090
void LoongArch64Emitter::VSRLRNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6091
	Write32(EncodeVdVjUk6(Opcode32::VSRLRNI_W_D, vd, vj, ui6));
6092
}
6093

6094
void LoongArch64Emitter::VSRLRNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6095
	Write32(EncodeVdVjUk7(Opcode32::VSRLRNI_D_Q, vd, vj, ui7));
6096
}
6097

6098
void LoongArch64Emitter::VSSRLNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6099
	Write32(EncodeVdVjUk4(Opcode32::VSSRLNI_B_H, vd, vj, ui4));
6100
}
6101

6102
void LoongArch64Emitter::VSSRLNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6103
	Write32(EncodeVdVjUk5(Opcode32::VSSRLNI_H_W, vd, vj, ui5));
6104
}
6105

6106
void LoongArch64Emitter::VSSRLNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6107
	Write32(EncodeVdVjUk6(Opcode32::VSSRLNI_W_D, vd, vj, ui6));
6108
}
6109

6110
void LoongArch64Emitter::VSSRLNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6111
	Write32(EncodeVdVjUk7(Opcode32::VSSRLNI_D_Q, vd, vj, ui7));
6112
}
6113

6114
void LoongArch64Emitter::VSSRLNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6115
	Write32(EncodeVdVjUk4(Opcode32::VSSRLNI_BU_H, vd, vj, ui4));
6116
}
6117

6118
void LoongArch64Emitter::VSSRLNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6119
	Write32(EncodeVdVjUk5(Opcode32::VSSRLNI_HU_W, vd, vj, ui5));
6120
}
6121

6122
void LoongArch64Emitter::VSSRLNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6123
	Write32(EncodeVdVjUk6(Opcode32::VSSRLNI_WU_D, vd, vj, ui6));
6124
}
6125

6126
void LoongArch64Emitter::VSSRLNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6127
	Write32(EncodeVdVjUk7(Opcode32::VSSRLNI_DU_Q, vd, vj, ui7));
6128
}
6129

6130
void LoongArch64Emitter::VSSRLRNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6131
	Write32(EncodeVdVjUk4(Opcode32::VSSRLRNI_B_H, vd, vj, ui4));
6132
}
6133

6134
void LoongArch64Emitter::VSSRLRNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6135
	Write32(EncodeVdVjUk5(Opcode32::VSSRLRNI_H_W, vd, vj, ui5));
6136
}
6137

6138
void LoongArch64Emitter::VSSRLRNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6139
	Write32(EncodeVdVjUk6(Opcode32::VSSRLRNI_W_D, vd, vj, ui6));
6140
}
6141

6142
void LoongArch64Emitter::VSSRLRNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6143
	Write32(EncodeVdVjUk7(Opcode32::VSSRLRNI_D_Q, vd, vj, ui7));
6144
}
6145

6146
void LoongArch64Emitter::VSSRLRNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6147
	Write32(EncodeVdVjUk4(Opcode32::VSSRLRNI_BU_H, vd, vj, ui4));
6148
}
6149

6150
void LoongArch64Emitter::VSSRLRNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6151
	Write32(EncodeVdVjUk5(Opcode32::VSSRLRNI_HU_W, vd, vj, ui5));
6152
}
6153

6154
void LoongArch64Emitter::VSSRLRNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6155
	Write32(EncodeVdVjUk6(Opcode32::VSSRLRNI_WU_D, vd, vj, ui6));
6156
}
6157

6158
void LoongArch64Emitter::VSSRLRNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6159
	Write32(EncodeVdVjUk7(Opcode32::VSSRLRNI_DU_Q, vd, vj, ui7));
6160
}
6161

6162
void LoongArch64Emitter::VSRANI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6163
	Write32(EncodeVdVjUk4(Opcode32::VSRANI_B_H, vd, vj, ui4));
6164
}
6165

6166
void LoongArch64Emitter::VSRANI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6167
	Write32(EncodeVdVjUk5(Opcode32::VSRANI_H_W, vd, vj, ui5));
6168
}
6169

6170
void LoongArch64Emitter::VSRANI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6171
	Write32(EncodeVdVjUk6(Opcode32::VSRANI_W_D, vd, vj, ui6));
6172
}
6173

6174
void LoongArch64Emitter::VSRANI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6175
	Write32(EncodeVdVjUk7(Opcode32::VSRANI_D_Q, vd, vj, ui7));
6176
}
6177

6178
void LoongArch64Emitter::VSRARNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6179
	Write32(EncodeVdVjUk4(Opcode32::VSRARNI_B_H, vd, vj, ui4));
6180
}
6181

6182
void LoongArch64Emitter::VSRARNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6183
	Write32(EncodeVdVjUk5(Opcode32::VSRARNI_H_W, vd, vj, ui5));
6184
}
6185

6186
void LoongArch64Emitter::VSRARNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6187
	Write32(EncodeVdVjUk6(Opcode32::VSRARNI_W_D, vd, vj, ui6));
6188
}
6189

6190
void LoongArch64Emitter::VSRARNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6191
	Write32(EncodeVdVjUk7(Opcode32::VSRARNI_D_Q, vd, vj, ui7));
6192
}
6193

6194
void LoongArch64Emitter::VSSRANI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6195
	Write32(EncodeVdVjUk4(Opcode32::VSSRANI_B_H, vd, vj, ui4));
6196
}
6197

6198
void LoongArch64Emitter::VSSRANI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6199
	Write32(EncodeVdVjUk5(Opcode32::VSSRANI_H_W, vd, vj, ui5));
6200
}
6201

6202
void LoongArch64Emitter::VSSRANI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6203
	Write32(EncodeVdVjUk6(Opcode32::VSSRANI_W_D, vd, vj, ui6));
6204
}
6205

6206
void LoongArch64Emitter::VSSRANI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6207
	Write32(EncodeVdVjUk7(Opcode32::VSSRANI_D_Q, vd, vj, ui7));
6208
}
6209

6210
void LoongArch64Emitter::VSSRANI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6211
	Write32(EncodeVdVjUk4(Opcode32::VSSRANI_BU_H, vd, vj, ui4));
6212
}
6213

6214
void LoongArch64Emitter::VSSRANI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6215
	Write32(EncodeVdVjUk5(Opcode32::VSSRANI_HU_W, vd, vj, ui5));
6216
}
6217

6218
void LoongArch64Emitter::VSSRANI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6219
	Write32(EncodeVdVjUk6(Opcode32::VSSRANI_WU_D, vd, vj, ui6));
6220
}
6221

6222
void LoongArch64Emitter::VSSRANI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6223
	Write32(EncodeVdVjUk7(Opcode32::VSSRANI_DU_Q, vd, vj, ui7));
6224
}
6225

6226
void LoongArch64Emitter::VSSRARNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6227
	Write32(EncodeVdVjUk4(Opcode32::VSSRARNI_B_H, vd, vj, ui4));
6228
}
6229

6230
void LoongArch64Emitter::VSSRARNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6231
	Write32(EncodeVdVjUk5(Opcode32::VSSRARNI_H_W, vd, vj, ui5));
6232
}
6233

6234
void LoongArch64Emitter::VSSRARNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6235
	Write32(EncodeVdVjUk6(Opcode32::VSSRARNI_W_D, vd, vj, ui6));
6236
}
6237

6238
void LoongArch64Emitter::VSSRARNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6239
	Write32(EncodeVdVjUk7(Opcode32::VSSRARNI_D_Q, vd, vj, ui7));
6240
}
6241

6242
void LoongArch64Emitter::VSSRARNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) {
6243
	Write32(EncodeVdVjUk4(Opcode32::VSSRARNI_BU_H, vd, vj, ui4));
6244
}
6245

6246
void LoongArch64Emitter::VSSRARNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) {
6247
	Write32(EncodeVdVjUk5(Opcode32::VSSRARNI_HU_W, vd, vj, ui5));
6248
}
6249

6250
void LoongArch64Emitter::VSSRARNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) {
6251
	Write32(EncodeVdVjUk6(Opcode32::VSSRARNI_WU_D, vd, vj, ui6));
6252
}
6253

6254
void LoongArch64Emitter::VSSRARNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) {
6255
	Write32(EncodeVdVjUk7(Opcode32::VSSRARNI_DU_Q, vd, vj, ui7));
6256
}
6257

6258
void LoongArch64Emitter::VEXTRINS_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6259
	Write32(EncodeVdVjUk8(Opcode32::VEXTRINS_D, vd, vj, ui8));
6260
}
6261

6262
void LoongArch64Emitter::VEXTRINS_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6263
	Write32(EncodeVdVjUk8(Opcode32::VEXTRINS_W, vd, vj, ui8));
6264
}
6265

6266
void LoongArch64Emitter::VEXTRINS_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6267
	Write32(EncodeVdVjUk8(Opcode32::VEXTRINS_H, vd, vj, ui8));
6268
}
6269

6270
void LoongArch64Emitter::VEXTRINS_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6271
	Write32(EncodeVdVjUk8(Opcode32::VEXTRINS_B, vd, vj, ui8));
6272
}
6273

6274
void LoongArch64Emitter::VSHUF4I_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6275
	Write32(EncodeVdVjUk8(Opcode32::VSHUF4I_B, vd, vj, ui8));
6276
}
6277

6278
void LoongArch64Emitter::VSHUF4I_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6279
	Write32(EncodeVdVjUk8(Opcode32::VSHUF4I_H, vd, vj, ui8));
6280
}
6281

6282
void LoongArch64Emitter::VSHUF4I_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6283
	Write32(EncodeVdVjUk8(Opcode32::VSHUF4I_W, vd, vj, ui8));
6284
}
6285

6286
void LoongArch64Emitter::VSHUF4I_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6287
	Write32(EncodeVdVjUk8(Opcode32::VSHUF4I_D, vd, vj, ui8));
6288
}
6289

6290
void LoongArch64Emitter::VBITSELI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6291
	Write32(EncodeVdVjUk8(Opcode32::VBITSELI_B, vd, vj, ui8));
6292
}
6293

6294
void LoongArch64Emitter::VANDI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6295
	Write32(EncodeVdVjUk8(Opcode32::VANDI_B, vd, vj, ui8));
6296
}
6297

6298
void LoongArch64Emitter::VORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6299
	Write32(EncodeVdVjUk8(Opcode32::VORI_B, vd, vj, ui8));
6300
}
6301

6302
void LoongArch64Emitter::VXORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6303
	Write32(EncodeVdVjUk8(Opcode32::VXORI_B, vd, vj, ui8));
6304
}
6305

6306
void LoongArch64Emitter::VNORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6307
	Write32(EncodeVdVjUk8(Opcode32::VNORI_B, vd, vj, ui8));
6308
}
6309

6310
void LoongArch64Emitter::VLDI(LoongArch64Reg vd, s16 i13) {
6311
	Write32(EncodeVdSj13(Opcode32::VLDI, vd, i13));
6312
}
6313

6314
void LoongArch64Emitter::VPERMI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) {
6315
	Write32(EncodeVdVjUk8(Opcode32::VPERMI_W, vd, vj, ui8));
6316
}
6317

6318
void LoongArch64CodeBlock::PoisonMemory(int offset) {
6319
    // So we can adjust region to writable space.  Might be zero.
6320
	ptrdiff_t writable = writable_ - code_;
6321

6322
	u32 *ptr = (u32 *)(region + offset + writable);
6323
	u32 *maxptr = (u32 *)(region + region_size - offset + writable);
6324
    // If our memory isn't a multiple of u32 then this won't write the last remaining bytes with anything
6325
	// Less than optimal, but there would be nothing we could do but throw a runtime warning anyway.
6326
	// LoongArch64: 0x002a0000 = BREAK 0
6327
	while (ptr < maxptr)
6328
		*ptr++ = 0x002a0000;
6329
}
6330

6331
};
6332

6333
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