CoCalc -- bcmdevs.h

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GitHub Repository: orangepi-xunlong/orangepi-build
Path: blob/next/external/cache/sources/wl/include/bcmdevs.h
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/*
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 * Broadcom device-specific manifest constants.
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 *
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 * $Copyright Open Broadcom Corporation$
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 *
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 * $Id: bcmdevs.h 401759 2013-05-13 16:08:08Z sudhirbs $
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 */
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#ifndef	_BCMDEVS_H
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#define	_BCMDEVS_H
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/* PCI vendor IDs */
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#define	VENDOR_EPIGRAM		0xfeda
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#define	VENDOR_BROADCOM		0x14e4
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#define	VENDOR_3COM		0x10b7
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#define	VENDOR_NETGEAR		0x1385
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#define	VENDOR_DIAMOND		0x1092
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#define	VENDOR_INTEL		0x8086
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#define	VENDOR_DELL		0x1028
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#define	VENDOR_HP		0x103c
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#define	VENDOR_HP_COMPAQ	0x0e11
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#define	VENDOR_APPLE		0x106b
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#define VENDOR_SI_IMAGE		0x1095		/* Silicon Image, used by Arasan SDIO Host */
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#define VENDOR_BUFFALO		0x1154		/* Buffalo vendor id */
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#define VENDOR_TI		0x104c		/* Texas Instruments */
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#define VENDOR_RICOH		0x1180		/* Ricoh */
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#define VENDOR_JMICRON		0x197b
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#ifdef BCMINTERNAL
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#define VENDOR_JINVANI		0x1947		/* Jinvani Systech, Inc. */
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#endif
32

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/* PCMCIA vendor IDs */
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#define	VENDOR_BROADCOM_PCMCIA	0x02d0
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/* SDIO vendor IDs */
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#define	VENDOR_BROADCOM_SDIO	0x00BF
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/* DONGLE VID/PIDs */
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#define BCM_DNGL_VID		0x0a5c
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#define BCM_DNGL_BL_PID_4328	0xbd12
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#define BCM_DNGL_BL_PID_4322	0xbd13
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#define BCM_DNGL_BL_PID_4319    0xbd16
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#define BCM_DNGL_BL_PID_43236   0xbd17
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#define BCM_DNGL_BL_PID_4332	0xbd18
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#define BCM_DNGL_BL_PID_4330	0xbd19
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#define BCM_DNGL_BL_PID_4334	0xbd1a
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#define BCM_DNGL_BL_PID_43239   0xbd1b
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#define BCM_DNGL_BL_PID_4324	0xbd1c
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#define BCM_DNGL_BL_PID_4360	0xbd1d
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#define BCM_DNGL_BL_PID_43143	0xbd1e
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#define BCM_DNGL_BL_PID_43242	0xbd1f
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#define BCM_DNGL_BL_PID_43342	0xbd21
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#define BCM_DNGL_BL_PID_4335	0xbd20
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#define BCM_DNGL_BL_PID_43341	0xbd22
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#define BCM_DNGL_BL_PID_4350    0xbd23
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#ifdef UNRELEASEDCHIP
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#define BCM_DNGL_BL_PID_4345    0xbd24
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#endif /* UNRELEASEDCHIP */
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#define BCM_DNGL_BDC_PID	0x0bdc
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#define BCM_DNGL_JTAG_PID	0x4a44
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/* HW USB BLOCK [CPULESS USB] PIDs */
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#define BCM_HWUSB_PID_43239     43239
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/* PCI Device IDs */
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#define	BCM4210_DEVICE_ID	0x1072		/* never used */
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#define	BCM4230_DEVICE_ID	0x1086		/* never used */
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#define	BCM4401_ENET_ID		0x170c		/* 4401b0 production enet cards */
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#define	BCM3352_DEVICE_ID	0x3352		/* bcm3352 device id */
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#define	BCM3360_DEVICE_ID	0x3360		/* bcm3360 device id */
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#define	BCM4211_DEVICE_ID	0x4211
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#define	BCM4231_DEVICE_ID	0x4231
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#define	BCM4303_D11B_ID		0x4303		/* 4303 802.11b */
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#define	BCM4311_D11G_ID		0x4311		/* 4311 802.11b/g id */
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#define	BCM4311_D11DUAL_ID	0x4312		/* 4311 802.11a/b/g id */
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#define	BCM4311_D11A_ID		0x4313		/* 4311 802.11a id */
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#define	BCM4328_D11DUAL_ID	0x4314		/* 4328/4312 802.11a/g id */
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#define	BCM4328_D11G_ID		0x4315		/* 4328/4312 802.11g id */
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#define	BCM4328_D11A_ID		0x4316		/* 4328/4312 802.11a id */
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#define	BCM4318_D11G_ID		0x4318		/* 4318 802.11b/g id */
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#define	BCM4318_D11DUAL_ID	0x4319		/* 4318 802.11a/b/g id */
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#define	BCM4318_D11A_ID		0x431a		/* 4318 802.11a id */
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#define	BCM4325_D11DUAL_ID	0x431b		/* 4325 802.11a/g id */
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#define	BCM4325_D11G_ID		0x431c		/* 4325 802.11g id */
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#define	BCM4325_D11A_ID		0x431d		/* 4325 802.11a id */
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#define	BCM4306_D11G_ID		0x4320		/* 4306 802.11g */
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#define	BCM4306_D11A_ID		0x4321		/* 4306 802.11a */
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#define	BCM4306_UART_ID		0x4322		/* 4306 uart */
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#define	BCM4306_V90_ID		0x4323		/* 4306 v90 codec */
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#define	BCM4306_D11DUAL_ID	0x4324		/* 4306 dual A+B */
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#define	BCM4306_D11G_ID2	0x4325		/* BCM4306_D11G_ID; INF w/loose binding war */
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#define	BCM4321_D11N_ID		0x4328		/* 4321 802.11n dualband id */
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#define	BCM4321_D11N2G_ID	0x4329		/* 4321 802.11n 2.4Ghz band id */
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#define	BCM4321_D11N5G_ID	0x432a		/* 4321 802.11n 5Ghz band id */
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#define BCM4322_D11N_ID		0x432b		/* 4322 802.11n dualband device */
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#define BCM4322_D11N2G_ID	0x432c		/* 4322 802.11n 2.4GHz device */
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#define BCM4322_D11N5G_ID	0x432d		/* 4322 802.11n 5GHz device */
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#define BCM4329_D11N_ID		0x432e		/* 4329 802.11n dualband device */
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#define BCM4329_D11N2G_ID	0x432f		/* 4329 802.11n 2.4G device */
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#define BCM4329_D11N5G_ID	0x4330		/* 4329 802.11n 5G device */
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#define	BCM4315_D11DUAL_ID	0x4334		/* 4315 802.11a/g id */
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#define	BCM4315_D11G_ID		0x4335		/* 4315 802.11g id */
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#define	BCM4315_D11A_ID		0x4336		/* 4315 802.11a id */
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#define BCM4319_D11N_ID		0x4337		/* 4319 802.11n dualband device */
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#define BCM4319_D11N2G_ID	0x4338		/* 4319 802.11n 2.4G device */
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#define BCM4319_D11N5G_ID	0x4339		/* 4319 802.11n 5G device */
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#define BCM43231_D11N2G_ID	0x4340		/* 43231 802.11n 2.4GHz device */
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#define BCM43221_D11N2G_ID	0x4341		/* 43221 802.11n 2.4GHz device */
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#define BCM43222_D11N_ID	0x4350		/* 43222 802.11n dualband device */
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#define BCM43222_D11N2G_ID	0x4351		/* 43222 802.11n 2.4GHz device */
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#define BCM43222_D11N5G_ID	0x4352		/* 43222 802.11n 5GHz device */
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#define BCM43224_D11N_ID	0x4353		/* 43224 802.11n dualband device */
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#define BCM43224_D11N_ID_VEN1	0x0576		/* Vendor specific 43224 802.11n db device */
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#define BCM43226_D11N_ID	0x4354		/* 43226 802.11n dualband device */
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#define BCM43236_D11N_ID	0x4346		/* 43236 802.11n dualband device */
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#define BCM43236_D11N2G_ID	0x4347		/* 43236 802.11n 2.4GHz device */
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#define BCM43236_D11N5G_ID	0x4348		/* 43236 802.11n 5GHz device */
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#define BCM43225_D11N2G_ID	0x4357		/* 43225 802.11n 2.4GHz device */
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#define BCM43421_D11N_ID	0xA99D		/* 43421 802.11n dualband device */
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#define BCM4313_D11N2G_ID	0x4727		/* 4313 802.11n 2.4G device */
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#define BCM4330_D11N_ID         0x4360          /* 4330 802.11n dualband device */
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#define BCM4330_D11N2G_ID       0x4361          /* 4330 802.11n 2.4G device */
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#define BCM4330_D11N5G_ID       0x4362          /* 4330 802.11n 5G device */
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#define BCM4336_D11N_ID		0x4343		/* 4336 802.11n 2.4GHz device */
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#define BCM6362_D11N_ID		0x435f		/* 6362 802.11n dualband device */
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#define BCM6362_D11N2G_ID	0x433f		/* 6362 802.11n 2.4Ghz band id */
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#define BCM6362_D11N5G_ID	0x434f		/* 6362 802.11n 5Ghz band id */
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#define BCM4331_D11N_ID		0x4331		/* 4331 802.11n dualband id */
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#define BCM4331_D11N2G_ID	0x4332		/* 4331 802.11n 2.4Ghz band id */
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#define BCM4331_D11N5G_ID	0x4333		/* 4331 802.11n 5Ghz band id */
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#define BCM43237_D11N_ID	0x4355		/* 43237 802.11n dualband device */
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#define BCM43237_D11N5G_ID	0x4356		/* 43237 802.11n 5GHz device */
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#define BCM43227_D11N2G_ID	0x4358		/* 43228 802.11n 2.4GHz device */
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#define BCM43228_D11N_ID	0x4359		/* 43228 802.11n DualBand device */
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#define BCM43228_D11N5G_ID	0x435a		/* 43228 802.11n 5GHz device */
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#define BCM43362_D11N_ID	0x4363		/* 43362 802.11n 2.4GHz device */
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#define BCM43239_D11N_ID	0x4370		/* 43239 802.11n dualband device */
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#define BCM4324_D11N_ID		0x4374		/* 4324 802.11n dualband device */
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#define BCM43217_D11N2G_ID	0x43a9		/* 43217 802.11n 2.4GHz device */
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#define BCM43131_D11N2G_ID	0x43aa		/* 43131 802.11n 2.4GHz device */
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#define BCM4314_D11N2G_ID	0x4364		/* 4314 802.11n 2.4G device */
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#define BCM43142_D11N2G_ID	0x4365		/* 43142 802.11n 2.4G device */
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#define BCM43143_D11N2G_ID	0x4366		/* 43143 802.11n 2.4G device */
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#define BCM4334_D11N_ID		0x4380		/* 4334 802.11n dualband device */
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#define BCM4334_D11N2G_ID	0x4381		/* 4334 802.11n 2.4G device */
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#define BCM4334_D11N5G_ID	0x4382		/* 4334 802.11n 5G device */
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#define BCM43342_D11N_ID	0x4383		/* 43342 802.11n dualband device */
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#define BCM43342_D11N2G_ID	0x4384		/* 43342 802.11n 2.4G device */
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#define BCM43342_D11N5G_ID	0x4385		/* 43342 802.11n 5G device */
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#define BCM43341_D11N_ID	0x4386		/* 43341 802.11n dualband device */
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#define BCM43341_D11N2G_ID	0x4387		/* 43341 802.11n 2.4G device */
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#define BCM43341_D11N5G_ID	0x4388		/* 43341 802.11n 5G device */
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#define BCM4360_D11AC_ID	0x43a0
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#define BCM4360_D11AC2G_ID	0x43a1
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#define BCM4360_D11AC5G_ID	0x43a2
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#ifdef UNRELEASEDCHIP
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#define BCM4345_D11AC_ID	0x43ab		/* 4345 802.11ac dualband device */
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#define BCM4345_D11AC2G_ID	0x43ac		/* 4345 802.11ac 2.4G device */
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#define BCM4345_D11AC5G_ID	0x43ad		/* 4345 802.11ac 5G device */
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#endif /* UNRELEASEDCHIP */
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#define BCM4335_D11AC_ID	0x43ae
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#define BCM4335_D11AC2G_ID	0x43af
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#define BCM4335_D11AC5G_ID	0x43b0
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#define BCM4352_D11AC_ID	0x43b1		/* 4352 802.11ac dualband device */
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#define BCM4352_D11AC2G_ID	0x43b2		/* 4352 802.11ac 2.4G device */
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#define BCM4352_D11AC5G_ID	0x43b3		/* 4352 802.11ac 5G device */
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#ifdef UNRELEASEDCHIP
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#define BCM43602_D11AC_ID	0x43ba		/* 43602 802.11ac dualband device */
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#define BCM43602_D11AC2G_ID	0x43bb		/* 43602 802.11ac 2.4G device */
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#define BCM43602_D11AC5G_ID	0x43bc		/* 43602 802.11ac 5G device */
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#endif /* UNRELEASEDCHIP */
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/* PCI Subsystem ID */
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#define BCM943228HMB_SSID_VEN1	0x0607
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#define BCM94313HMGBL_SSID_VEN1	0x0608
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#define BCM94313HMG_SSID_VEN1	0x0609
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#define BCM943142HM_SSID_VEN1	0x0611
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#define BCM43143_D11N2G_ID	0x4366		/* 43143 802.11n 2.4G device */
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#define BCM43242_D11N_ID	0x4367		/* 43242 802.11n dualband device */
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#define BCM43242_D11N2G_ID	0x4368		/* 43242 802.11n 2.4G device */
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#define BCM43242_D11N5G_ID	0x4369		/* 43242 802.11n 5G device */
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187
#define BCM4350_D11AC_ID	0x43a3
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#define BCM4350_D11AC2G_ID	0x43a4
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#define BCM4350_D11AC5G_ID	0x43a5
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#define BCM43556_D11AC_ID	0x43b7
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#define BCM43556_D11AC2G_ID	0x43b8
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#define BCM43556_D11AC5G_ID	0x43b9
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#ifdef UNRELEASEDCHIP
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/* Unreleased PCI Device IDs */
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#define BCM43229_D11N_ID	0x435d		/* 43229 802.11n dualband device */
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#define BCM43229_D11N2G_ID	0x435e		/* 43229 802.11n 2.4GHz device */
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#define BCM43229_D11N5G_ID	0x435c		/* 43229 802.11n 5GHz device (same as 43228?) */
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#define BCM4337_D11AC_ID	0x43a6
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#define BCM4337_D11AC2G_ID	0x43a7
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#define BCM4337_D11AC5G_ID	0x43a8
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#endif	/* UNRELEASEDCHIP */
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207
#define	BCMGPRS_UART_ID		0x4333		/* Uart id used by 4306/gprs card */
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#define	BCMGPRS2_UART_ID	0x4344		/* Uart id used by 4306/gprs card */
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#define FPGA_JTAGM_ID		0x43f0		/* FPGA jtagm device id */
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#define BCM_JTAGM_ID		0x43f1		/* BCM jtagm device id */
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#define SDIOH_FPGA_ID		0x43f2		/* sdio host fpga */
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#define BCM_SDIOH_ID		0x43f3		/* BCM sdio host id */
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#define SDIOD_FPGA_ID		0x43f4		/* sdio device fpga */
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#define SPIH_FPGA_ID		0x43f5		/* PCI SPI Host Controller FPGA */
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#define BCM_SPIH_ID		0x43f6		/* Synopsis SPI Host Controller */
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#define MIMO_FPGA_ID		0x43f8		/* FPGA mimo minimacphy device id */
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#define BCM_JTAGM2_ID		0x43f9		/* BCM alternate jtagm device id */
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#define SDHCI_FPGA_ID		0x43fa		/* Standard SDIO Host Controller FPGA */
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#define	BCM4402_ENET_ID		0x4402		/* 4402 enet */
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#define	BCM4402_V90_ID		0x4403		/* 4402 v90 codec */
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#define	BCM4410_DEVICE_ID	0x4410		/* bcm44xx family pci iline */
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#define	BCM4412_DEVICE_ID	0x4412		/* bcm44xx family pci enet */
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#define	BCM4430_DEVICE_ID	0x4430		/* bcm44xx family cardbus iline */
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#define	BCM4432_DEVICE_ID	0x4432		/* bcm44xx family cardbus enet */
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#define	BCM4704_ENET_ID		0x4706		/* 4704 enet (Use 47XX_ENET_ID instead!) */
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#define	BCM4710_DEVICE_ID	0x4710		/* 4710 primary function 0 */
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#define	BCM47XX_AUDIO_ID	0x4711		/* 47xx audio codec */
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#define	BCM47XX_V90_ID		0x4712		/* 47xx v90 codec */
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#define	BCM47XX_ENET_ID		0x4713		/* 47xx enet */
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#define	BCM47XX_EXT_ID		0x4714		/* 47xx external i/f */
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#define	BCM47XX_GMAC_ID		0x4715		/* 47xx Unimac based GbE */
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#define	BCM47XX_USBH_ID		0x4716		/* 47xx usb host */
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#define	BCM47XX_USBD_ID		0x4717		/* 47xx usb device */
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#define	BCM47XX_IPSEC_ID	0x4718		/* 47xx ipsec */
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#define	BCM47XX_ROBO_ID		0x4719		/* 47xx/53xx roboswitch core */
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#define	BCM47XX_USB20H_ID	0x471a		/* 47xx usb 2.0 host */
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#define	BCM47XX_USB20D_ID	0x471b		/* 47xx usb 2.0 device */
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#define	BCM47XX_ATA100_ID	0x471d		/* 47xx parallel ATA */
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#define	BCM47XX_SATAXOR_ID	0x471e		/* 47xx serial ATA & XOR DMA */
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#define	BCM47XX_GIGETH_ID	0x471f		/* 47xx GbE (5700) */
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#define	BCM4712_MIPS_ID		0x4720		/* 4712 base devid */
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#define	BCM4716_DEVICE_ID	0x4722		/* 4716 base devid */
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#define	BCM47XX_USB30H_ID	0x472a		/* 47xx usb 3.0 host */
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#define	BCM47XX_USB30D_ID	0x472b		/* 47xx usb 3.0 device */
245
#define BCM47XX_SMBUS_EMU_ID	0x47fe		/* 47xx emulated SMBus device */
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#define	BCM47XX_XOR_EMU_ID	0x47ff		/* 47xx emulated XOR engine */
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#define	EPI41210_DEVICE_ID	0xa0fa		/* bcm4210 */
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#define	EPI41230_DEVICE_ID	0xa10e		/* bcm4230 */
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#define JINVANI_SDIOH_ID	0x4743		/* Jinvani SDIO Gold Host */
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#define BCM27XX_SDIOH_ID	0x2702		/* BCM27xx Standard SDIO Host */
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#define PCIXX21_FLASHMEDIA_ID	0x803b		/* TI PCI xx21 Standard Host Controller */
252
#define PCIXX21_SDIOH_ID	0x803c		/* TI PCI xx21 Standard Host Controller */
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#define R5C822_SDIOH_ID		0x0822		/* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
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#define JMICRON_SDIOH_ID	0x2381		/* JMicron Standard SDIO Host Controller */
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/* Chip IDs */
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#define	BCM4306_CHIP_ID		0x4306		/* 4306 chipcommon chipid */
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#define	BCM4311_CHIP_ID		0x4311		/* 4311 PCIe 802.11a/b/g */
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#define	BCM43111_CHIP_ID	43111		/* 43111 chipcommon chipid (OTP chipid) */
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#define	BCM43112_CHIP_ID	43112		/* 43112 chipcommon chipid (OTP chipid) */
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#define	BCM4312_CHIP_ID		0x4312		/* 4312 chipcommon chipid */
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#define BCM4313_CHIP_ID		0x4313		/* 4313 chip id */
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#define	BCM43131_CHIP_ID	43131		/* 43131 chip id (OTP chipid) */
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#define	BCM4315_CHIP_ID		0x4315		/* 4315 chip id */
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#define	BCM4318_CHIP_ID		0x4318		/* 4318 chipcommon chipid */
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#define	BCM4319_CHIP_ID		0x4319		/* 4319 chip id */
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#define	BCM4320_CHIP_ID		0x4320		/* 4320 chipcommon chipid */
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#define	BCM4321_CHIP_ID		0x4321		/* 4321 chipcommon chipid */
269
#define	BCM43217_CHIP_ID	43217		/* 43217 chip id (OTP chipid) */
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#define	BCM4322_CHIP_ID		0x4322		/* 4322 chipcommon chipid */
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#define	BCM43221_CHIP_ID	43221		/* 43221 chipcommon chipid (OTP chipid) */
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#define	BCM43222_CHIP_ID	43222		/* 43222 chipcommon chipid */
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#define	BCM43224_CHIP_ID	43224		/* 43224 chipcommon chipid */
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#define	BCM43225_CHIP_ID	43225		/* 43225 chipcommon chipid */
275
#define	BCM43227_CHIP_ID	43227		/* 43227 chipcommon chipid */
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#define	BCM43228_CHIP_ID	43228		/* 43228 chipcommon chipid */
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#define	BCM43226_CHIP_ID	43226		/* 43226 chipcommon chipid */
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#define	BCM43231_CHIP_ID	43231		/* 43231 chipcommon chipid (OTP chipid) */
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#define	BCM43234_CHIP_ID	43234		/* 43234 chipcommon chipid */
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#define	BCM43235_CHIP_ID	43235		/* 43235 chipcommon chipid */
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#define	BCM43236_CHIP_ID	43236		/* 43236 chipcommon chipid */
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#define	BCM43237_CHIP_ID	43237		/* 43237 chipcommon chipid */
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#define	BCM43238_CHIP_ID	43238		/* 43238 chipcommon chipid */
284
#define	BCM43239_CHIP_ID	43239		/* 43239 chipcommon chipid */
285
#define	BCM43420_CHIP_ID	43420		/* 43222 chipcommon chipid (OTP, RBBU) */
286
#define	BCM43421_CHIP_ID	43421		/* 43224 chipcommon chipid (OTP, RBBU) */
287
#define	BCM43428_CHIP_ID	43428		/* 43228 chipcommon chipid (OTP, RBBU) */
288
#define	BCM43431_CHIP_ID	43431		/* 4331  chipcommon chipid (OTP, RBBU) */
289
#define	BCM43460_CHIP_ID	43460		/* 4360  chipcommon chipid (OTP, RBBU) */
290
#define	BCM4325_CHIP_ID		0x4325		/* 4325 chip id */
291
#define	BCM4328_CHIP_ID		0x4328		/* 4328 chip id */
292
#define	BCM4329_CHIP_ID		0x4329		/* 4329 chipcommon chipid */
293
#define	BCM4331_CHIP_ID		0x4331		/* 4331 chipcommon chipid */
294
#define BCM4336_CHIP_ID		0x4336		/* 4336 chipcommon chipid */
295
#define BCM43362_CHIP_ID	43362		/* 43362 chipcommon chipid */
296
#define BCM4330_CHIP_ID		0x4330		/* 4330 chipcommon chipid */
297
#define BCM6362_CHIP_ID		0x6362		/* 6362 chipcommon chipid */
298
#define BCM4314_CHIP_ID		0x4314		/* 4314 chipcommon chipid */
299
#define BCM43142_CHIP_ID	43142		/* 43142 chipcommon chipid */
300
#define BCM43143_CHIP_ID	43143		/* 43143 chipcommon chipid */
301
#define	BCM4324_CHIP_ID		0x4324		/* 4324 chipcommon chipid */
302
#define	BCM43242_CHIP_ID	43242		/* 43242 chipcommon chipid */
303
#define	BCM43243_CHIP_ID	43243		/* 43243 chipcommon chipid */
304
#define BCM4334_CHIP_ID		0x4334		/* 4334 chipcommon chipid */
305
#define BCM4335_CHIP_ID		0x4335		/* 4335 chipcommon chipid */
306
#define BCM4339_CHIP_ID		0x4339		/* 4339 chipcommon chipid */
307
#define BCM4360_CHIP_ID		0x4360          /* 4360 chipcommon chipid */
308
#define BCM4352_CHIP_ID		0x4352          /* 4352 chipcommon chipid */
309
#define BCM43526_CHIP_ID	0xAA06
310
#define BCM43341_CHIP_ID	43341		/* 43341 chipcommon chipid */
311
#define BCM43342_CHIP_ID	43342		/* 43342 chipcommon chipid */
312
#define BCM4350_CHIP_ID		0x4350          /* 4350 chipcommon chipid */
313
#define BCM43556_CHIP_ID	0xAA24          /* 43556 chipcommon chipid */
314
#ifdef UNRELEASEDCHIP
315
#define BCM4337_CHIP_ID		0x4337          /* 4337 chipcommon chipid */
316
#define BCM4345_CHIP_ID		0x4345		/* 4345 chipcommon chipid */
317
#define BCM43602_CHIP_ID	0xaa52		/* 43602 chipcommon chipid */
318
#endif /* UNRELEASEDCHIP */
319

320
#define	BCM4342_CHIP_ID		4342		/* 4342 chipcommon chipid (OTP, RBBU) */
321
#define	BCM4402_CHIP_ID		0x4402		/* 4402 chipid */
322
#define	BCM4704_CHIP_ID		0x4704		/* 4704 chipcommon chipid */
323
#define	BCM4706_CHIP_ID		0x5300		/* 4706 chipcommon chipid */
324
#define BCM4707_CHIP_ID		53010		/* 4707 chipcommon chipid */
325
#define BCM53018_CHIP_ID	53018		/* 53018 chipcommon chipid */
326
#define BCM4707_CHIP(chipid)	(((chipid) == BCM4707_CHIP_ID) || ((chipid) == BCM53018_CHIP_ID))
327
#define	BCM4710_CHIP_ID		0x4710		/* 4710 chipid */
328
#define	BCM4712_CHIP_ID		0x4712		/* 4712 chipcommon chipid */
329
#define	BCM4716_CHIP_ID		0x4716		/* 4716 chipcommon chipid */
330
#define	BCM47162_CHIP_ID	47162		/* 47162 chipcommon chipid */
331
#define	BCM4748_CHIP_ID		0x4748		/* 4716 chipcommon chipid (OTP, RBBU) */
332
#define	BCM4749_CHIP_ID		0x4749		/* 5357 chipcommon chipid (OTP, RBBU) */
333
#define BCM4785_CHIP_ID		0x4785		/* 4785 chipcommon chipid */
334
#define	BCM5350_CHIP_ID		0x5350		/* 5350 chipcommon chipid */
335
#define	BCM5352_CHIP_ID		0x5352		/* 5352 chipcommon chipid */
336
#define	BCM5354_CHIP_ID		0x5354		/* 5354 chipcommon chipid */
337
#define BCM5365_CHIP_ID		0x5365		/* 5365 chipcommon chipid */
338
#define	BCM5356_CHIP_ID		0x5356		/* 5356 chipcommon chipid */
339
#define	BCM5357_CHIP_ID		0x5357		/* 5357 chipcommon chipid */
340
#define	BCM53572_CHIP_ID	53572		/* 53572 chipcommon chipid */
341

342
/* Package IDs */
343
#define	BCM4303_PKG_ID		2		/* 4303 package id */
344
#define	BCM4309_PKG_ID		1		/* 4309 package id */
345
#define	BCM4712LARGE_PKG_ID	0		/* 340pin 4712 package id */
346
#define	BCM4712SMALL_PKG_ID	1		/* 200pin 4712 package id */
347
#define	BCM4712MID_PKG_ID	2		/* 225pin 4712 package id */
348
#define BCM4328USBD11G_PKG_ID	2		/* 4328 802.11g USB package id */
349
#define BCM4328USBDUAL_PKG_ID	3		/* 4328 802.11a/g USB package id */
350
#define BCM4328SDIOD11G_PKG_ID	4		/* 4328 802.11g SDIO package id */
351
#define BCM4328SDIODUAL_PKG_ID	5		/* 4328 802.11a/g SDIO package id */
352
#define BCM4329_289PIN_PKG_ID	0		/* 4329 289-pin package id */
353
#define BCM4329_182PIN_PKG_ID	1		/* 4329N 182-pin package id */
354
#define BCM5354E_PKG_ID		1		/* 5354E package id */
355
#define	BCM4716_PKG_ID		8		/* 4716 package id */
356
#define	BCM4717_PKG_ID		9		/* 4717 package id */
357
#define	BCM4718_PKG_ID		10		/* 4718 package id */
358
#define BCM5356_PKG_NONMODE	1		/* 5356 package without nmode suppport */
359
#define BCM5358U_PKG_ID		8		/* 5358U package id */
360
#define BCM5358_PKG_ID		9		/* 5358 package id */
361
#define BCM47186_PKG_ID		10		/* 47186 package id */
362
#define BCM5357_PKG_ID		11		/* 5357 package id */
363
#define BCM5356U_PKG_ID		12		/* 5356U package id */
364
#define BCM53572_PKG_ID		8		/* 53572 package id */
365
#define BCM5357C0_PKG_ID	8		/* 5357c0 package id (the same as 53572) */
366
#define BCM47188_PKG_ID		9		/* 47188 package id */
367
#define BCM5358C0_PKG_ID	0xa		/* 5358c0 package id */
368
#define BCM5356C0_PKG_ID	0xb		/* 5356c0 package id */
369
#define BCM4331TT_PKG_ID        8		/* 4331 12x12 package id */
370
#define BCM4331TN_PKG_ID        9		/* 4331 12x9 package id */
371
#define BCM4331TNA0_PKG_ID     0xb		/* 4331 12x9 package id */
372
/* XXX 4706L corresponding to BCM53001 */
373
#define	BCM4706L_PKG_ID		1		/* 4706L package id */
374

375
#define HDLSIM5350_PKG_ID	1		/* HDL simulator package id for a 5350 */
376
#define HDLSIM_PKG_ID		14		/* HDL simulator package id */
377
#define HWSIM_PKG_ID		15		/* Hardware simulator package id */
378
#define BCM43224_FAB_CSM	0x8		/* the chip is manufactured by CSM */
379
#define BCM43224_FAB_SMIC	0xa		/* the chip is manufactured by SMIC */
380
#define BCM4336_WLBGA_PKG_ID	0x8
381
#define BCM4330_WLBGA_PKG_ID	0x0
382
#define BCM4314PCIE_ARM_PKG_ID		(8 | 0)	/* 4314 QFN PCI package id, bit 3 tie high */
383
#define BCM4314SDIO_PKG_ID		(8 | 1)	/* 4314 QFN SDIO package id */
384
#define BCM4314PCIE_PKG_ID		(8 | 2)	/* 4314 QFN PCI (ARM-less) package id */
385
#define BCM4314SDIO_ARM_PKG_ID		(8 | 3)	/* 4314 QFN SDIO (ARM-less) package id */
386
#define BCM4314SDIO_FPBGA_PKG_ID	(8 | 4)	/* 4314 FpBGA SDIO package id */
387
#define BCM4314DEV_PKG_ID		(8 | 6)	/* 4314 Developement package id */
388

389
#define BCM4707_PKG_ID		1		/* 4707 package id */
390
#define BCM4708_PKG_ID		2		/* 4708 package id */
391
#define BCM4709_PKG_ID		0		/* 4709 package id */
392

393
#define PCIXX21_FLASHMEDIA0_ID	0x8033		/* TI PCI xx21 Standard Host Controller */
394
#define PCIXX21_SDIOH0_ID	0x8034		/* TI PCI xx21 Standard Host Controller */
395

396
#define BCM4335_WLCSP_PKG_ID	(0x0)	/* WLCSP Module/Mobile SDIO/HSIC. */
397
#define BCM4335_FCBGA_PKG_ID	(0x1)	/* FCBGA PC/Embeded/Media PCIE/SDIO */
398
#define BCM4335_WLBGA_PKG_ID	(0x2)	/* WLBGA COB/Mobile SDIO/HSIC. */
399
#define BCM4335_FCBGAD_PKG_ID	(0x3)	/* FCBGA Debug Debug/Dev All if's. */
400
#define BCM4335_PKG_MASK	(0x3)
401

402
/* boardflags */
403
#define	BFL_BTC2WIRE		0x00000001  /* old 2wire Bluetooth coexistence, OBSOLETE */
404
#define BFL_BTCOEX      0x00000001      /* Board supports BTCOEX */
405
#define	BFL_PACTRL		0x00000002  /* Board has gpio 9 controlling the PA */
406
#define BFL_AIRLINEMODE	0x00000004  /* Board implements gpio 13 radio disable indication, UNUSED */
407
#define	BFL_ADCDIV		0x00000008  /* Board has the rssi ADC divider */
408
#define BFL_DIS_256QAM		0x00000008
409
					/* XXX: for 4360, this bit is to disable 256QAM support */
410
#define	BFL_ENETROBO		0x00000010  /* Board has robo switch or core */
411
#define	BFL_NOPLLDOWN		0x00000020  /* Not ok to power down the chip pll and oscillator */
412
#define	BFL_CCKHIPWR		0x00000040  /* Can do high-power CCK transmission */
413
#define	BFL_ENETADM		0x00000080  /* Board has ADMtek switch */
414
#define	BFL_ENETVLAN		0x00000100  /* Board has VLAN capability */
415
#define	BFL_UNUSED		0x00000200  /* XXX: unused flag */
416
#define BFL_NOPCI		0x00000400  /* Board leaves PCI floating */
417
#define BFL_FEM			0x00000800  /* Board supports the Front End Module */
418
#define BFL_EXTLNA		0x00001000  /* Board has an external LNA in 2.4GHz band */
419
#define BFL_HGPA		0x00002000  /* Board has a high gain PA */
420
#define	BFL_BTC2WIRE_ALTGPIO	0x00004000  /* Board's BTC 2wire is in the alternate gpios */
421
#define	BFL_ALTIQ		0x00008000  /* Alternate I/Q settings */
422
#define BFL_NOPA		0x00010000  /* Board has no PA */
423
#define BFL_RSSIINV		0x00020000  /* Board's RSSI uses positive slope(not TSSI) */
424
#define BFL_PAREF		0x00040000  /* Board uses the PARef LDO */
425
#define BFL_3TSWITCH		0x00080000  /* Board uses a triple throw switch shared with BT */
426
#define BFL_PHASESHIFT		0x00100000  /* Board can support phase shifter */
427
#define BFL_BUCKBOOST		0x00200000  /* Power topology uses BUCKBOOST */
428
#define BFL_FEM_BT		0x00400000  /* Board has FEM and switch to share antenna w/ BT */
429
#define BFL_NOCBUCK		0x00800000  /* Power topology doesn't use CBUCK */
430
#define BFL_CCKFAVOREVM		0x01000000  /* Favor CCK EVM over spectral mask */
431
#define BFL_PALDO		0x02000000  /* Power topology uses PALDO */
432
#define BFL_LNLDO2_2P5		0x04000000  /* Select 2.5V as LNLDO2 output voltage */
433
/* XXX BFL_FASTPWR and BFL_UCPWRCTL_MININDX are non-overlaping features and use the same bit */
434
#define BFL_FASTPWR		0x08000000  /* XXX Fast switch/antenna powerup (no POR WAR) */
435
#define BFL_UCPWRCTL_MININDX	0x08000000  /* Enforce min power index to avoid FEM damage */
436
#define BFL_EXTLNA_5GHz		0x10000000  /* Board has an external LNA in 5GHz band */
437
#define BFL_TRSW_1by2		0x20000000  /* Board has 2 TRSW's in 1by2 designs */
438
#define BFL_GAINBOOSTA01        0x20000000  /* 5g Gainboost for core0 and core1 */
439
#define BFL_LO_TRSW_R_5GHz	0x40000000  /* In 5G do not throw TRSW to T for clipLO gain */
440
#define BFL_ELNA_GAINDEF	0x80000000  /* Backoff InitGain based on elna_2g/5g field
441
					     * when this flag is set
442
					     */
443
#define BFL_EXTLNA_TX	0x20000000	/* Temp boardflag to indicate to */
444

445
/* boardflags2 */
446
#define BFL2_RXBB_INT_REG_DIS	0x00000001  /* Board has an external rxbb regulator */
447
#define BFL2_APLL_WAR		0x00000002  /* Flag to implement alternative A-band PLL settings */
448
#define BFL2_TXPWRCTRL_EN	0x00000004  /* Board permits enabling TX Power Control */
449
#define BFL2_2X4_DIV		0x00000008  /* Board supports the 2X4 diversity switch */
450
#define BFL2_5G_PWRGAIN		0x00000010  /* Board supports 5G band power gain */
451
#define BFL2_PCIEWAR_OVR	0x00000020  /* Board overrides ASPM and Clkreq settings */
452
#define BFL2_CAESERS_BRD	0x00000040  /* Board is Caesers brd (unused by sw) */
453
#define BFL2_BTC3WIRE		0x00000080  /* Board support legacy 3 wire or 4 wire */
454
#define BFL2_BTCLEGACY          0x00000080  /* Board support legacy 3/4 wire, to replace
455
					     * BFL2_BTC3WIRE
456
					     */
457
#define BFL2_SKWRKFEM_BRD	0x00000100  /* 4321mcm93 board uses Skyworks FEM */
458
#define BFL2_SPUR_WAR		0x00000200  /* Board has a WAR for clock-harmonic spurs */
459
#define BFL2_GPLL_WAR		0x00000400  /* Flag to narrow G-band PLL loop b/w */
460
#define BFL2_TRISTATE_LED	0x00000800  /* Tri-state the LED */
461
#define BFL2_SINGLEANT_CCK	0x00001000  /* Tx CCK pkts on Ant 0 only */
462
#define BFL2_2G_SPUR_WAR	0x00002000  /* WAR to reduce and avoid clock-harmonic spurs in 2G */
463
#define BFL2_BPHY_ALL_TXCORES	0x00004000  /* Transmit bphy frames using all tx cores */
464
#define BFL2_FCC_BANDEDGE_WAR	0x00008000  /* Activates WAR to improve FCC bandedge performance */
465
#define BFL2_GPLL_WAR2	        0x00010000  /* Flag to widen G-band PLL loop b/w */
466
#define BFL2_IPALVLSHIFT_3P3    0x00020000  /* Flag to Activate the PR 74115 PA Level Shift
467
					     * Workaround where the gpaio pin is connected to 3.3V
468
					     */
469
#define BFL2_INTERNDET_TXIQCAL  0x00040000  /* Use internal envelope detector for TX IQCAL */
470
#define BFL2_XTALBUFOUTEN       0x00080000  /* Keep the buffered Xtal output from radio on */
471
				/* Most drivers will turn it off without this flag */
472
				/* to save power. */
473

474
#define BFL2_ANAPACTRL_2G	0x00100000  /* 2G ext PAs are controlled by analog PA ctrl lines */
475
#define BFL2_ANAPACTRL_5G	0x00200000  /* 5G ext PAs are controlled by analog PA ctrl lines */
476
#define BFL2_ELNACTRL_TRSW_2G	0x00400000  /* AZW4329: 2G gmode_elna_gain controls TR Switch */
477
#define BFL2_BT_SHARE_ANT0	0x00800000  /* share core0 antenna with BT */
478
#define BFL2_TEMPSENSE_HIGHER	0x01000000  /* The tempsense threshold can sustain higher value
479
					     * than programmed. The exact delta is decided by
480
					     * driver per chip/boardtype. This can be used
481
					     * when tempsense qualification happens after shipment
482
					     */
483
#define BFL2_BTC3WIREONLY       0x02000000  /* standard 3 wire btc only.  4 wire not supported */
484
#define BFL2_PWR_NOMINAL	0x04000000  /* 0: power reduction on, 1: no power reduction */
485
#define BFL2_EXTLNA_PWRSAVE	0x08000000  /* boardflag to enable ucode to apply power save */
486
						/* ucode control of eLNA during Tx */
487
#define BFL2_4313_RADIOREG	0x10000000 /* 4313 radio register change (PR82977) need to match */
488
									   /*  board rework */
489
#define BFL2_DYNAMIC_VMID	0x10000000  /* enable dynamic Vmid in idle TSSI CAL for 4331 */
490

491
#define BFL2_SDR_EN		0x20000000  /* SDR enabled or disabled */
492
#define BFL2_DYNAMIC_VMID	0x10000000  /* boardflag to enable dynamic Vmid idle TSSI CAL */
493
#define BFL2_LNA1BYPFORTR2G	0x40000000  /* acphy, enable lna1 bypass for clip gain, 2g */
494
#define BFL2_LNA1BYPFORTR5G	0x80000000  /* acphy, enable lna1 bypass for clip gain, 5g */
495

496
/* SROM 11 - 11ac boardflag definitions */
497
#define BFL_SROM11_BTCOEX  0x00000001  /* Board supports BTCOEX */
498
#define BFL_SROM11_WLAN_BT_SH_XTL  0x00000002  /* bluetooth and wlan share same crystal */
499
#define BFL_SROM11_EXTLNA	0x00001000  /* Board has an external LNA in 2.4GHz band */
500
#define BFL_SROM11_EXTLNA_5GHz	0x10000000  /* Board has an external LNA in 5GHz band */
501
#define BFL_SROM11_GAINBOOSTA01	0x20000000  /* 5g Gainboost for core0 and core1 */
502
#define BFL2_SROM11_APLL_WAR	0x00000002  /* Flag to implement alternative A-band PLL settings */
503
#define BFL2_SROM11_ANAPACTRL_2G  0x00100000  /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
504
#define BFL2_SROM11_ANAPACTRL_5G  0x00200000  /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */
505
#define BFL2_SROM11_SINGLEANT_CCK	0x00001000  /* Tx CCK pkts on Ant 0 only */
506

507
/* boardflags3 */
508
#define BFL3_FEMCTRL_SUB	  0x00000007  /* acphy, subrevs of femctrl on top of srom_femctrl */
509
#define BFL3_RCAL_WAR		  0x00000008  /* acphy, rcal war active on this board (4335a0) */
510
#define BFL3_TXGAINTBLID	  0x00000070  /* acphy, txgain table id */
511
#define BFL3_TXGAINTBLID_SHIFT	  0x4         /* acphy, txgain table id shift bit */
512
#define BFL3_TSSI_DIV_WAR	  0x00000080  /* acphy, Seperate paparam for 20/40/80 */
513
#define BFL3_TSSI_DIV_WAR_SHIFT	  0x7         /* acphy, Seperate paparam for 20/40/80 shift bit */
514
#define BFL3_FEMTBL_FROM_NVRAM    0x00000100  /* acphy, femctrl table is read from nvram */
515
#define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8         /* acphy, femctrl table is read from nvram */
516
#define BFL3_AGC_CFG_2G           0x00000200  /* acphy, gain control configuration for 2G */
517
#define BFL3_AGC_CFG_5G           0x00000400  /* acphy, gain control configuration for 5G */
518
#define BFL3_PPR_BIT_EXT          0x00000800  /* acphy, bit position for 1bit extension for ppr */
519
#define BFL3_PPR_BIT_EXT_SHIFT    11          /* acphy, bit shift for 1bit extension for ppr */
520
#define BFL3_BBPLL_SPR_MODE_DIS	  0x00001000  /* acphy, disables bbpll spur modes */
521
#define BFL3_RCAL_OTP_VAL_EN      0x00002000  /* acphy, to read rcal_trim value from otp */
522
#define BFL3_2GTXGAINTBL_BLANK	  0x00004000  /* acphy, blank the first X ticks of 2g gaintbl */
523
#define BFL3_2GTXGAINTBL_BLANK_SHIFT 14       /* acphy, blank the first X ticks of 2g gaintbl */
524
#define BFL3_5GTXGAINTBL_BLANK	  0x00008000  /* acphy, blank the first X ticks of 5g gaintbl */
525
#define BFL3_5GTXGAINTBL_BLANK_SHIFT 15       /* acphy, blank the first X ticks of 5g gaintbl */
526
#define BFL3_PHASETRACK_MAX_ALPHABETA	  0x00010000  /* acphy, to max out alpha,beta to 511 */
527
#define BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16       /* acphy, to max out alpha,beta to 511 */
528
/* acphy, to use backed off gaintbl for lte-coex */
529
#define BFL3_LTECOEX_GAINTBL_EN           0x00060000
530
/* acphy, to use backed off gaintbl for lte-coex */
531
#define BFL3_LTECOEX_GAINTBL_EN_SHIFT 17
532
#define BFL3_5G_SPUR_WAR          0x00080000  /* acphy, enable spur WAR in 5G band */
533

534
/* acphy: lpmode2g and lpmode_5g related boardflags */
535
#define BFL3_ACPHY_LPMODE_2G	  0x00300000  /* bits 20:21 for lpmode_2g choice */
536
#define BFL3_ACPHY_LPMODE_2G_SHIFT	  20
537

538
#define BFL3_ACPHY_LPMODE_5G	  0x00C00000  /* bits 22:23 for lpmode_5g choice */
539
#define BFL3_ACPHY_LPMODE_5G_SHIFT	  22
540

541
#define BFL3_EN_BRCM_IMPBF        0x10000000  /* acphy, Allow BRCM Implicit TxBF */
542
#define BFL3_AVVMID_FROM_NVRAM    0x40000000  /* Read Av Vmid from NVRAM  */
543
#define BFL3_AVVMID_FROM_NVRAM_SHIFT   30   /* Read Av Vmid from NVRAM  */
544
#define BFL3_FORCE_INT_LPO_SEL    0x04000000  /* Force internal lpo */
545
#define BFL3_FORCE_EXT_LPO_SEL    0x08000000  /* Force external lpo */
546

547

548
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
549
#define	BOARD_GPIO_BTC3W_IN	0x850	/* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
550
#define	BOARD_GPIO_BTC3W_OUT	0x020	/* bit 5 is TX_CONF */
551
#define	BOARD_GPIO_BTCMOD_IN	0x010	/* bit 4 is the alternate BT Coexistence Input */
552
#define	BOARD_GPIO_BTCMOD_OUT	0x020	/* bit 5 is the alternate BT Coexistence Out */
553
#define	BOARD_GPIO_BTC_IN	0x080	/* bit 7 is BT Coexistence Input */
554
#define	BOARD_GPIO_BTC_OUT	0x100	/* bit 8 is BT Coexistence Out */
555
#define	BOARD_GPIO_PACTRL	0x200	/* bit 9 controls the PA on new 4306 boards */
556
#define BOARD_GPIO_12		0x1000	/* gpio 12 */
557
#define BOARD_GPIO_13		0x2000	/* gpio 13 */
558
#define BOARD_GPIO_BTC4_IN	0x0800	/* gpio 11, coex4, in */
559
#define BOARD_GPIO_BTC4_BT	0x2000	/* gpio 12, coex4, bt active */
560
#define BOARD_GPIO_BTC4_STAT	0x4000	/* gpio 14, coex4, status */
561
#define BOARD_GPIO_BTC4_WLAN	0x8000	/* gpio 15, coex4, wlan active */
562
#define	BOARD_GPIO_1_WLAN_PWR	0x02	/* throttle WLAN power on X21 board */
563
#define	BOARD_GPIO_2_WLAN_PWR	0x04	/* throttle WLAN power on X29C board */
564
#define	BOARD_GPIO_3_WLAN_PWR	0x08	/* throttle WLAN power on X28 board */
565
#define	BOARD_GPIO_4_WLAN_PWR	0x10	/* throttle WLAN power on X19 board */
566

567
#define GPIO_BTC4W_OUT_4312  0x010  /* bit 4 is BT_IODISABLE */
568
#define GPIO_BTC4W_OUT_43224  0x020  /* bit 5 is BT_IODISABLE */
569
#define GPIO_BTC4W_OUT_43224_SHARED  0x0e0  /* bit 5 is BT_IODISABLE */
570
#define GPIO_BTC4W_OUT_43225  0x0e0  /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */
571
#define GPIO_BTC4W_OUT_43421  0x020  /* bit 5 is BT_IODISABLE */
572
#define GPIO_BTC4W_OUT_4313  0x060  /* bit 5 SW_BT, bit 6 SW_WL */
573
#define GPIO_BTC4W_OUT_4331_SHARED  0x010  /* GPIO 4  */
574

575
#define	PCI_CFG_GPIO_SCS	0x10	/* PCI config space bit 4 for 4306c0 slow clock source */
576
#define PCI_CFG_GPIO_HWRAD	0x20	/* PCI config space GPIO 13 for hw radio disable */
577
#define PCI_CFG_GPIO_XTAL	0x40	/* PCI config space GPIO 14 for Xtal power-up */
578
#define PCI_CFG_GPIO_PLL	0x80	/* PCI config space GPIO 15 for PLL power-down */
579

580
/* XXX, need to be moved to a chip specific header file */
581
/* power control defines */
582
#define PLL_DELAY		150		/* us pll on delay */
583
#define FREF_DELAY		200		/* us fref change delay */
584
#define MIN_SLOW_CLK		32		/* us Slow clock period */
585
#define	XTAL_ON_DELAY		1000		/* us crystal power-on delay */
586

587
#ifndef LINUX_POSTMOGRIFY_REMOVAL
588
/* Reference Board Types */
589
#define	BU4710_BOARD		0x0400
590
#define	VSIM4710_BOARD		0x0401
591
#define	QT4710_BOARD		0x0402
592

593
#define	BU4309_BOARD		0x040a
594
#define	BCM94309CB_BOARD	0x040b
595
#define	BCM94309MP_BOARD	0x040c
596
#define	BCM4309AP_BOARD		0x040d
597

598
#define	BCM94302MP_BOARD	0x040e
599

600
#define	BU4306_BOARD		0x0416
601
#define	BCM94306CB_BOARD	0x0417
602
#define	BCM94306MP_BOARD	0x0418
603

604
#define	BCM94710D_BOARD		0x041a
605
#define	BCM94710R1_BOARD	0x041b
606
#define	BCM94710R4_BOARD	0x041c
607
#define	BCM94710AP_BOARD	0x041d
608

609
#define	BU2050_BOARD		0x041f
610

611
#define	BCM94306P50_BOARD	0x0420
612

613
#define	BCM94309G_BOARD		0x0421
614

615
#define	BU4704_BOARD		0x0423
616
#define	BU4702_BOARD		0x0424
617

618
#define	BCM94306PC_BOARD	0x0425		/* pcmcia 3.3v 4306 card */
619

620
#define	MPSG4306_BOARD		0x0427
621

622
#define	BCM94702MN_BOARD	0x0428
623

624
/* BCM4702 1U CompactPCI Board */
625
#define	BCM94702CPCI_BOARD	0x0429
626

627
/* BCM4702 with BCM95380 VLAN Router */
628
#define	BCM95380RR_BOARD	0x042a
629

630
/* cb4306 with SiGe PA */
631
#define	BCM94306CBSG_BOARD	0x042b
632

633
/* cb4306 with SiGe PA */
634
#define	PCSG94306_BOARD		0x042d
635

636
/* bu4704 with sdram */
637
#define	BU4704SD_BOARD		0x042e
638

639
/* Dual 11a/11g Router */
640
#define	BCM94704AGR_BOARD	0x042f
641

642
/* 11a-only minipci */
643
#define	BCM94308MP_BOARD	0x0430
644

645
/* 4306/gprs combo */
646
#define	BCM94306GPRS_BOARD	0x0432
647

648
/* BCM5365/BCM4704 FPGA Bringup Board */
649
#define BU5365_FPGA_BOARD	0x0433
650

651
#define BU4712_BOARD		0x0444
652
#define	BU4712SD_BOARD		0x045d
653
#define	BU4712L_BOARD		0x045f
654

655
/* BCM4712 boards */
656
#define BCM94712AP_BOARD	0x0445
657
#define BCM94712P_BOARD		0x0446
658

659
/* BCM4318 boards */
660
#define BU4318_BOARD		0x0447
661
#define CB4318_BOARD		0x0448
662
#define MPG4318_BOARD		0x0449
663
#define MP4318_BOARD		0x044a
664
#define SD4318_BOARD		0x044b
665

666
/* BCM4313 boards */
667
#define BCM94313BU_BOARD	0x050f
668
#define BCM94313HM_BOARD	0x0510
669
#define BCM94313EPA_BOARD	0x0511
670
#define BCM94313HMG_BOARD       0x051C
671

672
/* BCM63XX boards */
673
#define BCM96338_BOARD		0x6338
674
#define BCM96348_BOARD		0x6348
675
#define BCM96358_BOARD		0x6358
676
#define BCM96368_BOARD		0x6368
677

678
/* Another mp4306 with SiGe */
679
#define	BCM94306P_BOARD		0x044c
680

681
/* mp4303 */
682
#define	BCM94303MP_BOARD	0x044e
683

684
/* mpsgh4306 */
685
#define	BCM94306MPSGH_BOARD	0x044f
686

687
/* BRCM 4306 w/ Front End Modules */
688
#define BCM94306MPM		0x0450
689
#define BCM94306MPL		0x0453
690

691
/* 4712agr */
692
#define	BCM94712AGR_BOARD	0x0451
693

694
/* pcmcia 4303 */
695
#define	PC4303_BOARD		0x0454
696

697
/* 5350K */
698
#define	BCM95350K_BOARD		0x0455
699

700
/* 5350R */
701
#define	BCM95350R_BOARD		0x0456
702

703
/* 4306mplna */
704
#define	BCM94306MPLNA_BOARD	0x0457
705

706
/* 4320 boards */
707
#define	BU4320_BOARD		0x0458
708
#define	BU4320S_BOARD		0x0459
709
#define	BCM94320PH_BOARD	0x045a
710

711
/* 4306mph */
712
#define	BCM94306MPH_BOARD	0x045b
713

714
/* 4306pciv */
715
#define	BCM94306PCIV_BOARD	0x045c
716

717
#define	BU4712SD_BOARD		0x045d
718

719
#define	BCM94320PFLSH_BOARD	0x045e
720

721
#define	BU4712L_BOARD		0x045f
722
#define	BCM94712LGR_BOARD	0x0460
723
#define	BCM94320R_BOARD		0x0461
724

725
#define	BU5352_BOARD		0x0462
726

727
#define	BCM94318MPGH_BOARD	0x0463
728

729
#define	BU4311_BOARD		0x0464
730
#define	BCM94311MC_BOARD	0x0465
731
#define	BCM94311MCAG_BOARD	0x0466
732

733
#define	BCM95352GR_BOARD	0x0467
734

735
/* bcm95351agr */
736
#define	BCM95351AGR_BOARD	0x0470
737

738
/* bcm94704mpcb */
739
#define	BCM94704MPCB_BOARD	0x0472
740

741
/* 4785 boards */
742
#define BU4785_BOARD		0x0478
743

744
/* 4321 boards */
745
#define BU4321_BOARD		0x046b
746
#define BU4321E_BOARD		0x047c
747
#define MP4321_BOARD		0x046c
748
#define CB2_4321_BOARD		0x046d
749
#define CB2_4321_AG_BOARD	0x0066
750
#define MC4321_BOARD		0x046e
751

752
/* 4328 boards */
753
#define BU4328_BOARD		0x0481
754
#define BCM4328SDG_BOARD	0x0482
755
#define BCM4328SDAG_BOARD	0x0483
756
#define BCM4328UG_BOARD		0x0484
757
#define BCM4328UAG_BOARD	0x0485
758
#define BCM4328PC_BOARD		0x0486
759
#define BCM4328CF_BOARD		0x0487
760

761
/* 4325 boards */
762
#define BCM94325DEVBU_BOARD	0x0490
763
#define BCM94325BGABU_BOARD	0x0491
764

765
#define BCM94325SDGWB_BOARD	0x0492
766

767
#define BCM94325SDGMDL_BOARD	0x04aa
768
#define BCM94325SDGMDL2_BOARD	0x04c6
769
#define BCM94325SDGMDL3_BOARD	0x04c9
770

771
#define BCM94325SDABGWBA_BOARD	0x04e1
772

773
/* 4322 boards */
774
#define BCM94322MC_SSID		0x04a4
775
#define BCM94322USB_SSID	0x04a8	/* dualband */
776
#define BCM94322HM_SSID		0x04b0
777
#define BCM94322USB2D_SSID	0x04bf	/* single band discrete front end */
778

779
/* 4312 boards */
780
#define	BCM4312MCGSG_BOARD	0x04b5
781

782
/* 4315 boards */
783
#define BCM94315DEVBU_SSID	0x04c2
784
#define BCM94315USBGP_SSID	0x04c7
785
#define BCM94315BGABU_SSID	0x04ca
786
#define BCM94315USBGP41_SSID	0x04cb
787

788
/* 4319 boards */
789
#define BCM94319DEVBU_SSID	0X04e5
790
#define BCM94319USB_SSID	0X04e6
791
#define BCM94319SD_SSID		0X04e7
792

793
/* 4716 boards */
794
#define BCM94716NR2_SSID	0x04cd
795

796
/* 4319 boards */
797
#define BCM94319DEVBU_SSID	0X04e5
798
#define BCM94319USBNP4L_SSID	0X04e6
799
#define BCM94319WLUSBN4L_SSID	0X04e7
800
#define BCM94319SDG_SSID	0X04ea
801
#define BCM94319LCUSBSDN4L_SSID	0X04eb
802
#define BCM94319USBB_SSID       0x04ee
803
#define BCM94319LCSDN4L_SSID	0X0507
804
#define BCM94319LSUSBN4L_SSID	0X0508
805
#define BCM94319SDNA4L_SSID	0X0517
806
#define BCM94319SDELNA4L_SSID	0X0518
807
#define BCM94319SDELNA6L_SSID	0X0539
808
#define BCM94319ARCADYAN_SSID	0X0546
809
#define BCM94319WINDSOR_SSID    0x0561
810
#define BCM94319MLAP_SSID       0x0562
811
#define BCM94319SDNA_SSID       0x058b
812
#define BCM94319BHEMU3_SSID     0x0563
813
#define BCM94319SDHMB_SSID     0x058c
814
#define BCM94319SDBREF_SSID     0x05a1
815
#define BCM94319USBSDB_SSID     0x05a2
816

817

818
/* 4329 boards */
819
#define BCM94329AGB_SSID	0X04b9
820
#define BCM94329TDKMDL1_SSID	0X04ba
821
#define BCM94329TDKMDL11_SSID	0X04fc
822
#define BCM94329OLYMPICN18_SSID	0X04fd
823
#define BCM94329OLYMPICN90_SSID	0X04fe
824
#define BCM94329OLYMPICN90U_SSID 0X050c
825
#define BCM94329OLYMPICN90M_SSID 0X050b
826
#define BCM94329AGBF_SSID	0X04ff
827
#define BCM94329OLYMPICX17_SSID	0X0504
828
#define BCM94329OLYMPICX17M_SSID	0X050a
829
#define BCM94329OLYMPICX17U_SSID	0X0509
830
#define BCM94329OLYMPICUNO_SSID	0X0564
831
#define BCM94329MOTOROLA_SSID   0X0565
832
#define BCM94329OLYMPICLOCO_SSID	0X0568
833
/* 4336 SDIO board types */
834
#define BCM94336SD_WLBGABU_SSID		0x0511
835
#define BCM94336SD_WLBGAREF_SSID	0x0519
836
#define BCM94336SDGP_SSID	0x0538
837
#define BCM94336SDG_SSID	0x0519
838
#define BCM94336SDGN_SSID	0x0538
839
#define BCM94336SDGFC_SSID	0x056B
840

841
/* 4330 SDIO board types */
842
#define BCM94330SDG_SSID	0x0528
843
#define BCM94330SD_FCBGABU_SSID	0x052e
844
#define BCM94330SD_WLBGABU_SSID	0x052f
845
#define BCM94330SD_FCBGA_SSID	0x0530
846
#define BCM94330FCSDAGB_SSID		0x0532
847
#define BCM94330OLYMPICAMG_SSID		0x0549
848
#define BCM94330OLYMPICAMGEPA_SSID		0x054F
849
#define BCM94330OLYMPICUNO3_SSID	0x0551
850
#define BCM94330WLSDAGB_SSID	0x0547
851
#define BCM94330CSPSDAGBB_SSID	0x054A
852

853
/* 43224 boards */
854
#define BCM943224X21        0x056e
855
#define BCM943224X21_FCC    0x00d1
856
#define BCM943224X21B	    0x00e9
857
#define BCM943224M93	    0x008b
858
#define BCM943224M93A	    0x0090
859
#define BCM943224X16	    0x0093
860
#define BCM94322X9		    0x008d
861
#define BCM94322M35e	    0x008e
862

863
/* 43228 Boards */
864
#define BCM943228BU8_SSID	0x0540
865
#define BCM943228BU9_SSID	0x0541
866
#define BCM943228BU_SSID	0x0542
867
#define BCM943227HM4L_SSID	0x0543
868
#define BCM943227HMB_SSID	0x0544
869
#define BCM943228HM4L_SSID	0x0545
870
#define BCM943228SD_SSID	0x0573
871

872
/* 43239 Boards */
873
#define BCM943239MOD_SSID	0x05ac
874
#define BCM943239REF_SSID	0x05aa
875

876
/* 4331 boards */
877
#define BCM94331X19               0x00D6	/* X19B */
878
#define BCM94331X28               0x00E4	/* X28 */
879
#define BCM94331X28B              0x010E	/* X28B */
880
#define BCM94331PCIEBT3Ax_SSID    BCM94331X28
881
#define BCM94331X12_2G_SSID       0x00EC	/* X12 2G */
882
#define BCM94331X12_5G_SSID       0x00ED	/* X12 5G */
883
#define BCM94331X29B              0x00EF	/* X29B */
884
#define BCM94331X29D              0x010F	/* X29D */
885
#define BCM94331CSAX_SSID         BCM94331X29B
886
#define BCM94331X19C              0x00F5	/* X19C */
887
#define BCM94331X33	          0x00F4	/* X33 */
888
#define BCM94331BU_SSID           0x0523
889
#define BCM94331S9BU_SSID         0x0524
890
#define BCM94331MC_SSID           0x0525
891
#define BCM94331MCI_SSID          0x0526
892
#define BCM94331PCIEBT4_SSID      0x0527	/* XXX BRCM Build of X19 */
893
#define BCM94331HM_SSID           0x0574
894
#define BCM94331PCIEDUAL_SSID     0x059B	/* XXX BRCM Build of X12 */
895
#define BCM94331MCH5_SSID         0x05A9
896
#define BCM94331CS_SSID           0x05C6	/* XXX BRCM Build of X29 */
897
#define BCM94331CD_SSID           0x05DA	/* XXX BRCM Build of X33 */
898

899
/* 4314 Boards */
900
#define BCM94314BU_SSID         0x05b1
901

902
/* 53572 Boards */
903
#define BCM953572BU_SSID       0x058D
904
#define BCM953572NR2_SSID      0x058E
905
#define BCM947188NR2_SSID      0x058F
906
#define BCM953572SDRNR2_SSID   0x0590
907

908
/* 43236 boards */
909
#define BCM943236OLYMPICSULLEY_SSID 0x594
910
#define BCM943236PREPROTOBLU2O3_SSID 0x5b9
911
#define BCM943236USBELNA_SSID 0x5f8
912

913
/* 4314 Boards */
914
#define BCM94314BUSDIO_SSID	0x05c8
915
#define BCM94314BGABU_SSID	0x05c9
916
#define BCM94314HMEPA_SSID	0x05ca
917
#define BCM94314HMEPABK_SSID	0x05cb
918
#define BCM94314SUHMEPA_SSID	0x05cc
919
#define BCM94314SUHM_SSID	0x05cd
920
#define BCM94314HM_SSID		0x05d1
921

922
/* 4334 Boards */
923
#define BCM94334FCAGBI_SSID	0x05df
924
#define BCM94334WLAGBI_SSID	0x05dd
925

926
/* 4335 Boards */
927
#define BCM94335X52             0x0114
928

929
#ifdef UNRELEASEDCHIP
930
/* 4345 Boards */
931
#define BCM94345_SSID           0x0687
932
#endif /* UNRELEASEDCHIP */
933

934
/* 4360 Boards */
935
#define BCM94360X52C            0X0117
936
#define BCM94360X29C            0X0112
937
#define BCM94360X29CP2          0X1000
938
#define BCM94360X51             0x0111
939
#define BCM94360X51P2           0x0129
940
#define BCM94360CS              0x061B
941
#define BCM94360J28_D11AC2G     0x0c00
942
#define BCM94360J28_D11AC5G     0x0c01
943

944
/* 4350 Boards */
945
#define BCM94350X52B            0X0116
946

947
/* 43217 Boards */
948
#define BCM943217BU_SSID	0x05d5
949
#define BCM943217HM2L_SSID	0x05d6
950
#define BCM943217HMITR2L_SSID	0x05d7
951

952
/* 43142 Boards */
953
#define BCM943142HM_SSID	0x05e0
954
#endif /* LINUX_POSTMOGRIFY_REMOVAL */
955

956
/* 43341 Boards */
957
#define BCM943341WLABGS_SSID	0x062d
958

959
/* 43342 Boards */
960
#define BCM943342FCAGBI_SSID	0x0641
961

962
#ifdef UNRELEASEDCHIP
963
/* 43602 Boards, unclear yet what boards will be created. */
964
#define BCM943602RSVD1_SSID	0x06a5
965
#define BCM943602RSVD2_SSID	0x06a6
966
#endif /* UNRELEASEDCHIP */
967

968
/* # of GPIO pins */
969
#define GPIO_NUMPINS		32
970

971
/* These values are used by dhd host driver. */
972
#define RDL_RAM_BASE_4319 0x60000000
973
#define RDL_RAM_BASE_4329 0x60000000
974
#define RDL_RAM_SIZE_4319 0x48000
975
#define RDL_RAM_SIZE_4329  0x48000
976
#define RDL_RAM_SIZE_43236 0x70000
977
#define RDL_RAM_BASE_43236 0x60000000
978
#define RDL_RAM_SIZE_4328 0x60000
979
#define RDL_RAM_BASE_4328 0x80000000
980
#define RDL_RAM_SIZE_4322 0x60000
981
#define RDL_RAM_BASE_4322 0x60000000
982
#define RDL_RAM_SIZE_4360  0xA0000
983
#define RDL_RAM_BASE_4360  0x60000000
984
#define RDL_RAM_SIZE_43242  0x90000
985
#define RDL_RAM_BASE_43242  0x60000000
986
#define RDL_RAM_SIZE_43143  0x70000
987
#define RDL_RAM_BASE_43143  0x60000000
988
#define RDL_RAM_SIZE_4350  0xC0000
989
#define RDL_RAM_BASE_4350  0x180800
990

991
/* generic defs for nvram "muxenab" bits
992
* Note: these differ for 4335a0. refer bcmchipc.h for specific mux options.
993
*/
994
#define MUXENAB_UART		0x00000001
995
#define MUXENAB_GPIO		0x00000002
996
#define MUXENAB_ERCX		0x00000004	/* External Radio BT coex */
997
#define MUXENAB_JTAG		0x00000008
998
#define MUXENAB_HOST_WAKE	0x00000010	/* configure GPIO for SDIO host_wake */
999
#define MUXENAB_I2S_EN		0x00000020
1000
#define MUXENAB_I2S_MASTER	0x00000040
1001
#define MUXENAB_I2S_FULL	0x00000080
1002
#define MUXENAB_SFLASH		0x00000100
1003
#define MUXENAB_RFSWCTRL0	0x00000200
1004
#define MUXENAB_RFSWCTRL1	0x00000400
1005
#define MUXENAB_RFSWCTRL2	0x00000800
1006
#define MUXENAB_SECI		0x00001000
1007
#define MUXENAB_BT_LEGACY	0x00002000
1008
#define MUXENAB_HOST_WAKE1	0x00004000	/* configure alternative GPIO for SDIO host_wake */
1009

1010
/* Boot flags */
1011
#define FLASH_KERNEL_NFLASH	0x00000001
1012
#define FLASH_BOOT_NFLASH	0x00000002
1013

1014
#endif /* _BCMDEVS_H */
1015

1016
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