Path: blob/master/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/cpufreq/mediatek,mt8196-cpufreq-hw.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: MediaTek Hybrid CPUFreq for MT8196/MT6991 series SoCs78maintainers:9- Nicolas Frattaroli <nicolas.frattaroli@collabora.com>1011description:12MT8196 uses CPUFreq management hardware that supports dynamic voltage13frequency scaling (dvfs), and can support several performance domains.1415properties:16compatible:17const: mediatek,mt8196-cpufreq-hw1819reg:20items:21- description: FDVFS control register region22- description: OPP tables and control for performance domain 023- description: OPP tables and control for performance domain 124- description: OPP tables and control for performance domain 22526"#performance-domain-cells":27const: 12829required:30- compatible31- reg32- "#performance-domain-cells"3334additionalProperties: false3536examples:37- |38cpus {39#address-cells = <1>;40#size-cells = <0>;4142cpu0: cpu@0 {43device_type = "cpu";44compatible = "arm,cortex-a720";45enable-method = "psci";46performance-domains = <&performance 0>;47reg = <0x000>;48};4950/* ... */5152cpu6: cpu@600 {53device_type = "cpu";54compatible = "arm,cortex-x4";55enable-method = "psci";56performance-domains = <&performance 1>;57reg = <0x600>;58};5960cpu7: cpu@700 {61device_type = "cpu";62compatible = "arm,cortex-x925";63enable-method = "psci";64performance-domains = <&performance 2>;65reg = <0x700>;66};67};6869/* ... */7071soc {72#address-cells = <2>;73#size-cells = <2>;7475performance: performance-controller@c2c2034 {76compatible = "mediatek,mt8196-cpufreq-hw";77reg = <0 0xc220400 0 0x20>, <0 0xc2c0f20 0 0x120>,78<0 0xc2c1040 0 0x120>, <0 0xc2c1160 0 0x120>;79#performance-domain-cells = <1>;80};81};828384