Path: blob/master/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries2%YAML 1.23---4$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator89maintainers:10- Tudor Ambarus <tudor.ambarus@linaro.org>1112properties:13compatible:14oneOf:15- const: atmel,at91sam9g46-aes16- items:17- enum:18- microchip,lan9691-aes19- microchip,sam9x7-aes20- microchip,sama7d65-aes21- const: atmel,at91sam9g46-aes2223reg:24maxItems: 12526interrupts:27maxItems: 12829clocks:30maxItems: 13132clock-names:33const: aes_clk3435dmas:36items:37- description: TX DMA Channel38- description: RX DMA Channel3940dma-names:41items:42- const: tx43- const: rx4445required:46- compatible47- reg48- interrupts49- clocks50- clock-names51- dmas52- dma-names5354additionalProperties: false5556examples:57- |58#include <dt-bindings/interrupt-controller/irq.h>59#include <dt-bindings/interrupt-controller/arm-gic.h>60#include <dt-bindings/clock/at91.h>61#include <dt-bindings/dma/at91.h>6263aes: crypto@e1810000 {64compatible = "atmel,at91sam9g46-aes";65reg = <0xe1810000 0x100>;66interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;67clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;68clock-names = "aes_clk";69dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,70<&dma0 AT91_XDMAC_DT_PERID(2)>;71dma-names = "tx", "rx";72};737475