Path: blob/master/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: ITE IT6263 LVDS to HDMI converter78maintainers:9- Liu Ying <victor.liu@nxp.com>1011description: |12The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS13to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,14the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.15The built-in LVDS receiver can support single-link and dual-link LVDS inputs,16and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP171.2 and backward compatible with DVI 1.0 specification.1819The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,20with sampling rate up to 192KHz and sample size up to 24 bits. In addition,21an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.2223The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is24provided by the IT6263 in two interfaces: the four I2S input ports or the25S/PDIF input port. With both interfaces the highest possible HBR frame rate26is supported at up to 768KHz.2728allOf:29- $ref: /schemas/display/lvds-dual-ports.yaml#30- $ref: /schemas/sound/dai-common.yaml#3132properties:33compatible:34const: ite,it62633536reg:37maxItems: 13839clocks:40maxItems: 141description: audio master clock4243clock-names:44const: mclk4546data-mapping:47enum:48- jeida-1849- jeida-2450- jeida-3051- vesa-2452- vesa-305354reset-gpios:55maxItems: 15657ivdd-supply:58description: 1.8V digital logic power5960ovdd-supply:61description: 3.3V I/O pin power6263txavcc18-supply:64description: 1.8V HDMI analog frontend power6566txavcc33-supply:67description: 3.3V HDMI analog frontend power6869pvcc1-supply:70description: 1.8V HDMI frontend core PLL power7172pvcc2-supply:73description: 1.8V HDMI frontend filter PLL power7475avcc-supply:76description: 3.3V LVDS frontend power7778anvdd-supply:79description: 1.8V LVDS frontend analog power8081apvdd-supply:82description: 1.8V LVDS frontend PLL power8384"#sound-dai-cells":85const: 08687ite,i2s-audio-fifo-sources:88$ref: /schemas/types.yaml#/definitions/uint32-array89minItems: 190maxItems: 491items:92enum: [0, 1, 2, 3]93description:94Each array element indicates the pin number of an I2S serial data input95line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.9697ite,rl-channel-swap-audio-sources:98$ref: /schemas/types.yaml#/definitions/uint32-array99minItems: 1100maxItems: 4101uniqueItems: true102items:103enum: [0, 1, 2, 3]104description:105Each array element indicates an audio source whose right channel and left106channel are swapped by this converter. For I2S, the element is the pin107number of an I2S serial data input line. For S/PDIF, the element is always1080.109110ports:111$ref: /schemas/graph.yaml#/properties/ports112113properties:114port@0: true115116port@1:117oneOf:118- required: [dual-lvds-odd-pixels]119- required: [dual-lvds-even-pixels]120121port@2:122$ref: /schemas/graph.yaml#/properties/port123description: video port for the HDMI output124125port@3:126$ref: /schemas/graph.yaml#/properties/port127description: sound input port128129required:130- port@0131- port@2132133required:134- compatible135- reg136- data-mapping137- ivdd-supply138- ovdd-supply139- txavcc18-supply140- txavcc33-supply141- pvcc1-supply142- pvcc2-supply143- avcc-supply144- anvdd-supply145- apvdd-supply146147unevaluatedProperties: false148149examples:150- |151/* single-link LVDS input */152#include <dt-bindings/gpio/gpio.h>153154i2c {155#address-cells = <1>;156#size-cells = <0>;157158hdmi@4c {159compatible = "ite,it6263";160reg = <0x4c>;161data-mapping = "jeida-24";162reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;163ivdd-supply = <®_buck5>;164ovdd-supply = <®_vext_3v3>;165txavcc18-supply = <®_buck5>;166txavcc33-supply = <®_vext_3v3>;167pvcc1-supply = <®_buck5>;168pvcc2-supply = <®_buck5>;169avcc-supply = <®_vext_3v3>;170anvdd-supply = <®_buck5>;171apvdd-supply = <®_buck5>;172173ports {174#address-cells = <1>;175#size-cells = <0>;176177port@0 {178reg = <0>;179180it6263_lvds_link1: endpoint {181remote-endpoint = <&ldb_lvds_ch0>;182};183};184185port@2 {186reg = <2>;187188it6263_out: endpoint {189remote-endpoint = <&hdmi_in>;190};191};192};193};194};195196- |197/* dual-link LVDS input */198#include <dt-bindings/gpio/gpio.h>199200i2c {201#address-cells = <1>;202#size-cells = <0>;203204hdmi@4c {205compatible = "ite,it6263";206reg = <0x4c>;207data-mapping = "jeida-24";208reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;209ivdd-supply = <®_buck5>;210ovdd-supply = <®_vext_3v3>;211txavcc18-supply = <®_buck5>;212txavcc33-supply = <®_vext_3v3>;213pvcc1-supply = <®_buck5>;214pvcc2-supply = <®_buck5>;215avcc-supply = <®_vext_3v3>;216anvdd-supply = <®_buck5>;217apvdd-supply = <®_buck5>;218219ports {220#address-cells = <1>;221#size-cells = <0>;222223port@0 {224reg = <0>;225dual-lvds-odd-pixels;226227it6263_lvds_link1_dual: endpoint {228remote-endpoint = <&ldb_lvds_ch0>;229};230};231232port@1 {233reg = <1>;234dual-lvds-even-pixels;235236it6263_lvds_link2_dual: endpoint {237remote-endpoint = <&ldb_lvds_ch1>;238};239};240241port@2 {242reg = <2>;243244it6263_out_dual: endpoint {245remote-endpoint = <&hdmi_in>;246};247};248};249};250};251252253