Path: blob/master/Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/edac/apm,xgene-edac.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: APM X-Gene SoC EDAC78maintainers:9- Khuong Dinh <khuong@os.amperecomputing.com>1011description: >12EDAC node is defined to describe on-chip error detection and correction.1314The following error types are supported:1516memory controller - Memory controller17PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache18L3 - L3 cache controller19SoC - SoC IPs such as Ethernet, SATA, etc2021properties:22compatible:23const: apm,xgene-edac2425reg:26items:27- description: CPU bus (PCP) resource2829'#address-cells':30const: 23132'#size-cells':33const: 23435ranges: true3637interrupts:38description: Interrupt-specifier for MCU, PMD, L3, or SoC error IRQ(s).39items:40- description: MCU error IRQ41- description: PMD error IRQ42- description: L3 error IRQ43- description: SoC error IRQ44minItems: 14546regmap-csw:47description: Regmap of the CPU switch fabric (CSW) resource.48$ref: /schemas/types.yaml#/definitions/phandle4950regmap-mcba:51description: Regmap of the MCB-A (memory bridge) resource.52$ref: /schemas/types.yaml#/definitions/phandle5354regmap-mcbb:55description: Regmap of the MCB-B (memory bridge) resource.56$ref: /schemas/types.yaml#/definitions/phandle5758regmap-efuse:59description: Regmap of the PMD efuse resource.60$ref: /schemas/types.yaml#/definitions/phandle6162regmap-rb:63description: Regmap of the register bus resource (optional for compatibility).64$ref: /schemas/types.yaml#/definitions/phandle6566required:67- compatible68- regmap-csw69- regmap-mcba70- regmap-mcbb71- regmap-efuse72- reg73- interrupts7475# Child-node bindings76patternProperties:77'^edacmc@':78description: Memory controller subnode79type: object80additionalProperties: false8182properties:83compatible:84const: apm,xgene-edac-mc8586reg:87maxItems: 18889memory-controller:90description: Instance number of the memory controller.91$ref: /schemas/types.yaml#/definitions/uint3292maximum: 39394required:95- compatible96- reg97- memory-controller9899100'^edacpmd@':101description: PMD subnode102type: object103additionalProperties: false104105properties:106compatible:107const: apm,xgene-edac-pmd108109reg:110maxItems: 1111112pmd-controller:113description: Instance number of the PMD controller.114$ref: /schemas/types.yaml#/definitions/uint32115maximum: 3116117required:118- compatible119- reg120- pmd-controller121122'^edacl3@':123description: L3 subnode124type: object125additionalProperties: false126127properties:128compatible:129enum:130- apm,xgene-edac-l3131- apm,xgene-edac-l3-v2132133reg:134maxItems: 1135136required:137- compatible138- reg139140'^edacsoc@':141description: SoC subnode142type: object143additionalProperties: false144145properties:146compatible:147enum:148- apm,xgene-edac-soc149- apm,xgene-edac-soc-v1150151reg:152maxItems: 1153154required:155- compatible156- reg157158additionalProperties: false159160examples:161- |162bus {163#address-cells = <2>;164#size-cells = <2>;165166edac@78800000 {167compatible = "apm,xgene-edac";168reg = <0x0 0x78800000 0x0 0x100>;169#address-cells = <2>;170#size-cells = <2>;171ranges;172interrupts = <0x0 0x20 0x4>, <0x0 0x21 0x4>, <0x0 0x27 0x4>;173174regmap-csw = <&csw>;175regmap-mcba = <&mcba>;176regmap-mcbb = <&mcbb>;177regmap-efuse = <&efuse>;178regmap-rb = <&rb>;179180edacmc@7e800000 {181compatible = "apm,xgene-edac-mc";182reg = <0x0 0x7e800000 0x0 0x1000>;183memory-controller = <0>;184};185186edacpmd@7c000000 {187compatible = "apm,xgene-edac-pmd";188reg = <0x0 0x7c000000 0x0 0x200000>;189pmd-controller = <0>;190};191192edacl3@7e600000 {193compatible = "apm,xgene-edac-l3";194reg = <0x0 0x7e600000 0x0 0x1000>;195};196197edacsoc@7e930000 {198compatible = "apm,xgene-edac-soc-v1";199reg = <0x0 0x7e930000 0x0 0x1000>;200};201};202};203204205