Path: blob/master/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Generic 8-bit shift register78description: |9NOTE: These chips nominally don't have a chip select pin. They do however10have a rising-edge triggered latch clock (or storage register clock) pin,11which behaves like an active-low chip select.1213After the bits are shifted into the shift register, CS# is driven high, which14the 74HC595 sees as a rising edge on the latch clock that results in a15transfer of the bits from the shift register to the storage register and thus16to the output pins.17_ _ _ _18shift clock ____| |_| |_..._| |_| |_________1920latch clock * trigger21___ ________22chip select# |___________________|2324maintainers:25- Maxime Ripard <mripard@kernel.org>2627properties:28compatible:29enum:30- fairchild,74hc59531- nxp,74lvc5943233reg:34maxItems: 13536gpio-controller: true3738'#gpio-cells':39description:40The second cell is only used to specify the GPIO polarity.41const: 24243registers-number:44$ref: /schemas/types.yaml#/definitions/uint3245description: Number of daisy-chained shift registers4647enable-gpios:48description: GPIO connected to the OE (Output Enable) pin.49maxItems: 15051patternProperties:52"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":53type: object54required:55- gpio-hog5657required:58- compatible59- reg60- gpio-controller61- '#gpio-cells'62- registers-number6364allOf:65- $ref: /schemas/spi/spi-peripheral-props.yaml#6667unevaluatedProperties: false6869examples:70- |71spi {72#address-cells = <1>;73#size-cells = <0>;7475gpio5@0 {76compatible = "fairchild,74hc595";77reg = <0>;78gpio-controller;79#gpio-cells = <2>;80registers-number = <4>;81spi-max-frequency = <100000>;82};83};848586