Path: blob/master/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
29282 views
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/gpu/nvidia,gk20a.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: NVIDIA Tegra Graphics Processing Units78maintainers:9- Alexandre Courbot <acourbot@nvidia.com>10- Jon Hunter <jonathanh@nvidia.com>11- Thierry Reding <treding@nvidia.com>1213properties:14compatible:15enum:16- nvidia,gk20a17- nvidia,gm20b18- nvidia,gp10b19- nvidia,gv11b2021reg:22items:23- description: Bar0 register window24- description: Bar1 register window2526interrupts:27items:28- description: Stall interrupt29- description: Nonstall interrupt3031interrupt-names:32items:33- const: stall34- const: nonstall3536vdd-supply:37description:38Regulator for GPU supply voltage3940clocks:41minItems: 242items:43- description: GPU clock44- description: Power clock45- description: Reference or fuse clock4647clock-names:48minItems: 249items:50- const: gpu51- const: pwr52- enum: [ ref, fuse ]5354resets:55maxItems: 15657reset-names:58items:59- const: gpu6061power-domains:62maxItems: 16364interconnects:65minItems: 466maxItems: 126768interconnect-names:69minItems: 470maxItems: 127172iommus:73maxItems: 17475dma-coherent: true7677required:78- compatible79- reg80- interrupts81- interrupt-names82- clocks83- clock-names84- resets85- reset-names8687allOf:88- if:89properties:90compatible:91contains:92enum:93- nvidia,gp10b94- nvidia,gv11b95then:96required:97- power-domains98else:99properties:100interconnects: false101interconnect-names: false102103required:104- vdd-supply105- if:106properties:107compatible:108contains:109enum:110- nvidia,gp10b111then:112properties:113interconnects:114maxItems: 4115116interconnect-names:117items:118- const: dma-mem119- const: write-0120- const: read-1121- const: write-1122- if:123properties:124compatible:125contains:126enum:127- nvidia,gv11b128then:129properties:130interconnects:131minItems: 12132133interconnect-names:134items:135- const: dma-mem136- const: read-0-hp137- const: write-0138- const: read-1139- const: read-1-hp140- const: write-1141- const: read-2142- const: read-2-hp143- const: write-2144- const: read-3145- const: read-3-hp146- const: write-3147148additionalProperties: false149150examples:151- |152#include <dt-bindings/interrupt-controller/arm-gic.h>153#include <dt-bindings/clock/tegra124-car-common.h>154#include <dt-bindings/memory/tegra124-mc.h>155156gpu@57000000 {157compatible = "nvidia,gk20a";158reg = <0x57000000 0x01000000>,159<0x58000000 0x01000000>;160interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,161<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;162interrupt-names = "stall", "nonstall";163vdd-supply = <&vdd_gpu>;164clocks = <&tegra_car TEGRA124_CLK_GPU>,165<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;166clock-names = "gpu", "pwr";167resets = <&tegra_car 184>;168reset-names = "gpu";169iommus = <&mc TEGRA_SWGROUP_GPU>;170};171172173