adi,i3c-master.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i3c/adi,i3c-master.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices I3C Controller

description:
  FPGA-based I3C controller designed to interface with I3C and I2C peripherals,
  implementing a subset of the I3C-basic specification. The IP core is tested
  on arm, microblaze, and arm64 architectures.

  https://analogdevicesinc.github.io/hdl/library/i3c_controller

maintainers:
  - Jorge Marques <[e-mail]>

properties:
  compatible:
    const: adi,i3c-master-v1

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: The AXI interconnect clock, drives the register map.
      - description:
          The secondary clock, drives the internal logic asynchronously to the
          register map. The presence of this entry states that the IP Core was
          synthesized with a second clock input, and the absence of this entry
          indicates a topology where a single clock input drives all the
          internal logic.

  clock-names:
    minItems: 1
    items:
      - const: axi
      - const: i3c

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts

allOf:
  - $ref: i3c.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    i3c@44a00000 {
        compatible = "adi,i3c-master-v1";
        reg = <0x44a00000 0x1000>;
        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clkc 15>, <&clkc 15>;
        clock-names = "axi", "i3c";
        #address-cells = <3>;
        #size-cells = <0>;

        /* I3C and I2C devices */
    };