Path: blob/master/arch/arm/boot/dts/samsung/exynos-pinctrl.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* Samsung Exynos DTS pinctrl constants3*4* Copyright (c) 2016 Samsung Electronics Co., Ltd.5* http://www.samsung.com6* Copyright (c) 2022 Linaro Ltd7* Author: Krzysztof Kozlowski <[email protected]>8*/910#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__11#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__1213#define EXYNOS_PIN_PULL_NONE 014#define EXYNOS_PIN_PULL_DOWN 115#define EXYNOS_PIN_PULL_UP 31617/* Pin function in power down mode */18#define EXYNOS_PIN_PDN_OUT0 019#define EXYNOS_PIN_PDN_OUT1 120#define EXYNOS_PIN_PDN_INPUT 221#define EXYNOS_PIN_PDN_PREV 32223/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */24#define EXYNOS4_PIN_DRV_LV1 025#define EXYNOS4_PIN_DRV_LV2 226#define EXYNOS4_PIN_DRV_LV3 127#define EXYNOS4_PIN_DRV_LV4 32829/* Drive strengths for Exynos5260 */30#define EXYNOS5260_PIN_DRV_LV1 031#define EXYNOS5260_PIN_DRV_LV2 132#define EXYNOS5260_PIN_DRV_LV4 233#define EXYNOS5260_PIN_DRV_LV6 33435/*36* Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except37* GPIO_HSI block)38*/39#define EXYNOS5420_PIN_DRV_LV1 040#define EXYNOS5420_PIN_DRV_LV2 141#define EXYNOS5420_PIN_DRV_LV3 242#define EXYNOS5420_PIN_DRV_LV4 34344#define EXYNOS_PIN_FUNC_INPUT 045#define EXYNOS_PIN_FUNC_OUTPUT 146#define EXYNOS_PIN_FUNC_2 247#define EXYNOS_PIN_FUNC_3 348#define EXYNOS_PIN_FUNC_4 449#define EXYNOS_PIN_FUNC_5 550#define EXYNOS_PIN_FUNC_6 651#define EXYNOS_PIN_FUNC_EINT 0xf52#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT5354#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */555657