Path: blob/master/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */1/*2* Axis ARTPEC-8 SoC device tree pinctrl constants3*4* Copyright (c) 2025 Samsung Electronics Co., Ltd.5* https://www.samsung.com6* Copyright (c) 2025 Axis Communications AB.7* https://www.axis.com8*/910#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__11#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__1213#define ARTPEC_PIN_PULL_NONE 014#define ARTPEC_PIN_PULL_DOWN 115#define ARTPEC_PIN_PULL_UP 31617#define ARTPEC_PIN_FUNC_INPUT 018#define ARTPEC_PIN_FUNC_OUTPUT 119#define ARTPEC_PIN_FUNC_2 220#define ARTPEC_PIN_FUNC_3 321#define ARTPEC_PIN_FUNC_4 422#define ARTPEC_PIN_FUNC_5 523#define ARTPEC_PIN_FUNC_6 624#define ARTPEC_PIN_FUNC_EINT 0xf25#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT2627/* Drive strength for ARTPEC */28#define ARTPEC_PIN_DRV_SR1 0x829#define ARTPEC_PIN_DRV_SR2 0x930#define ARTPEC_PIN_DRV_SR3 0xa31#define ARTPEC_PIN_DRV_SR4 0xb32#define ARTPEC_PIN_DRV_SR5 0xc33#define ARTPEC_PIN_DRV_SR6 0xd3435#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */363738