Path: blob/master/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2025 Microchip Technology Inc */
/ {
core_pwm0: pwm@40000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x40000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
#pwm-cells = <3>;
clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
status = "disabled";
};
i2c2: i2c@40000200 {
compatible = "microchip,corei2c-rtl-v7";
reg = <0x0 0x40000200 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
interrupt-parent = <&plic>;
interrupts = <122>;
clock-frequency = <100000>;
status = "disabled";
};
ihc: mailbox {
compatible = "microchip,sbi-ipc";
interrupt-parent = <&plic>;
interrupts = <180>, <179>, <178>, <177>;
interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
#mbox-cells = <1>;
status = "disabled";
};
mailbox@50000000 {
compatible = "microchip,miv-ihc-rtl-v2";
reg = <0x0 0x50000000 0x0 0x1c000>;
interrupt-parent = <&plic>;
interrupts = <180>, <179>, <178>, <177>;
interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
#mbox-cells = <1>;
microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
status = "disabled";
};
refclk_ccc: clock-cccref {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
&ccc_sw {
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
<&refclk_ccc>, <&refclk_ccc>;
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
"dll0_ref", "dll1_ref";
status = "okay";
};