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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/arch/x86/include/asm/apic.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ASM_X86_APIC_H
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#define _ASM_X86_APIC_H
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#include <linux/cpumask.h>
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#include <linux/static_call.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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#include <asm/apicdef.h>
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#include <linux/atomic.h>
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#include <asm/fixmap.h>
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#include <asm/mpspec.h>
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#include <asm/msr.h>
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#include <asm/hardirq.h>
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#include <asm/io.h>
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#include <asm/posted_intr.h>
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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/* Macros for apic_extnmi which controls external NMI masking */
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#define APIC_EXTNMI_BSP 0 /* Default */
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#define APIC_EXTNMI_ALL 1
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#define APIC_EXTNMI_NONE 2
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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/*
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* Define the default level of output to be very little This can be turned
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* up by using apic=verbose for more information and apic=debug for _lots_
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* of information. apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) \
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do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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#define apic_pr_verbose(s, a...) apic_printk(APIC_VERBOSE, KERN_INFO s, ##a)
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#define apic_pr_debug(s, a...) apic_printk(APIC_DEBUG, KERN_DEBUG s, ##a)
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#define apic_pr_debug_cont(s, a...) apic_printk(APIC_DEBUG, KERN_CONT s, ##a)
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/* Unconditional debug prints for code which is guarded by apic_verbosity already */
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#define apic_dbg(s, a...) printk(KERN_DEBUG s, ##a)
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
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extern void x86_32_probe_apic(void);
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#else
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static inline void x86_32_probe_apic(void) { }
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#endif
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extern u32 cpuid_to_apicid[];
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#define CPU_ACPIID_INVALID U32_MAX
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#ifdef CONFIG_X86_LOCAL_APIC
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extern int apic_verbosity;
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extern int local_apic_timer_c2_ok;
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extern bool apic_is_disabled;
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extern unsigned int lapic_timer_period;
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extern enum apic_intr_mode_id apic_intr_mode;
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enum apic_intr_mode_id {
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APIC_PIC,
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APIC_VIRTUAL_WIRE,
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APIC_VIRTUAL_WIRE_NO_CONFIG,
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APIC_SYMMETRIC_IO,
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APIC_SYMMETRIC_IO_NO_ROUTING
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};
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/*
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* With 82489DX we can't rely on apic feature bit
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* retrieved via cpuid but still have to deal with
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* such an apic chip so we assume that SMP configuration
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* is found from MP table (64bit case uses ACPI mostly
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* which set smp presence flag as well so we are safe
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* to use this helper too).
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*/
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static inline bool apic_from_smp_config(void)
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{
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return smp_found_config && !apic_is_disabled;
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}
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#endif
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static inline void native_apic_mem_write(u32 reg, u32 v)
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{
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volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
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alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,
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ASM_OUTPUT("=r" (v), "=m" (*addr)),
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ASM_INPUT("0" (v), "m" (*addr)));
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}
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static inline u32 native_apic_mem_read(u32 reg)
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{
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return readl((void __iomem *)(APIC_BASE + reg));
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}
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static inline void native_apic_mem_eoi(void)
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{
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native_apic_mem_write(APIC_EOI, APIC_EOI_ACK);
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}
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extern void native_apic_icr_write(u32 low, u32 id);
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extern u64 native_apic_icr_read(void);
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static inline bool apic_is_x2apic_enabled(void)
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{
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u64 msr;
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if (rdmsrq_safe(MSR_IA32_APICBASE, &msr))
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return false;
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return msr & X2APIC_ENABLE;
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}
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extern void enable_IR_x2apic(void);
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void apic_soft_disable(void);
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extern void lapic_shutdown(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void apic_intr_mode_select(void);
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extern void apic_intr_mode_init(void);
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extern void init_apic_mappings(void);
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void register_lapic_address(unsigned long address);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern void lapic_update_tsc_freq(void);
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#ifdef CONFIG_X86_64
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static inline bool apic_force_enable(unsigned long addr)
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{
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return false;
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}
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#else
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extern bool apic_force_enable(unsigned long addr);
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#endif
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extern void apic_ap_setup(void);
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/*
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* On 32bit this is mach-xxx local
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*/
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#ifdef CONFIG_X86_64
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extern int apic_is_clustered_box(void);
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#else
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static inline int apic_is_clustered_box(void)
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{
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return 0;
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}
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#endif
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extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
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extern void lapic_assign_system_vectors(void);
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extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
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extern void lapic_update_legacy_vectors(void);
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extern void lapic_online(void);
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extern void lapic_offline(void);
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extern bool apic_needs_pit(void);
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extern void apic_send_IPI_allbutself(unsigned int vector);
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extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present);
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extern void topology_register_boot_apic(u32 apic_id);
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extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id);
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extern void topology_hotunplug_apic(unsigned int cpu);
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extern void topology_apply_cmdline_limits_early(void);
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extern void topology_init_possible_cpus(void);
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extern void topology_reset_possible_cpus_up(void);
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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static inline void init_apic_mappings(void) { }
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static inline void disable_local_APIC(void) { }
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# define setup_boot_APIC_clock x86_init_noop
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# define setup_secondary_APIC_clock x86_init_noop
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static inline void lapic_update_tsc_freq(void) { }
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static inline void init_bsp_APIC(void) { }
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static inline void apic_intr_mode_select(void) { }
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static inline void apic_intr_mode_init(void) { }
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static inline void lapic_assign_system_vectors(void) { }
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static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
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static inline bool apic_needs_pit(void) { return true; }
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static inline void topology_apply_cmdline_limits_early(void) { }
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static inline void topology_init_possible_cpus(void) { }
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_X86_X2APIC
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static inline void native_apic_msr_write(u32 reg, u32 v)
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{
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if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
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reg == APIC_LVR)
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return;
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wrmsrq(APIC_BASE_MSR + (reg >> 4), v);
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}
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static inline void native_apic_msr_eoi(void)
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{
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native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK);
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}
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static inline u32 native_apic_msr_read(u32 reg)
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{
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u64 msr;
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if (reg == APIC_DFR)
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return -1;
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rdmsrq(APIC_BASE_MSR + (reg >> 4), msr);
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return (u32)msr;
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}
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static inline void native_x2apic_icr_write(u32 low, u32 id)
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{
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wrmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
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}
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static inline u64 native_x2apic_icr_read(void)
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{
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unsigned long val;
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rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val);
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return val;
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}
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extern int x2apic_mode;
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extern int x2apic_phys;
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extern void __init x2apic_set_max_apicid(u32 apicid);
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extern void x2apic_setup(void);
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static inline int x2apic_enabled(void)
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{
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return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
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}
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#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
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#else /* !CONFIG_X86_X2APIC */
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static inline void x2apic_setup(void) { }
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static inline int x2apic_enabled(void) { return 0; }
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static inline u32 native_apic_msr_read(u32 reg) { BUG(); }
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#define x2apic_mode (0)
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#define x2apic_supported() (0)
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#endif /* !CONFIG_X86_X2APIC */
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extern void __init check_x2apic(void);
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struct irq_data;
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/*
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* Copyright 2004 James Cleverdon, IBM.
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*
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* Generic APIC sub-arch data struct.
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*
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* Hacked for x86-64 by James Cleverdon from i386 architecture code by
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* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
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* James Cleverdon.
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*/
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struct apic {
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/* Hotpath functions first */
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void (*eoi)(void);
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void (*native_eoi)(void);
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void (*write)(u32 reg, u32 v);
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u32 (*read)(u32 reg);
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/* IPI related functions */
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void (*wait_icr_idle)(void);
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u32 (*safe_wait_icr_idle)(void);
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void (*send_IPI)(int cpu, int vector);
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void (*send_IPI_mask)(const struct cpumask *mask, int vector);
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void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
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void (*send_IPI_allbutself)(int vector);
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void (*send_IPI_all)(int vector);
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void (*send_IPI_self)(int vector);
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u32 disable_esr : 1,
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dest_mode_logical : 1,
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x2apic_set_max_apicid : 1,
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nmi_to_offline_cpu : 1;
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u32 (*calc_dest_apicid)(unsigned int cpu);
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/* ICR related functions */
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u64 (*icr_read)(void);
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void (*icr_write)(u32 low, u32 high);
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/* The limit of the APIC ID space. */
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u32 max_apic_id;
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/* Probe, setup and smpboot functions */
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int (*probe)(void);
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void (*setup)(void);
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void (*teardown)(void);
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int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
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void (*init_apic_ldr)(void);
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u32 (*cpu_present_to_apicid)(int mps_cpu);
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u32 (*get_apic_id)(u32 id);
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/* wakeup_secondary_cpu */
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int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip, unsigned int cpu);
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/* wakeup secondary CPU using 64-bit wakeup point */
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int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsigned int cpu);
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void (*update_vector)(unsigned int cpu, unsigned int vector, bool set);
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char *name;
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};
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struct apic_override {
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void (*eoi)(void);
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void (*native_eoi)(void);
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void (*write)(u32 reg, u32 v);
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u32 (*read)(u32 reg);
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void (*send_IPI)(int cpu, int vector);
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void (*send_IPI_mask)(const struct cpumask *mask, int vector);
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void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
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void (*send_IPI_allbutself)(int vector);
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void (*send_IPI_all)(int vector);
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void (*send_IPI_self)(int vector);
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u64 (*icr_read)(void);
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void (*icr_write)(u32 low, u32 high);
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int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip, unsigned int cpu);
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int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsigned int cpu);
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};
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/*
345
* Pointer to the local APIC driver in use on this system (there's
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* always just one such driver in use - the kernel decides via an
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* early probing process which one it picks - and then sticks to it):
348
*/
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extern struct apic *apic;
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/*
352
* APIC drivers are probed based on how they are listed in the .apicdrivers
353
* section. So the order is important and enforced by the ordering
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* of different apic driver files in the Makefile.
355
*/
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#define apic_driver(sym) \
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static const struct apic *__apicdrivers_##sym __used \
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__aligned(sizeof(struct apic *)) \
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__section(".apicdrivers") = { &sym }
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extern struct apic *__apicdrivers[], *__apicdrivers_end[];
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/*
364
* APIC functionality to boot other CPUs - only used on SMP:
365
*/
366
#ifdef CONFIG_SMP
367
extern int lapic_can_unplug_cpu(void);
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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extern struct apic_override __x86_apic_override;
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void __init apic_setup_apic_calls(void);
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void __init apic_install_driver(struct apic *driver);
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#define apic_update_callback(_callback, _fn) { \
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__x86_apic_override._callback = _fn; \
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apic->_callback = _fn; \
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static_call_update(apic_call_##_callback, _fn); \
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pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \
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}
382
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#define DECLARE_APIC_CALL(__cb) \
384
DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb)
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DECLARE_APIC_CALL(eoi);
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DECLARE_APIC_CALL(native_eoi);
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DECLARE_APIC_CALL(icr_read);
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DECLARE_APIC_CALL(icr_write);
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DECLARE_APIC_CALL(read);
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DECLARE_APIC_CALL(send_IPI);
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DECLARE_APIC_CALL(send_IPI_mask);
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DECLARE_APIC_CALL(send_IPI_mask_allbutself);
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DECLARE_APIC_CALL(send_IPI_allbutself);
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DECLARE_APIC_CALL(send_IPI_all);
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DECLARE_APIC_CALL(send_IPI_self);
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DECLARE_APIC_CALL(wait_icr_idle);
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DECLARE_APIC_CALL(wakeup_secondary_cpu);
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DECLARE_APIC_CALL(wakeup_secondary_cpu_64);
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DECLARE_APIC_CALL(write);
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static __always_inline u32 apic_read(u32 reg)
403
{
404
return static_call(apic_call_read)(reg);
405
}
406
407
static __always_inline void apic_write(u32 reg, u32 val)
408
{
409
static_call(apic_call_write)(reg, val);
410
}
411
412
static __always_inline void apic_eoi(void)
413
{
414
static_call(apic_call_eoi)();
415
}
416
417
static __always_inline void apic_native_eoi(void)
418
{
419
static_call(apic_call_native_eoi)();
420
}
421
422
static __always_inline u64 apic_icr_read(void)
423
{
424
return static_call(apic_call_icr_read)();
425
}
426
427
static __always_inline void apic_icr_write(u32 low, u32 high)
428
{
429
static_call(apic_call_icr_write)(low, high);
430
}
431
432
static __always_inline void __apic_send_IPI(int cpu, int vector)
433
{
434
static_call(apic_call_send_IPI)(cpu, vector);
435
}
436
437
static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector)
438
{
439
static_call_mod(apic_call_send_IPI_mask)(mask, vector);
440
}
441
442
static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
443
{
444
static_call(apic_call_send_IPI_mask_allbutself)(mask, vector);
445
}
446
447
static __always_inline void __apic_send_IPI_allbutself(int vector)
448
{
449
static_call(apic_call_send_IPI_allbutself)(vector);
450
}
451
452
static __always_inline void __apic_send_IPI_all(int vector)
453
{
454
static_call(apic_call_send_IPI_all)(vector);
455
}
456
457
static __always_inline void __apic_send_IPI_self(int vector)
458
{
459
static_call_mod(apic_call_send_IPI_self)(vector);
460
}
461
462
static __always_inline void apic_wait_icr_idle(void)
463
{
464
static_call_cond(apic_call_wait_icr_idle)();
465
}
466
467
static __always_inline u32 safe_apic_wait_icr_idle(void)
468
{
469
return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
470
}
471
472
static __always_inline bool apic_id_valid(u32 apic_id)
473
{
474
return apic_id <= apic->max_apic_id;
475
}
476
477
static __always_inline void apic_update_vector(unsigned int cpu, unsigned int vector, bool set)
478
{
479
if (apic->update_vector)
480
apic->update_vector(cpu, vector, set);
481
}
482
483
#else /* CONFIG_X86_LOCAL_APIC */
484
485
static inline u32 apic_read(u32 reg) { return 0; }
486
static inline void apic_write(u32 reg, u32 val) { }
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static inline void apic_eoi(void) { }
488
static inline u64 apic_icr_read(void) { return 0; }
489
static inline void apic_icr_write(u32 low, u32 high) { }
490
static inline void apic_wait_icr_idle(void) { }
491
static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
492
static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); }
493
static inline void apic_setup_apic_calls(void) { }
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static inline void apic_update_vector(unsigned int cpu, unsigned int vector, bool set) { }
495
496
#define apic_update_callback(_callback, _fn) do { } while (0)
497
498
#endif /* CONFIG_X86_LOCAL_APIC */
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extern void apic_ack_irq(struct irq_data *data);
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#define APIC_VECTOR_TO_BIT_NUMBER(v) ((unsigned int)(v) % 32)
503
#define APIC_VECTOR_TO_REG_OFFSET(v) ((unsigned int)(v) / 32 * 0x10)
504
505
static inline bool lapic_vector_set_in_irr(unsigned int vector)
506
{
507
u32 irr = apic_read(APIC_IRR + APIC_VECTOR_TO_REG_OFFSET(vector));
508
509
return !!(irr & (1U << APIC_VECTOR_TO_BIT_NUMBER(vector)));
510
}
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512
static inline bool is_vector_pending(unsigned int vector)
513
{
514
return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector);
515
}
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#define MAX_APIC_VECTOR 256
518
#define APIC_VECTORS_PER_REG 32
519
520
/*
521
* Vector states are maintained by APIC in 32-bit registers that are
522
* 16 bytes aligned. The status of each vector is kept in a single
523
* bit.
524
*/
525
static inline int apic_find_highest_vector(void *bitmap)
526
{
527
int vec;
528
u32 *reg;
529
530
for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; vec >= 0; vec -= APIC_VECTORS_PER_REG) {
531
reg = bitmap + APIC_VECTOR_TO_REG_OFFSET(vec);
532
if (*reg)
533
return __fls(*reg) + vec;
534
}
535
536
return -1;
537
}
538
539
static inline u32 apic_get_reg(void *regs, int reg)
540
{
541
return *((u32 *) (regs + reg));
542
}
543
544
static inline void apic_set_reg(void *regs, int reg, u32 val)
545
{
546
*((u32 *) (regs + reg)) = val;
547
}
548
549
static __always_inline u64 apic_get_reg64(void *regs, int reg)
550
{
551
BUILD_BUG_ON(reg != APIC_ICR);
552
return *((u64 *) (regs + reg));
553
}
554
555
static __always_inline void apic_set_reg64(void *regs, int reg, u64 val)
556
{
557
BUILD_BUG_ON(reg != APIC_ICR);
558
*((u64 *) (regs + reg)) = val;
559
}
560
561
static inline void apic_clear_vector(int vec, void *bitmap)
562
{
563
clear_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec));
564
}
565
566
static inline void apic_set_vector(int vec, void *bitmap)
567
{
568
set_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec));
569
}
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static inline int apic_test_vector(int vec, void *bitmap)
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{
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return test_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec));
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}
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/*
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* Warm reset vector position:
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*/
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#define TRAMPOLINE_PHYS_LOW 0x467
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#define TRAMPOLINE_PHYS_HIGH 0x469
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/smp.h>
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extern struct apic apic_noop;
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static inline u32 read_apic_id(void)
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{
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u32 reg = apic_read(APIC_ID);
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return apic->get_apic_id(reg);
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}
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#ifdef CONFIG_X86_64
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typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
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extern int default_acpi_madt_oem_check(char *, char *);
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extern void x86_64_probe_apic(void);
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#else
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static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; }
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static inline void x86_64_probe_apic(void) { }
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#endif
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extern u32 apic_default_calc_apicid(unsigned int cpu);
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extern u32 apic_flat_calc_apicid(unsigned int cpu);
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extern u32 default_cpu_present_to_apicid(int mps_cpu);
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void apic_send_nmi_to_offline_cpu(unsigned int cpu);
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#else /* CONFIG_X86_LOCAL_APIC */
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static inline u32 read_apic_id(void) { return 0; }
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_SMP
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void apic_smt_update(void);
619
#else
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static inline void apic_smt_update(void) { }
621
#endif
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623
struct msi_msg;
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struct irq_cfg;
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extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
627
bool dmar);
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extern void ioapic_zap_locks(void);
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631
#endif /* _ASM_X86_APIC_H */
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