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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/drivers/char/hw_random/airoha-trng.c
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2024 Christian Marangi */
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/hw_random.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/platform_device.h>
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#define TRNG_IP_RDY 0x800
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#define CNT_TRANS GENMASK(15, 8)
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#define SAMPLE_RDY BIT(0)
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#define TRNG_NS_SEK_AND_DAT_EN 0x804
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#define RNG_EN BIT(31) /* referenced as ring_en */
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#define RAW_DATA_EN BIT(16)
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#define TRNG_HEALTH_TEST_SW_RST 0x808
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#define SW_RST BIT(0) /* Active High */
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#define TRNG_INTR_EN 0x818
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#define INTR_MASK BIT(16)
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#define CONTINUOUS_HEALTH_INITR_EN BIT(2)
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#define SW_STARTUP_INITR_EN BIT(1)
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#define RST_STARTUP_INITR_EN BIT(0)
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/* Notice that Health Test are done only out of Reset and with RNG_EN */
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#define TRNG_HEALTH_TEST_STATUS 0x824
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#define CONTINUOUS_HEALTH_AP_TEST_FAIL BIT(23)
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#define CONTINUOUS_HEALTH_RC_TEST_FAIL BIT(22)
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#define SW_STARTUP_TEST_DONE BIT(21)
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#define SW_STARTUP_AP_TEST_FAIL BIT(20)
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#define SW_STARTUP_RC_TEST_FAIL BIT(19)
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#define RST_STARTUP_TEST_DONE BIT(18)
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#define RST_STARTUP_AP_TEST_FAIL BIT(17)
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#define RST_STARTUP_RC_TEST_FAIL BIT(16)
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#define RAW_DATA_VALID BIT(7)
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#define TRNG_RAW_DATA_OUT 0x828
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#define TRNG_CNT_TRANS_VALID 0x80
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#define BUSY_LOOP_SLEEP 10
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#define BUSY_LOOP_TIMEOUT (BUSY_LOOP_SLEEP * 10000)
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struct airoha_trng {
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void __iomem *base;
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struct hwrng rng;
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struct device *dev;
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struct completion rng_op_done;
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};
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static int airoha_trng_irq_mask(struct airoha_trng *trng)
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{
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u32 val;
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val = readl(trng->base + TRNG_INTR_EN);
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val |= INTR_MASK;
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writel(val, trng->base + TRNG_INTR_EN);
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return 0;
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}
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static int airoha_trng_irq_unmask(struct airoha_trng *trng)
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{
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u32 val;
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val = readl(trng->base + TRNG_INTR_EN);
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val &= ~INTR_MASK;
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writel(val, trng->base + TRNG_INTR_EN);
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return 0;
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}
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static int airoha_trng_init(struct hwrng *rng)
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{
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struct airoha_trng *trng = container_of(rng, struct airoha_trng, rng);
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int ret;
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u32 val;
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val = readl(trng->base + TRNG_NS_SEK_AND_DAT_EN);
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val |= RNG_EN;
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writel(val, trng->base + TRNG_NS_SEK_AND_DAT_EN);
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/* Set out of SW Reset */
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airoha_trng_irq_unmask(trng);
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writel(0, trng->base + TRNG_HEALTH_TEST_SW_RST);
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ret = wait_for_completion_timeout(&trng->rng_op_done, BUSY_LOOP_TIMEOUT);
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if (ret <= 0) {
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dev_err(trng->dev, "Timeout waiting for Health Check\n");
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airoha_trng_irq_mask(trng);
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return -ENODEV;
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}
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/* Check if Health Test Failed */
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val = readl(trng->base + TRNG_HEALTH_TEST_STATUS);
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if (val & (RST_STARTUP_AP_TEST_FAIL | RST_STARTUP_RC_TEST_FAIL)) {
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dev_err(trng->dev, "Health Check fail: %s test fail\n",
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val & RST_STARTUP_AP_TEST_FAIL ? "AP" : "RC");
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return -ENODEV;
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}
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/* Check if IP is ready */
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ret = readl_poll_timeout(trng->base + TRNG_IP_RDY, val,
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val & SAMPLE_RDY, 10, 1000);
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if (ret < 0) {
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dev_err(trng->dev, "Timeout waiting for IP ready");
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return -ENODEV;
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}
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/* CNT_TRANS must be 0x80 for IP to be considered ready */
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ret = readl_poll_timeout(trng->base + TRNG_IP_RDY, val,
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FIELD_GET(CNT_TRANS, val) == TRNG_CNT_TRANS_VALID,
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10, 1000);
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if (ret < 0) {
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dev_err(trng->dev, "Timeout waiting for IP ready");
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return -ENODEV;
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}
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return 0;
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}
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static void airoha_trng_cleanup(struct hwrng *rng)
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{
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struct airoha_trng *trng = container_of(rng, struct airoha_trng, rng);
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u32 val;
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val = readl(trng->base + TRNG_NS_SEK_AND_DAT_EN);
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val &= ~RNG_EN;
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writel(val, trng->base + TRNG_NS_SEK_AND_DAT_EN);
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/* Put it in SW Reset */
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writel(SW_RST, trng->base + TRNG_HEALTH_TEST_SW_RST);
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}
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static int airoha_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
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{
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struct airoha_trng *trng = container_of(rng, struct airoha_trng, rng);
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u32 *data = buf;
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u32 status;
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int ret;
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ret = readl_poll_timeout(trng->base + TRNG_HEALTH_TEST_STATUS, status,
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status & RAW_DATA_VALID, 10, 1000);
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if (ret < 0) {
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dev_err(trng->dev, "Timeout waiting for TRNG RAW Data valid\n");
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return ret;
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}
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*data = readl(trng->base + TRNG_RAW_DATA_OUT);
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return 4;
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}
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static irqreturn_t airoha_trng_irq(int irq, void *priv)
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{
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struct airoha_trng *trng = (struct airoha_trng *)priv;
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airoha_trng_irq_mask(trng);
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/* Just complete the task, we will read the value later */
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complete(&trng->rng_op_done);
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return IRQ_HANDLED;
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}
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static int airoha_trng_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct airoha_trng *trng;
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int irq, ret;
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u32 val;
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trng = devm_kzalloc(dev, sizeof(*trng), GFP_KERNEL);
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if (!trng)
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return -ENOMEM;
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trng->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(trng->base))
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return PTR_ERR(trng->base);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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airoha_trng_irq_mask(trng);
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ret = devm_request_irq(&pdev->dev, irq, airoha_trng_irq, 0,
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pdev->name, (void *)trng);
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if (ret) {
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dev_err(dev, "Can't get interrupt working.\n");
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return ret;
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}
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init_completion(&trng->rng_op_done);
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/* Enable interrupt for SW reset Health Check */
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val = readl(trng->base + TRNG_INTR_EN);
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val |= RST_STARTUP_INITR_EN;
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writel(val, trng->base + TRNG_INTR_EN);
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/* Set output to raw data */
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val = readl(trng->base + TRNG_NS_SEK_AND_DAT_EN);
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val |= RAW_DATA_EN;
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writel(val, trng->base + TRNG_NS_SEK_AND_DAT_EN);
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/* Put it in SW Reset */
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writel(SW_RST, trng->base + TRNG_HEALTH_TEST_SW_RST);
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trng->dev = dev;
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trng->rng.name = pdev->name;
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trng->rng.init = airoha_trng_init;
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trng->rng.cleanup = airoha_trng_cleanup;
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trng->rng.read = airoha_trng_read;
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ret = devm_hwrng_register(dev, &trng->rng);
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if (ret) {
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dev_err(dev, "failed to register rng device: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct of_device_id airoha_trng_of_match[] = {
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{ .compatible = "airoha,en7581-trng", },
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{},
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};
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MODULE_DEVICE_TABLE(of, airoha_trng_of_match);
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static struct platform_driver airoha_trng_driver = {
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.driver = {
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.name = "airoha-trng",
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.of_match_table = airoha_trng_of_match,
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},
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.probe = airoha_trng_probe,
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};
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module_platform_driver(airoha_trng_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Christian Marangi <[email protected]>");
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MODULE_DESCRIPTION("Airoha True Random Number Generator driver");
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