/*1* RNG driver for VIA RNGs2*3* Copyright 2005 (c) MontaVista Software, Inc.4*5* with the majority of the code coming from:6*7* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)8* (c) Copyright 2003 Red Hat Inc <[email protected]>9*10* derived from11*12* Hardware driver for the AMD 768 Random Number Generator (RNG)13* (c) Copyright 2001 Red Hat Inc14*15* derived from16*17* Hardware driver for Intel i810 Random Number Generator (RNG)18* Copyright 2000,2001 Jeff Garzik <[email protected]>19* Copyright 2000,2001 Philipp Rumpf <[email protected]>20*21* This file is licensed under the terms of the GNU General Public22* License version 2. This program is licensed "as is" without any23* warranty of any kind, whether express or implied.24*/2526#include <crypto/padlock.h>27#include <linux/module.h>28#include <linux/kernel.h>29#include <linux/hw_random.h>30#include <linux/delay.h>31#include <asm/cpu_device_id.h>32#include <asm/io.h>33#include <asm/msr.h>34#include <asm/cpufeature.h>35#include <asm/fpu/api.h>3637383940enum {41VIA_STRFILT_CNT_SHIFT = 16,42VIA_STRFILT_FAIL = (1 << 15),43VIA_STRFILT_ENABLE = (1 << 14),44VIA_RAWBITS_ENABLE = (1 << 13),45VIA_RNG_ENABLE = (1 << 6),46VIA_NOISESRC1 = (1 << 8),47VIA_NOISESRC2 = (1 << 9),48VIA_XSTORE_CNT_MASK = 0x0F,4950VIA_RNG_CHUNK_8 = 0x00, /* 64 rand bits, 64 stored bits */51VIA_RNG_CHUNK_4 = 0x01, /* 32 rand bits, 32 stored bits */52VIA_RNG_CHUNK_4_MASK = 0xFFFFFFFF,53VIA_RNG_CHUNK_2 = 0x02, /* 16 rand bits, 32 stored bits */54VIA_RNG_CHUNK_2_MASK = 0xFFFF,55VIA_RNG_CHUNK_1 = 0x03, /* 8 rand bits, 32 stored bits */56VIA_RNG_CHUNK_1_MASK = 0xFF,57};5859/*60* Investigate using the 'rep' prefix to obtain 32 bits of random data61* in one insn. The upside is potentially better performance. The62* downside is that the instruction becomes no longer atomic. Due to63* this, just like familiar issues with /dev/random itself, the worst64* case of a 'rep xstore' could potentially pause a cpu for an65* unreasonably long time. In practice, this condition would likely66* only occur when the hardware is failing. (or so we hope :))67*68* Another possible performance boost may come from simply buffering69* until we have 4 bytes, thus returning a u32 at a time,70* instead of the current u8-at-a-time.71*72* Padlock instructions can generate a spurious DNA fault, but the73* kernel doesn't use CR0.TS, so this doesn't matter.74*/7576static inline u32 xstore(u32 *addr, u32 edx_in)77{78u32 eax_out;7980asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"81: "=m" (*addr), "=a" (eax_out), "+d" (edx_in), "+D" (addr));8283return eax_out;84}8586static int via_rng_data_present(struct hwrng *rng, int wait)87{88char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__89((aligned(STACK_ALIGN)));90u32 *via_rng_datum = (u32 *)PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);91u32 bytes_out;92int i;9394/* We choose the recommended 1-byte-per-instruction RNG rate,95* for greater randomness at the expense of speed. Larger96* values 2, 4, or 8 bytes-per-instruction yield greater97* speed at lesser randomness.98*99* If you change this to another VIA_CHUNK_n, you must also100* change the ->n_bytes values in rng_vendor_ops[] tables.101* VIA_CHUNK_8 requires further code changes.102*103* A copy of MSR_VIA_RNG is placed in eax_out when xstore104* completes.105*/106107for (i = 0; i < 20; i++) {108*via_rng_datum = 0; /* paranoia, not really necessary */109bytes_out = xstore(via_rng_datum, VIA_RNG_CHUNK_1);110bytes_out &= VIA_XSTORE_CNT_MASK;111if (bytes_out || !wait)112break;113udelay(10);114}115rng->priv = *via_rng_datum;116return bytes_out ? 1 : 0;117}118119static int via_rng_data_read(struct hwrng *rng, u32 *data)120{121u32 via_rng_datum = (u32)rng->priv;122123*data = via_rng_datum;124125return 1;126}127128static int via_rng_init(struct hwrng *rng)129{130struct cpuinfo_x86 *c = &cpu_data(0);131u32 lo, hi, old_lo;132133/* VIA Nano CPUs don't have the MSR_VIA_RNG anymore. The RNG134* is always enabled if CPUID rng_en is set. There is no135* RNG configuration like it used to be the case in this136* register */137if (((c->x86 == 6) && (c->x86_model >= 0x0f)) || (c->x86 > 6)){138if (!boot_cpu_has(X86_FEATURE_XSTORE_EN)) {139pr_err(PFX "can't enable hardware RNG "140"if XSTORE is not enabled\n");141return -ENODEV;142}143return 0;144}145146/* Control the RNG via MSR. Tread lightly and pay very close147* attention to values written, as the reserved fields148* are documented to be "undefined and unpredictable"; but it149* does not say to write them as zero, so I make a guess that150* we restore the values we find in the register.151*/152rdmsr(MSR_VIA_RNG, lo, hi);153154old_lo = lo;155lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);156lo &= ~VIA_XSTORE_CNT_MASK;157lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);158lo |= VIA_RNG_ENABLE;159lo |= VIA_NOISESRC1;160161/* Enable secondary noise source on CPUs where it is present. */162163/* Nehemiah stepping 8 and higher */164if ((c->x86_model == 9) && (c->x86_stepping > 7))165lo |= VIA_NOISESRC2;166167/* Esther */168if (c->x86_model >= 10)169lo |= VIA_NOISESRC2;170171if (lo != old_lo)172wrmsr(MSR_VIA_RNG, lo, hi);173174/* perhaps-unnecessary sanity check; remove after testing if175unneeded */176rdmsr(MSR_VIA_RNG, lo, hi);177if ((lo & VIA_RNG_ENABLE) == 0) {178pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");179return -ENODEV;180}181182return 0;183}184185186static struct hwrng via_rng = {187.name = "via",188.init = via_rng_init,189.data_present = via_rng_data_present,190.data_read = via_rng_data_read,191};192193194static int __init via_rng_mod_init(void)195{196int err;197198if (!boot_cpu_has(X86_FEATURE_XSTORE))199return -ENODEV;200201pr_info("VIA RNG detected\n");202err = hwrng_register(&via_rng);203if (err) {204pr_err(PFX "RNG registering failed (%d)\n",205err);206goto out;207}208out:209return err;210}211module_init(via_rng_mod_init);212213static void __exit via_rng_mod_exit(void)214{215hwrng_unregister(&via_rng);216}217module_exit(via_rng_mod_exit);218219static struct x86_cpu_id __maybe_unused via_rng_cpu_id[] = {220X86_MATCH_FEATURE(X86_FEATURE_XSTORE, NULL),221{}222};223MODULE_DEVICE_TABLE(x86cpu, via_rng_cpu_id);224225MODULE_DESCRIPTION("H/W RNG driver for VIA CPU with PadLock");226MODULE_LICENSE("GPL");227228229