Path: blob/master/drivers/crypto/intel/qat/qat_6xxx/adf_drv.c
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// SPDX-License-Identifier: GPL-2.0-only1/* Copyright(c) 2025 Intel Corporation */2#include <linux/array_size.h>3#include <linux/device.h>4#include <linux/dma-mapping.h>5#include <linux/errno.h>6#include <linux/list.h>7#include <linux/module.h>8#include <linux/pci.h>9#include <linux/types.h>1011#include <adf_accel_devices.h>12#include <adf_cfg.h>13#include <adf_common_drv.h>14#include <adf_dbgfs.h>1516#include "adf_gen6_shared.h"17#include "adf_6xxx_hw_data.h"1819static int bar_map[] = {200, /* SRAM */212, /* PMISC */224, /* ETR */23};2425static void adf_device_down(void *accel_dev)26{27adf_dev_down(accel_dev);28}2930static void adf_dbgfs_cleanup(void *accel_dev)31{32adf_dbgfs_exit(accel_dev);33}3435static void adf_cfg_device_remove(void *accel_dev)36{37adf_cfg_dev_remove(accel_dev);38}3940static void adf_cleanup_hw_data(void *accel_dev)41{42struct adf_accel_dev *accel_device = accel_dev;4344if (accel_device->hw_device) {45adf_clean_hw_data_6xxx(accel_device->hw_device);46accel_device->hw_device = NULL;47}48}4950static void adf_devmgr_remove(void *accel_dev)51{52adf_devmgr_rm_dev(accel_dev, NULL);53}5455static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)56{57struct adf_accel_pci *accel_pci_dev;58struct adf_hw_device_data *hw_data;59struct device *dev = &pdev->dev;60struct adf_accel_dev *accel_dev;61struct adf_bar *bar;62unsigned int i;63int ret;6465if (num_possible_nodes() > 1 && dev_to_node(dev) < 0) {66/*67* If the accelerator is connected to a node with no memory68* there is no point in using the accelerator since the remote69* memory transaction will be very slow.70*/71return dev_err_probe(dev, -EINVAL, "Invalid NUMA configuration.\n");72}7374accel_dev = devm_kzalloc(dev, sizeof(*accel_dev), GFP_KERNEL);75if (!accel_dev)76return -ENOMEM;7778INIT_LIST_HEAD(&accel_dev->crypto_list);79INIT_LIST_HEAD(&accel_dev->list);80accel_pci_dev = &accel_dev->accel_pci_dev;81accel_pci_dev->pci_dev = pdev;82accel_dev->owner = THIS_MODULE;8384hw_data = devm_kzalloc(dev, sizeof(*hw_data), GFP_KERNEL);85if (!hw_data)86return -ENOMEM;8788pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);89pci_read_config_dword(pdev, ADF_GEN6_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]);90pci_read_config_dword(pdev, ADF_GEN6_FUSECTL0_OFFSET, &hw_data->fuses[ADF_FUSECTL0]);91pci_read_config_dword(pdev, ADF_GEN6_FUSECTL1_OFFSET, &hw_data->fuses[ADF_FUSECTL1]);9293if (!(hw_data->fuses[ADF_FUSECTL1] & ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE))94return dev_err_probe(dev, -EFAULT, "Wireless mode is not supported.\n");9596/* Enable PCI device */97ret = pcim_enable_device(pdev);98if (ret)99return dev_err_probe(dev, ret, "Cannot enable PCI device.\n");100101ret = adf_devmgr_add_dev(accel_dev, NULL);102if (ret)103return dev_err_probe(dev, ret, "Failed to add new accelerator device.\n");104105ret = devm_add_action_or_reset(dev, adf_devmgr_remove, accel_dev);106if (ret)107return ret;108109accel_dev->hw_device = hw_data;110adf_init_hw_data_6xxx(accel_dev->hw_device);111112ret = devm_add_action_or_reset(dev, adf_cleanup_hw_data, accel_dev);113if (ret)114return ret;115116/* Get Accelerators and Accelerator Engine masks */117hw_data->accel_mask = hw_data->get_accel_mask(hw_data);118hw_data->ae_mask = hw_data->get_ae_mask(hw_data);119accel_pci_dev->sku = hw_data->get_sku(hw_data);120121/* If the device has no acceleration engines then ignore it */122if (!hw_data->accel_mask || !hw_data->ae_mask ||123(~hw_data->ae_mask & ADF_GEN6_ACCELERATORS_MASK)) {124ret = -EFAULT;125return dev_err_probe(dev, ret, "No acceleration units were found.\n");126}127128/* Create device configuration table */129ret = adf_cfg_dev_add(accel_dev);130if (ret)131return ret;132133ret = devm_add_action_or_reset(dev, adf_cfg_device_remove, accel_dev);134if (ret)135return ret;136137/* Set DMA identifier */138ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));139if (ret)140return dev_err_probe(dev, ret, "No usable DMA configuration.\n");141142ret = adf_gen6_cfg_dev_init(accel_dev);143if (ret)144return dev_err_probe(dev, ret, "Failed to initialize configuration.\n");145146/* Get accelerator capability mask */147hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);148if (!hw_data->accel_capabilities_mask) {149ret = -EINVAL;150return dev_err_probe(dev, ret, "Failed to get capabilities mask.\n");151}152153for (i = 0; i < ARRAY_SIZE(bar_map); i++) {154bar = &accel_pci_dev->pci_bars[i];155156/* Map 64-bit PCIe BAR */157bar->virt_addr = pcim_iomap_region(pdev, bar_map[i], pci_name(pdev));158if (IS_ERR(bar->virt_addr)) {159ret = PTR_ERR(bar->virt_addr);160return dev_err_probe(dev, ret, "Failed to ioremap PCI region.\n");161}162}163164pci_set_master(pdev);165166/*167* The PCI config space is saved at this point and will be restored168* after a Function Level Reset (FLR) as the FLR does not completely169* restore it.170*/171ret = pci_save_state(pdev);172if (ret)173return dev_err_probe(dev, ret, "Failed to save pci state.\n");174175accel_dev->ras_errors.enabled = true;176177adf_dbgfs_init(accel_dev);178179ret = devm_add_action_or_reset(dev, adf_dbgfs_cleanup, accel_dev);180if (ret)181return ret;182183ret = adf_dev_up(accel_dev, true);184if (ret)185return ret;186187ret = devm_add_action_or_reset(dev, adf_device_down, accel_dev);188if (ret)189return ret;190191ret = adf_sysfs_init(accel_dev);192193return ret;194}195196static void adf_shutdown(struct pci_dev *pdev)197{198struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev);199200adf_dev_down(accel_dev);201}202203static const struct pci_device_id adf_pci_tbl[] = {204{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QAT_6XXX) },205{ }206};207MODULE_DEVICE_TABLE(pci, adf_pci_tbl);208209static struct pci_driver adf_driver = {210.id_table = adf_pci_tbl,211.name = ADF_6XXX_DEVICE_NAME,212.probe = adf_probe,213.shutdown = adf_shutdown,214.sriov_configure = adf_sriov_configure,215.err_handler = &adf_err_handler,216};217module_pci_driver(adf_driver);218219MODULE_LICENSE("GPL");220MODULE_AUTHOR("Intel");221MODULE_FIRMWARE(ADF_6XXX_FW);222MODULE_FIRMWARE(ADF_6XXX_MMP);223MODULE_DESCRIPTION("Intel(R) QuickAssist Technology for GEN6 Devices");224MODULE_SOFTDEP("pre: crypto-intel_qat");225MODULE_IMPORT_NS("CRYPTO_QAT");226227228