Path: blob/master/drivers/crypto/intel/qat/qat_common/adf_admin.h
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/* SPDX-License-Identifier: GPL-2.0-only */1/* Copyright(c) 2023 Intel Corporation */2#ifndef ADF_ADMIN3#define ADF_ADMIN45#include "icp_qat_fw_init_admin.h"67struct adf_accel_dev;89int adf_init_admin_comms(struct adf_accel_dev *accel_dev);10void adf_exit_admin_comms(struct adf_accel_dev *accel_dev);11int adf_send_admin_init(struct adf_accel_dev *accel_dev);12int adf_get_ae_fw_counters(struct adf_accel_dev *accel_dev, u16 ae, u64 *reqs, u64 *resps);13int adf_init_admin_pm(struct adf_accel_dev *accel_dev, u32 idle_delay);14int adf_send_admin_tim_sync(struct adf_accel_dev *accel_dev, u32 cnt);15int adf_send_admin_hb_timer(struct adf_accel_dev *accel_dev, uint32_t ticks);16int adf_send_admin_rl_init(struct adf_accel_dev *accel_dev,17struct icp_qat_fw_init_admin_slice_cnt *slices);18int adf_send_admin_rl_add_update(struct adf_accel_dev *accel_dev,19struct icp_qat_fw_init_admin_req *req);20int adf_send_admin_rl_delete(struct adf_accel_dev *accel_dev, u16 node_id,21u8 node_type);22int adf_get_fw_timestamp(struct adf_accel_dev *accel_dev, u64 *timestamp);23int adf_get_pm_info(struct adf_accel_dev *accel_dev, dma_addr_t p_state_addr, size_t buff_size);24int adf_get_cnv_stats(struct adf_accel_dev *accel_dev, u16 ae, u16 *err_cnt, u16 *latest_err);25int adf_send_admin_tl_start(struct adf_accel_dev *accel_dev,26dma_addr_t tl_dma_addr, size_t layout_sz, u8 *rp_indexes,27struct icp_qat_fw_init_admin_slice_cnt *slice_count);28int adf_send_admin_tl_stop(struct adf_accel_dev *accel_dev);2930#endif313233