Path: blob/master/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h
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/*1* GMC_7_1 Register documentation2*3* Copyright (C) 2014 Advanced Micro Devices, Inc.4*5* Permission is hereby granted, free of charge, to any person obtaining a6* copy of this software and associated documentation files (the "Software"),7* to deal in the Software without restriction, including without limitation8* the rights to use, copy, modify, merge, publish, distribute, sublicense,9* and/or sell copies of the Software, and to permit persons to whom the10* Software is furnished to do so, subject to the following conditions:11*12* The above copyright notice and this permission notice shall be included13* in all copies or substantial portions of the Software.14*15* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS16* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN19* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN20* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.21*/2223#ifndef GMC_7_1_SH_MASK_H24#define GMC_7_1_SH_MASK_H2526#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x127#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x028#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x229#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x130#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x431#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x232#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x833#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x334#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x1035#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x436#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x2037#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x538#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x4039#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x640#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x8041#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x742#define MC_CONFIG__MC_RD_ENABLE_MASK 0x70043#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x844#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x8000000045#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f46#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x147#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x048#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x249#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x150#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x451#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x252#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x853#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x354#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x1055#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x456#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x2057#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x558#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x4059#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x660#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x8061#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x762#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x10063#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x864#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x20065#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x966#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x40067#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa68#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x80069#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb70#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x100071#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc72#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x200073#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd74#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x400075#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe76#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x800077#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf78#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x7000079#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x1080#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x38000081#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x1382#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x40000083#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x1684#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x80000085#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x1786#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x100000087#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x1888#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x200000089#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x1990#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff91#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x092#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x10093#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x894#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x20095#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x996#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x40097#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa98#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x80099#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb100#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000101#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc102#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000103#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd104#define MC_ARB_FED_CNTL__MODE_MASK 0x3105#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0106#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc107#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2108#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10109#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4110#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20111#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5112#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40113#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6114#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80115#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7116#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1117#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0118#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2119#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1120#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4121#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2122#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8123#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3124#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10125#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4126#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20127#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5128#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40129#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6130#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80131#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7132#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100133#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8134#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200135#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9136#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400137#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa138#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800139#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb140#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000141#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc142#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000143#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd144#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000145#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe146#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000147#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf148#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000149#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10150#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000151#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11152#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000153#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12154#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000155#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14156#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000157#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15158#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000159#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16160#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000161#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18162#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000163#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19164#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000165#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a166#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000167#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c168#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000169#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d170#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf171#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0172#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10173#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4174#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20175#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5176#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40177#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6178#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80179#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7180#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100181#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8182#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200183#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9184#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400185#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa186#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800187#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb188#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000189#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc190#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000191#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd192#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3193#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0194#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4195#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2196#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18197#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3198#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20199#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5200#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff201#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0202#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00203#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8204#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000205#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10206#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000207#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18208#define MC_ARB_PERF_CID__CH0_MASK 0xff209#define MC_ARB_PERF_CID__CH0__SHIFT 0x0210#define MC_ARB_PERF_CID__CH1_MASK 0xff00211#define MC_ARB_PERF_CID__CH1__SHIFT 0x8212#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000213#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10214#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000215#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11216#define MC_ARB_GECC2__ENABLE_MASK 0x1217#define MC_ARB_GECC2__ENABLE__SHIFT 0x0218#define MC_ARB_GECC2__ECC_MODE_MASK 0x6219#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1220#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18221#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3222#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60223#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5224#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780225#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7226#define MC_ARB_GECC2__READ_ERR_MASK 0x3800227#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb228#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000229#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe230#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000231#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf232#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000233#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15234#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000235#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16236#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff237#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0238#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00239#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8240#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000241#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10242#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000243#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18244#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf245#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0246#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0247#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4248#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00249#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8250#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000251#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc252#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000253#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10254#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000255#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14256#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000257#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18258#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000259#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c260#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf261#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0262#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0263#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4264#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00265#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8266#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000267#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc268#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1269#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0270#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2271#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1272#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4273#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2274#define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffff8275#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x3276#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf277#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0278#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0279#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4280#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200281#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9282#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400283#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa284#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800285#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb286#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000287#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc288#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000289#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd290#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000291#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe292#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff293#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0294#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1295#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0296#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2297#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1298#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc299#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2300#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10301#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4302#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20303#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5304#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40305#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6306#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80307#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7308#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100309#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8310#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200311#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9312#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400313#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa314#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800315#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb316#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000317#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe318#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000319#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf320#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000321#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10322#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000323#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11324#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000325#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12326#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000327#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13328#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000329#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14330#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000331#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15332#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000333#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16334#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000335#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17336#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000337#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18338#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000339#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19340#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f341#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0342#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20343#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5344#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0345#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6346#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000347#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd348#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000349#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14350#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000351#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19352#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000353#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e354#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f355#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0356#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0357#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6358#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000359#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc360#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000361#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd362#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3363#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0364#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc365#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2366#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0367#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4368#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000369#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc370#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000371#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11372#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000373#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19374#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1375#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0376#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e377#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1378#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80379#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7380#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000381#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd382#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20383#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5384#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40385#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6386#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80387#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7388#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100389#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8390#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200391#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9392#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400393#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa394#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800395#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb396#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000397#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc398#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000399#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd400#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000401#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe402#define MC_ARB_MISC2__GECC_MASK 0x40000403#define MC_ARB_MISC2__GECC__SHIFT 0x12404#define MC_ARB_MISC2__GECC_RST_MASK 0x80000405#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13406#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000407#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14408#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000409#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15410#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000411#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19412#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000413#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c414#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000415#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d416#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000417#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e418#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000419#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f420#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1421#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0422#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2423#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1424#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4425#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2426#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8427#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3428#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800429#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb430#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000431#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13432#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000433#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14434#define MC_ARB_MISC__CALI_RATES_MASK 0x600000435#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15436#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000437#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17438#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000439#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18440#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000441#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19442#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000443#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a444#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000445#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e446#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000447#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f448#define MC_ARB_BANKMAP__BANK0_MASK 0xf449#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0450#define MC_ARB_BANKMAP__BANK1_MASK 0xf0451#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4452#define MC_ARB_BANKMAP__BANK2_MASK 0xf00453#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8454#define MC_ARB_BANKMAP__BANK3_MASK 0xf000455#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc456#define MC_ARB_BANKMAP__RANK_MASK 0xf0000457#define MC_ARB_BANKMAP__RANK__SHIFT 0x10458#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3459#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0460#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4461#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2462#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38463#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3464#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0465#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6466#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100467#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8468#define MC_ARB_RAMCFG__RSV_1_MASK 0x200469#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9470#define MC_ARB_RAMCFG__RSV_2_MASK 0x400471#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa472#define MC_ARB_RAMCFG__RSV_3_MASK 0x800473#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb474#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000475#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc476#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000477#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd478#define MC_ARB_POP__ENABLE_ARB_MASK 0x1479#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0480#define MC_ARB_POP__SPEC_OPEN_MASK 0x2481#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1482#define MC_ARB_POP__POP_DEPTH_MASK 0x3c483#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2484#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0485#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6486#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000487#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc488#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000489#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf490#define MC_ARB_POP__QUICK_STOP_MASK 0x20000491#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11492#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000493#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12494#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000495#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13496#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff497#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0498#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00499#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8500#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000501#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10502#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000503#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11504#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff505#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0506#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100507#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8508#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200509#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9510#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00511#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa512#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000513#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10514#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000515#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18516#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf517#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0518#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0519#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4520#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000521#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc522#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff523#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0524#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00525#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8526#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000527#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10528#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000529#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18530#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff531#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0532#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00533#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8534#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000535#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10536#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000537#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18538#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3539#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0540#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4541#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2542#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8543#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3544#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10545#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4546#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20547#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5548#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40549#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6550#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80551#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7552#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100553#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8554#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200555#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9556#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400557#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa558#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800559#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb560#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000561#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc562#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000563#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd564#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3565#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0566#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4567#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2568#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8569#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3570#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10571#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4572#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20573#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5574#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40575#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6576#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80577#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7578#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100579#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8580#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200581#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9582#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400583#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa584#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800585#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb586#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000587#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc588#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000589#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd590#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3591#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0592#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc593#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2594#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30595#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4596#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0597#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6598#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300599#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8600#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00601#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa602#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000603#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc604#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000605#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe606#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000607#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10608#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3609#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0610#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc611#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2612#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30613#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4614#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0615#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6616#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300617#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8618#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00619#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa620#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000621#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc622#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000623#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe624#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000625#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10626#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1627#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0628#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6629#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1630#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8631#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3632#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10633#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4634#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1635#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0636#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6637#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1638#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8639#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3640#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10641#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4642#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff643#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0644#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00645#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8646#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000647#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10648#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000649#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18650#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff651#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0652#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00653#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8654#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000655#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10656#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000657#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18658#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff659#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0660#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00661#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8662#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000663#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10664#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000665#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18666#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff667#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0668#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00669#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8670#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000671#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10672#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000673#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18674#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3675#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0676#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc677#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2678#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30679#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4680#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0681#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6682#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300683#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8684#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00685#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa686#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000687#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc688#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000689#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe690#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000691#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10692#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000693#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11694#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000695#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12696#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000697#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13698#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000699#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14700#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000701#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15702#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000703#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16704#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000705#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17706#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000707#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18708#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000709#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19710#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000711#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a712#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000713#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b714#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000715#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c716#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000717#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d718#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000719#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e720#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000721#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f722#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3723#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0724#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc725#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2726#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30727#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4728#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0729#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6730#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300731#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8732#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00733#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa734#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000735#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc736#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000737#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe738#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000739#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10740#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000741#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11742#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000743#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12744#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000745#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13746#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000747#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14748#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000749#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15750#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000751#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16752#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000753#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17754#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000755#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18756#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000757#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19758#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000759#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a760#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000761#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b762#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000763#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c764#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000765#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d766#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000767#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e768#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000769#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f770#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1771#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0772#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e773#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1774#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0775#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6776#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800777#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb778#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000779#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc780#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000781#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd782#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000783#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe784#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff785#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0786#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3787#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0788#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4789#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2790#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8791#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3792#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10793#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4794#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20795#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5796#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40797#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6798#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80799#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7800#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300801#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8802#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400803#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa804#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800805#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb806#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000807#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc808#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000809#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd810#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000811#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe812#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000813#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf814#define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000815#define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10816#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000817#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12818#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000819#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13820#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000821#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14822#define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000823#define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18824#define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000825#define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19826#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf827#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0828#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0829#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4830#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100831#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8832#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200833#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9834#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00835#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa836#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf837#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0838#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0839#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4840#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100841#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8842#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200843#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9844#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00845#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa846#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff847#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0848#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00849#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8850#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000851#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10852#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000853#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11854#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000855#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12856#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000857#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13858#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000859#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14860#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000861#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15862#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff863#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0864#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00865#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8866#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000867#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10868#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000869#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11870#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000871#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12872#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000873#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13874#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000875#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14876#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000877#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15878#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000879#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18880#define MC_ARB_REMREQ__RD_WATER_MASK 0xff881#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0882#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00883#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8884#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000885#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10886#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000887#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14888#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000889#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18890#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1891#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0892#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2893#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1894#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4895#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2896#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8897#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3898#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10899#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4900#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20901#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5902#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40903#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6904#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80905#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7906#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00907#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8908#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000909#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf910#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff911#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0912#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00913#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8914#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000915#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10916#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000917#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18918#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff919#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0920#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00921#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8922#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000923#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10924#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000925#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18926#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000927#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c928#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff929#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0930#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00931#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8932#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000933#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10934#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000935#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11936#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000937#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12938#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000939#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13940#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff941#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0942#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff943#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0944#define MC_ARB_SSM__FORMAT_MASK 0x1f945#define MC_ARB_SSM__FORMAT__SHIFT 0x0946#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff947#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0948#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00949#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8950#define MC_ARB_CG__RSV_0_MASK 0xff0000951#define MC_ARB_CG__RSV_0__SHIFT 0x10952#define MC_ARB_CG__RSV_1_MASK 0xff000000953#define MC_ARB_CG__RSV_1__SHIFT 0x18954#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1955#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0956#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2957#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1958#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c959#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2960#define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80961#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7962#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000963#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd964#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000965#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe966#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000967#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10968#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000969#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11970#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000971#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12972#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000973#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16974#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000975#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19976#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000977#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a978#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000979#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b980#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000981#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c982#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff983#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0984#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00985#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8986#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000987#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10988#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000989#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18990#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1991#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0992#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2993#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1994#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4995#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2996#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8997#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3998#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10999#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x41000#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x201001#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x51002#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x401003#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x61004#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x801005#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x71006#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x1001007#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x81008#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x2001009#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x91010#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x4001011#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa1012#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x8001013#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb1014#define MC_ARB_BUSY_STATUS__POP0_MASK 0x10001015#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc1016#define MC_ARB_BUSY_STATUS__POP1_MASK 0x20001017#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd1018#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x40001019#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe1020#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x80001021#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf1022#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x100001023#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x101024#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x200001025#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x111026#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x400001027#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x121028#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x800001029#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x131030#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x1000001031#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x141032#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x2000001033#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x151034#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x4000001035#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x161036#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x8000001037#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x171038#define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x10000001039#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x181040#define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x20000001041#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x191042#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x40000001043#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a1044#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x80000001045#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b1046#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x100000001047#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c1048#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x200000001049#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d1050#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x400000001051#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e1052#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x800000001053#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f1054#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff1055#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x01056#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff001057#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x81058#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff00001059#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x101060#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f0000001061#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x181062#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f1063#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x01064#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e01065#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x51066#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c001067#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa1068#define MC_ARB_BURST_TIME__STATE3_MASK 0xf80001069#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf1070#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x11071#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x01072#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x21073#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x11074#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x41075#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x21076#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x81077#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x31078#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x101079#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x41080#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf001081#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x81082#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x10001083#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc1084#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x60001085#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd1086#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x180001087#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf1088#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x600001089#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x111090#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x1800001091#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x131092#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x6000001093#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x151094#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x18000001095#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x171096#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x20000001097#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x191098#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x40000001099#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a1100#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x80000001101#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b1102#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x100000001103#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c1104#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x600000001105#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d1106#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e1107#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x11108#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x11109#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x01110#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x21111#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x11112#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x41113#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x21114#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x81115#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x31116#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x301117#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x41118#define MC_CG_CONFIG__INDEX_MASK 0x3fffc01119#define MC_CG_CONFIG__INDEX__SHIFT 0x61120#define MC_CITF_CNTL__IGNOREPM_MASK 0x41121#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x21122#define MC_CITF_CNTL__EXEMPTPM_MASK 0x81123#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x31124#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x301125#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x41126#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x401127#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x61128#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x1801129#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x71130#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x2001131#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x91132#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f1133#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x01134#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc01135#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x61136#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff1137#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x01138#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff001139#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x81140#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff00001141#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x101142#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x10000001143#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x181144#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x20000001145#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x191146#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff1147#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x01148#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff001149#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x81150#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff00001151#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x101152#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x10000001153#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x181154#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x20000001155#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x191156#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x11157#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x01158#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e1159#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x11160#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x201161#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x51162#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c01163#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x61164#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f1165#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x01166#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f0001167#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc1168#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc00001169#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x121170#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f0000001171#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x181172#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x11173#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x01174#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x21175#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x11176#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x41177#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x21178#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x81179#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x31180#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x101181#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x41182#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x201183#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x51184#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x401185#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x61186#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f801187#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x71188#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f1189#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x01190#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f00001191#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x101192#define MC_CITF_DAGB_DLY__POS_MASK 0x1f0000001193#define MC_CITF_DAGB_DLY__POS__SHIFT 0x181194#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf1195#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x01196#define MC_RD_GRP_EXT__TC0_MASK 0xf01197#define MC_RD_GRP_EXT__TC0__SHIFT 0x41198#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf1199#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x01200#define MC_WR_GRP_EXT__TC0_MASK 0xf01201#define MC_WR_GRP_EXT__TC0__SHIFT 0x41202#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f1203#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x01204#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f801205#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x71206#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x40001207#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe1208#define MC_WR_TC0__ENABLE_MASK 0x11209#define MC_WR_TC0__ENABLE__SHIFT 0x01210#define MC_WR_TC0__PRESCALE_MASK 0x61211#define MC_WR_TC0__PRESCALE__SHIFT 0x11212#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x81213#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x31214#define MC_WR_TC0__STALL_MODE_MASK 0x301215#define MC_WR_TC0__STALL_MODE__SHIFT 0x41216#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x401217#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x61218#define MC_WR_TC0__MAX_BURST_MASK 0x7801219#define MC_WR_TC0__MAX_BURST__SHIFT 0x71220#define MC_WR_TC0__LAZY_TIMER_MASK 0x78001221#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb1222#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x80001223#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf1224#define MC_WR_TC1__ENABLE_MASK 0x11225#define MC_WR_TC1__ENABLE__SHIFT 0x01226#define MC_WR_TC1__PRESCALE_MASK 0x61227#define MC_WR_TC1__PRESCALE__SHIFT 0x11228#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x81229#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x31230#define MC_WR_TC1__STALL_MODE_MASK 0x301231#define MC_WR_TC1__STALL_MODE__SHIFT 0x41232#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x401233#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x61234#define MC_WR_TC1__MAX_BURST_MASK 0x7801235#define MC_WR_TC1__MAX_BURST__SHIFT 0x71236#define MC_WR_TC1__LAZY_TIMER_MASK 0x78001237#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb1238#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x80001239#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf1240#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f1241#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x01242#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc01243#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x61244#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x71245#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x01246#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x381247#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x31248#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c01249#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x61250#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe001251#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x91252#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x70001253#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc1254#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x380001255#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf1256#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c00001257#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x121258#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe000001259#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x151260#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x10000001261#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x181262#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x20000001263#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x191264#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x71265#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x01266#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x381267#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x31268#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c01269#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x61270#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe001271#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x91272#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x70001273#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc1274#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x380001275#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf1276#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c00001277#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x121278#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe000001279#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x151280#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x10000001281#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x181282#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x20000001283#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x191284#define MC_RD_CB__ENABLE_MASK 0x11285#define MC_RD_CB__ENABLE__SHIFT 0x01286#define MC_RD_CB__PRESCALE_MASK 0x61287#define MC_RD_CB__PRESCALE__SHIFT 0x11288#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x81289#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x31290#define MC_RD_CB__STALL_MODE_MASK 0x301291#define MC_RD_CB__STALL_MODE__SHIFT 0x41292#define MC_RD_CB__STALL_OVERRIDE_MASK 0x401293#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x61294#define MC_RD_CB__MAX_BURST_MASK 0x7801295#define MC_RD_CB__MAX_BURST__SHIFT 0x71296#define MC_RD_CB__LAZY_TIMER_MASK 0x78001297#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb1298#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x80001299#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf1300#define MC_RD_DB__ENABLE_MASK 0x11301#define MC_RD_DB__ENABLE__SHIFT 0x01302#define MC_RD_DB__PRESCALE_MASK 0x61303#define MC_RD_DB__PRESCALE__SHIFT 0x11304#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x81305#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x31306#define MC_RD_DB__STALL_MODE_MASK 0x301307#define MC_RD_DB__STALL_MODE__SHIFT 0x41308#define MC_RD_DB__STALL_OVERRIDE_MASK 0x401309#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x61310#define MC_RD_DB__MAX_BURST_MASK 0x7801311#define MC_RD_DB__MAX_BURST__SHIFT 0x71312#define MC_RD_DB__LAZY_TIMER_MASK 0x78001313#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb1314#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x80001315#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf1316#define MC_RD_TC0__ENABLE_MASK 0x11317#define MC_RD_TC0__ENABLE__SHIFT 0x01318#define MC_RD_TC0__PRESCALE_MASK 0x61319#define MC_RD_TC0__PRESCALE__SHIFT 0x11320#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x81321#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x31322#define MC_RD_TC0__STALL_MODE_MASK 0x301323#define MC_RD_TC0__STALL_MODE__SHIFT 0x41324#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x401325#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x61326#define MC_RD_TC0__MAX_BURST_MASK 0x7801327#define MC_RD_TC0__MAX_BURST__SHIFT 0x71328#define MC_RD_TC0__LAZY_TIMER_MASK 0x78001329#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb1330#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x80001331#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf1332#define MC_RD_TC1__ENABLE_MASK 0x11333#define MC_RD_TC1__ENABLE__SHIFT 0x01334#define MC_RD_TC1__PRESCALE_MASK 0x61335#define MC_RD_TC1__PRESCALE__SHIFT 0x11336#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x81337#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x31338#define MC_RD_TC1__STALL_MODE_MASK 0x301339#define MC_RD_TC1__STALL_MODE__SHIFT 0x41340#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x401341#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x61342#define MC_RD_TC1__MAX_BURST_MASK 0x7801343#define MC_RD_TC1__MAX_BURST__SHIFT 0x71344#define MC_RD_TC1__LAZY_TIMER_MASK 0x78001345#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb1346#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x80001347#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf1348#define MC_RD_HUB__ENABLE_MASK 0x11349#define MC_RD_HUB__ENABLE__SHIFT 0x01350#define MC_RD_HUB__PRESCALE_MASK 0x61351#define MC_RD_HUB__PRESCALE__SHIFT 0x11352#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x81353#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x31354#define MC_RD_HUB__STALL_MODE_MASK 0x301355#define MC_RD_HUB__STALL_MODE__SHIFT 0x41356#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x401357#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x61358#define MC_RD_HUB__MAX_BURST_MASK 0x7801359#define MC_RD_HUB__MAX_BURST__SHIFT 0x71360#define MC_RD_HUB__LAZY_TIMER_MASK 0x78001361#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb1362#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x80001363#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf1364#define MC_WR_CB__ENABLE_MASK 0x11365#define MC_WR_CB__ENABLE__SHIFT 0x01366#define MC_WR_CB__PRESCALE_MASK 0x61367#define MC_WR_CB__PRESCALE__SHIFT 0x11368#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x81369#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x31370#define MC_WR_CB__STALL_MODE_MASK 0x301371#define MC_WR_CB__STALL_MODE__SHIFT 0x41372#define MC_WR_CB__STALL_OVERRIDE_MASK 0x401373#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x61374#define MC_WR_CB__MAX_BURST_MASK 0x7801375#define MC_WR_CB__MAX_BURST__SHIFT 0x71376#define MC_WR_CB__LAZY_TIMER_MASK 0x78001377#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb1378#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x80001379#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf1380#define MC_WR_DB__ENABLE_MASK 0x11381#define MC_WR_DB__ENABLE__SHIFT 0x01382#define MC_WR_DB__PRESCALE_MASK 0x61383#define MC_WR_DB__PRESCALE__SHIFT 0x11384#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x81385#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x31386#define MC_WR_DB__STALL_MODE_MASK 0x301387#define MC_WR_DB__STALL_MODE__SHIFT 0x41388#define MC_WR_DB__STALL_OVERRIDE_MASK 0x401389#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x61390#define MC_WR_DB__MAX_BURST_MASK 0x7801391#define MC_WR_DB__MAX_BURST__SHIFT 0x71392#define MC_WR_DB__LAZY_TIMER_MASK 0x78001393#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb1394#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x80001395#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf1396#define MC_WR_HUB__ENABLE_MASK 0x11397#define MC_WR_HUB__ENABLE__SHIFT 0x01398#define MC_WR_HUB__PRESCALE_MASK 0x61399#define MC_WR_HUB__PRESCALE__SHIFT 0x11400#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x81401#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x31402#define MC_WR_HUB__STALL_MODE_MASK 0x301403#define MC_WR_HUB__STALL_MODE__SHIFT 0x41404#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x401405#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x61406#define MC_WR_HUB__MAX_BURST_MASK 0x7801407#define MC_WR_HUB__MAX_BURST__SHIFT 0x71408#define MC_WR_HUB__LAZY_TIMER_MASK 0x78001409#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb1410#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x80001411#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf1412#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff1413#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x01414#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff001415#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x81416#define MC_RD_GRP_LCL__CB0_MASK 0xf0001417#define MC_RD_GRP_LCL__CB0__SHIFT 0xc1418#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf00001419#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x101420#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf000001421#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x141422#define MC_RD_GRP_LCL__DB0_MASK 0xf0000001423#define MC_RD_GRP_LCL__DB0__SHIFT 0x181424#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf00000001425#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c1426#define MC_WR_GRP_LCL__CB0_MASK 0xf1427#define MC_WR_GRP_LCL__CB0__SHIFT 0x01428#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf01429#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x41430#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf001431#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x81432#define MC_WR_GRP_LCL__DB0_MASK 0xf0001433#define MC_WR_GRP_LCL__DB0__SHIFT 0xc1434#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf00001435#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x101436#define MC_WR_GRP_LCL__SX0_MASK 0xf000001437#define MC_WR_GRP_LCL__SX0__SHIFT 0x141438#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf00000001439#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c1440#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff1441#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x01442#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x401443#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x61444#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x801445#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x71446#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x1001447#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x81448#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x2001449#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x91450#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x4001451#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa1452#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x8001453#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb1454#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x10001455#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc1456#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x20001457#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd1458#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x40001459#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe1460#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x80001461#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf1462#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x100001463#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x101464#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x200001465#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x111466#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x400001467#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x121468#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f1469#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x01470#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc01471#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x61472#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f0001473#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc1474#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x400001475#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x121476#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x800001477#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x131478#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f1479#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x01480#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc01481#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x61482#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f0001483#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc1484#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x400001485#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x121486#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x800001487#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x131488#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f1489#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x01490#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc01491#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x61492#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f0001493#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc1494#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x400001495#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x121496#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x800001497#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x131498#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x41499#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x21500#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x181501#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x31502#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f1503#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x01504#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc01505#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x61506#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f0001507#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc1508#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x400001509#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x121510#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x800001511#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x131512#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f1513#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x01514#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc01515#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x61516#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f0001517#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc1518#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x400001519#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x121520#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x800001521#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x131522#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f1523#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x01524#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc01525#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x61526#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f0001527#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc1528#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x400001529#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x121530#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x800001531#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x131532#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x11533#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x01534#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x21535#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x11536#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x41537#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x21538#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x81539#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x31540#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x101541#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x41542#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x201543#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x51544#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x401545#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x61546#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x801547#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x71548#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1001549#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x81550#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2001551#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x91552#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x4001553#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa1554#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x8001555#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb1556#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x10001557#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc1558#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x20001559#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd1560#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x31561#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x01562#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff1563#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x01564#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x21565#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x11566#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x41567#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x21568#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x81569#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x31570#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x101571#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x41572#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe01573#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x51574#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x20001575#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd1576#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x40001577#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe1578#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x80001579#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf1580#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x100001581#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x101582#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x200001583#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x111584#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x400001585#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x121586#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x800001587#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x131588#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x1000001589#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x141590#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x2000001591#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x151592#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x4000001593#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x161594#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x11595#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x01596#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x21597#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x11598#define MC_HUB_WDP_BP__ENABLE_MASK 0x11599#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x01600#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe1601#define MC_HUB_WDP_BP__RDRET__SHIFT 0x11602#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc00001603#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x121604#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x11605#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x01606#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x21607#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x11608#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x41609#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x21610#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x81611#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x31612#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x101613#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x41614#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x201615#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x51616#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x401617#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x61618#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x801619#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x71620#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x1001621#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x81622#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x2001623#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x91624#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x4001625#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa1626#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x8001627#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb1628#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x10001629#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc1630#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x20001631#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd1632#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x40001633#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe1634#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x80001635#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf1636#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x100001637#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x101638#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x200001639#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x111640#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x400001641#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x121642#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800001643#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x131644#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x1000001645#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x141646#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x2000001647#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x151648#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000001649#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x161650#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x11651#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x01652#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x21653#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x11654#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x41655#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x21656#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x81657#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x31658#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x101659#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x41660#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x201661#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x51662#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x401663#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x61664#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x801665#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x71666#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x1001667#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x81668#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x2001669#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x91670#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x4001671#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa1672#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x8001673#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb1674#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x10001675#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc1676#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x20001677#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd1678#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x40001679#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe1680#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x80001681#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf1682#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x11683#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x01684#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x21685#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x11686#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x41687#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x21688#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x81689#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x31690#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x101691#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x41692#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x201693#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x51694#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x401695#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x61696#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x801697#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x71698#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x11699#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x01700#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x41701#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x21702#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x81703#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x31704#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x101705#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x41706#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x201707#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x51708#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x401709#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x61710#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x801711#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x71712#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x1001713#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x81714#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x2001715#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x91716#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x4001717#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa1718#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x8001719#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb1720#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x10001721#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc1722#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x20001723#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd1724#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc0001725#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe1726#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000001727#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x151728#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000001729#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x161730#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x8000001731#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x171732#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x10000001733#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x181734#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x20000001735#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x191736#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x11737#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x01738#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe1739#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x11740#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x2000001741#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x151742#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc000001743#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x161744#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x400000001745#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e1746#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x800000001747#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f1748#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x71749#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x01750#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x381751#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x31752#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c01753#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x61754#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe001755#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x91756#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x70001757#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc1758#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x380001759#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf1760#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c00001761#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x121762#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe000001763#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x151764#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x71765#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x01766#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x381767#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x31768#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c01769#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x61770#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe001771#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x91772#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x70001773#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc1774#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x380001775#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf1776#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c00001777#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x121778#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe000001779#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x151780#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff1781#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x01782#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff001783#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x81784#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff00001785#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x101786#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff0000001787#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x181788#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff1789#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x01790#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff001791#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x81792#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf1793#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x01794#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf01795#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x41796#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff001797#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x81798#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x100001799#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x101800#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe00001801#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x111802#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf1803#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x01804#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf01805#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x41806#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff001807#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x81808#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x100001809#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x101810#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe00001811#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x111812#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff1813#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x01814#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff001815#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x81816#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff00001817#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x101818#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff0000001819#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x181820#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff1821#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x01822#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff001823#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x81824#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f1825#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x01826#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f00001827#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x101828#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f0000001829#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x181830#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x11831#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x01832#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x21833#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x11834#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x41835#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x21836#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x81837#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x31838#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x101839#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x41840#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x201841#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x51842#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x401843#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x61844#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x801845#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x71846#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x1001847#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x81848#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x2001849#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x91850#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x4001851#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa1852#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x8001853#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb1854#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x10001855#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc1856#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x20001857#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd1858#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x40001859#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe1860#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x80001861#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf1862#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x100001863#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x101864#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x200001865#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x111866#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x400001867#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x121868#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x800001869#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x131870#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x1000001871#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x141872#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x2000001873#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x151874#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x4000001875#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x161876#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x8000001877#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x171878#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x10000001879#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x181880#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x20000001881#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x191882#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x40000001883#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a1884#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x80000001885#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b1886#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x100000001887#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c1888#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x200000001889#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d1890#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x400000001891#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1e1892#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x800000001893#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1f1894#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x31895#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x01896#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c1897#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x21898#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x31899#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x01900#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c1901#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x21902#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x11903#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x01904#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe1905#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x11906#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe001907#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x91908#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe00001909#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x111910#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f0000001911#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x181912#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x11913#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x01914#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe1915#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x11916#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe001917#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x91918#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe00001919#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x111920#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f0000001921#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x181922#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x11923#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x01924#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe1925#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x11926#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe001927#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x91928#define MC_HUB_WDP_SH2__ENABLE_MASK 0x11929#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x01930#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x61931#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x11932#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x81933#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x31934#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x301935#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x41936#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x401937#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x61938#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x7801939#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x71940#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x78001941#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb1942#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x80001943#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf1944#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x100001945#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x101946#define MC_HUB_WDP_SH3__ENABLE_MASK 0x11947#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x01948#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x61949#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x11950#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x81951#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x31952#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x301953#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x41954#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x401955#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x61956#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x7801957#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x71958#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x78001959#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb1960#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x80001961#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf1962#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x100001963#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x101964#define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x11965#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x01966#define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x61967#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x11968#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x81969#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x31970#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x301971#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x41972#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x401973#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x61974#define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x7801975#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x71976#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x78001977#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb1978#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x80001979#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf1980#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE_MASK 0x100001981#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x101982#define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x11983#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x01984#define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x61985#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x11986#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x81987#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x31988#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x301989#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x41990#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x401991#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x61992#define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x7801993#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x71994#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x78001995#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb1996#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x80001997#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf1998#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE_MASK 0x100001999#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102000#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x12001#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x02002#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x22003#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x12004#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x42005#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x22006#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x782007#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x32008#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x7802009#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x72010#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f8002011#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb2012#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc00002013#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x122014#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe0000002015#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x192016#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x12017#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x02018#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x22019#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x12020#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x42021#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x22022#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x782023#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x32024#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x7802025#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x72026#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f8002027#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb2028#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc00002029#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x122030#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe0000002031#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x192032#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x12033#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x02034#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x22035#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x12036#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x42037#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x22038#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x782039#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x32040#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x7802041#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x72042#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f8002043#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb2044#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc00002045#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x122046#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe0000002047#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x192048#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x12049#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x02050#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x22051#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x12052#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x42053#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x22054#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x782055#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x32056#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x7802057#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x72058#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f8002059#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb2060#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc00002061#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x122062#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe0000002063#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x192064#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f2065#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x02066#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x802067#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x72068#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f002069#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x82070#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff2071#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x02072#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff002073#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x82074#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff2075#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x02076#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff002077#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x82078#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x12079#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x02080#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x62081#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x12082#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x82083#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x32084#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x302085#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x42086#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x402087#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x62088#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x7802089#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x72090#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x78002091#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb2092#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x80002093#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf2094#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x100002095#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102096#define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x12097#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x02098#define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x62099#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x12100#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x82101#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x32102#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x302103#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x42104#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x402105#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x62106#define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x7802107#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x72108#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x78002109#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb2110#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x80002111#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf2112#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x100002113#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102114#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x12115#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x02116#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x62117#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x12118#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x82119#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x32120#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x302121#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x42122#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x402123#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x62124#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x7802125#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x72126#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x78002127#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb2128#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x80002129#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf2130#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x100002131#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102132#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x12133#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x02134#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x62135#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x12136#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x82137#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x32138#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x302139#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x42140#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x402141#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x62142#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x7802143#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x72144#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x78002145#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb2146#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x80002147#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf2148#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x100002149#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102150#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x12151#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x02152#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x62153#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x12154#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x82155#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x32156#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x302157#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x42158#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x402159#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x62160#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x7802161#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x72162#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x78002163#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb2164#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x80002165#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf2166#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x100002167#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102168#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x12169#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x02170#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x62171#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x12172#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x82173#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x32174#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x302175#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x42176#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x402177#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x62178#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x7802179#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x72180#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x78002181#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb2182#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x80002183#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf2184#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x100002185#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102186#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x12187#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x02188#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x62189#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x12190#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x82191#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x32192#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x302193#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x42194#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x402195#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x62196#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x7802197#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x72198#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x78002199#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb2200#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x80002201#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf2202#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x100002203#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102204#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x12205#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x02206#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x62207#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x12208#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x82209#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x32210#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x302211#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x42212#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x402213#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x62214#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x7802215#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x72216#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x78002217#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb2218#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x80002219#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf2220#define MC_HUB_RDREQ_VCE__VM_BYPASS_MASK 0x100002221#define MC_HUB_RDREQ_VCE__VM_BYPASS__SHIFT 0x102222#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x200002223#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x112224#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x12225#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x02226#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x62227#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x12228#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x82229#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x32230#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x302231#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x42232#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x402233#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x62234#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x7802235#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x72236#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x78002237#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb2238#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x80002239#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf2240#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x100002241#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x102242#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x200002243#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x112244#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x12245#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x02246#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x62247#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x12248#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x82249#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x32250#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x302251#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x42252#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x402253#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x62254#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x7802255#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x72256#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x78002257#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb2258#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x80002259#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf2260#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x100002261#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x102262#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x200002263#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x112264#define MC_HUB_RDREQ_IA__ENABLE_MASK 0x12265#define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x02266#define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x62267#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x12268#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x82269#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x32270#define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x302271#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x42272#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x402273#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x62274#define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x7802275#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x72276#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x78002277#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb2278#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x80002279#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf2280#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE_MASK 0x100002281#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102282#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x12283#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x02284#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x62285#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x12286#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x82287#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x32288#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x302289#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x42290#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x402291#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x62292#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x7802293#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x72294#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x78002295#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb2296#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x80002297#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf2298#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x100002299#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102300#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x12301#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x02302#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x62303#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x12304#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x82305#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x32306#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x302307#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x42308#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x402309#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x62310#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x7802311#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x72312#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x78002313#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb2314#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x80002315#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf2316#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x100002317#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102318#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x12319#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x02320#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x62321#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x12322#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x82323#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x32324#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x302325#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x42326#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x402327#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x62328#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x7802329#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x72330#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x78002331#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb2332#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x80002333#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf2334#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x100002335#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102336#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x12337#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x02338#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x62339#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x12340#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x82341#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x32342#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x302343#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x42344#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x402345#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x62346#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x7802347#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x72348#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x78002349#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb2350#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x80002351#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf2352#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x100002353#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102354#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x12355#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x02356#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x22357#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x12358#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x42359#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x22360#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x782361#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x32362#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f802363#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x72364#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e0002365#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd2366#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe00002367#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x112368#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f0000002369#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x182370#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x12371#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x02372#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x22373#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x12374#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x42375#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x22376#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x782377#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x32378#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f802379#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x72380#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e0002381#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd2382#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe00002383#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x112384#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f0000002385#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x182386#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x12387#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x02388#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x22389#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x12390#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x42391#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x22392#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x782393#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x32394#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f802395#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x72396#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e0002397#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd2398#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe00002399#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x112400#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f0000002401#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x182402#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x12403#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x02404#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x22405#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x12406#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x42407#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x22408#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x782409#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x32410#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f802411#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x72412#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e0002413#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd2414#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe00002415#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x112416#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f0000002417#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x182418#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x32419#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x02420#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc2421#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x22422#define MC_HUB_WDP_CPG__ENABLE_MASK 0x12423#define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x02424#define MC_HUB_WDP_CPG__PRESCALE_MASK 0x62425#define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x12426#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x82427#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x32428#define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x302429#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x42430#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x402431#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x62432#define MC_HUB_WDP_CPG__MAXBURST_MASK 0x7802433#define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x72434#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x78002435#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb2436#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x80002437#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf2438#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x100002439#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102440#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x12441#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x02442#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x62443#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x12444#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x82445#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x32446#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x302447#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x42448#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x402449#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x62450#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x7802451#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x72452#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x78002453#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb2454#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x80002455#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf2456#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x100002457#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102458#define MC_HUB_WDP_SH0__ENABLE_MASK 0x12459#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x02460#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x62461#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x12462#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x82463#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x32464#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x302465#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x42466#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x402467#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x62468#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x7802469#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x72470#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x78002471#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb2472#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x80002473#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf2474#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x100002475#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102476#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x12477#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x02478#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x62479#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x12480#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x82481#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x32482#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x302483#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x42484#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x402485#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x62486#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x7802487#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x72488#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x78002489#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb2490#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x80002491#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf2492#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x100002493#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102494#define MC_HUB_WDP_VCE__ENABLE_MASK 0x12495#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x02496#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x62497#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x12498#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x82499#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x32500#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x302501#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x42502#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x402503#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x62504#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x7802505#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x72506#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x78002507#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb2508#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x80002509#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf2510#define MC_HUB_WDP_VCE__VM_BYPASS_MASK 0x100002511#define MC_HUB_WDP_VCE__VM_BYPASS__SHIFT 0x102512#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x200002513#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x112514#define MC_HUB_WDP_XDP__ENABLE_MASK 0x12515#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x02516#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x62517#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x12518#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x82519#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x32520#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x302521#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x42522#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x402523#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x62524#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x7802525#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x72526#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x78002527#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb2528#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x80002529#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf2530#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x100002531#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102532#define MC_HUB_WDP_IH__ENABLE_MASK 0x12533#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x02534#define MC_HUB_WDP_IH__PRESCALE_MASK 0x62535#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x12536#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x82537#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x32538#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x302539#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x42540#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x402541#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x62542#define MC_HUB_WDP_IH__MAXBURST_MASK 0x7802543#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x72544#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x78002545#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb2546#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x80002547#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf2548#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x100002549#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102550#define MC_HUB_WDP_RLC__ENABLE_MASK 0x12551#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x02552#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x62553#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x12554#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x82555#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x32556#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x302557#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x42558#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x402559#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x62560#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x7802561#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x72562#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x78002563#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb2564#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x80002565#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf2566#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x100002567#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102568#define MC_HUB_WDP_SEM__ENABLE_MASK 0x12569#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x02570#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x62571#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x12572#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x82573#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x32574#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x302575#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x42576#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x402577#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x62578#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x7802579#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x72580#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x78002581#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb2582#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x80002583#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf2584#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x100002585#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102586#define MC_HUB_WDP_SMU__ENABLE_MASK 0x12587#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x02588#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x62589#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x12590#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x82591#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x32592#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x302593#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x42594#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x402595#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x62596#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x7802597#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x72598#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x78002599#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb2600#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x80002601#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf2602#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x100002603#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102604#define MC_HUB_WDP_SH1__ENABLE_MASK 0x12605#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x02606#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x62607#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x12608#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x82609#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x32610#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x302611#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x42612#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x402613#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x62614#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x7802615#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x72616#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x78002617#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb2618#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x80002619#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf2620#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x100002621#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102622#define MC_HUB_WDP_UMC__ENABLE_MASK 0x12623#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x02624#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x62625#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x12626#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x82627#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x32628#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x302629#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x42630#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x402631#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x62632#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x7802633#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x72634#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x78002635#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb2636#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x80002637#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf2638#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x100002639#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102640#define MC_HUB_WDP_UVD__ENABLE_MASK 0x12641#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x02642#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x62643#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x12644#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x82645#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x32646#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x302647#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x42648#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x402649#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x62650#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x7802651#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x72652#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x78002653#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb2654#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x80002655#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf2656#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x100002657#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x102658#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x200002659#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x112660#define MC_HUB_WDP_HDP__ENABLE_MASK 0x12661#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x02662#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x62663#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x12664#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x82665#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x32666#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x302667#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x42668#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x402669#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x62670#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x7802671#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x72672#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x78002673#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb2674#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x80002675#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf2676#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x100002677#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102678#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x12679#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x02680#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x62681#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x12682#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x82683#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x32684#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x302685#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x42686#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x402687#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x62688#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x7802689#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x72690#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x78002691#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb2692#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x80002693#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf2694#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x100002695#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102696#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x12697#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x02698#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe2699#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x12700#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x12701#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x02702#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe2703#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x12704#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x12705#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x02706#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe2707#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x12708#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x12709#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x02710#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe2711#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x12712#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x12713#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x02714#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x62715#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x12716#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x82717#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x32718#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x302719#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x42720#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x402721#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x62722#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x7802723#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x72724#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x78002725#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb2726#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x80002727#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf2728#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x100002729#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102730#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x12731#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x02732#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x62733#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x12734#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x82735#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x32736#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x302737#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x42738#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x402739#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x62740#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x7802741#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x72742#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x78002743#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb2744#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x80002745#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf2746#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x100002747#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102748#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x12749#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x02750#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x62751#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x12752#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x82753#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x32754#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x302755#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x42756#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x402757#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x62758#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x7802759#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x72760#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x78002761#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb2762#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x80002763#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf2764#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x100002765#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102766#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x12767#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x02768#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x62769#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x12770#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x82771#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x32772#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x302773#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x42774#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x402775#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x62776#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x7802777#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x72778#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x78002779#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb2780#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x80002781#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf2782#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x100002783#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102784#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x12785#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x02786#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x62787#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x12788#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x82789#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x32790#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x302791#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x42792#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x402793#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x62794#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x7802795#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x72796#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x78002797#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb2798#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x80002799#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf2800#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x100002801#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102802#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x200002803#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x112804#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x400002805#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x122806#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f800002807#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x132808#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x12809#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x02810#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x62811#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x12812#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x82813#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x32814#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x302815#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x42816#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x402817#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x62818#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x7802819#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x72820#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x78002821#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb2822#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x80002823#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf2824#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x100002825#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102826#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x200002827#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x112828#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x400002829#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x122830#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f800002831#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x132832#define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x12833#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x02834#define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x62835#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x12836#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x82837#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x32838#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x302839#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x42840#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x402841#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x62842#define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x7802843#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x72844#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x78002845#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb2846#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x80002847#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf2848#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x100002849#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102850#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x12851#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x02852#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x62853#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x12854#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x82855#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x32856#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x302857#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x42858#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x402859#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x62860#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x7802861#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x72862#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x78002863#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb2864#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x80002865#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf2866#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x100002867#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102868#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x200002869#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x112870#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x400002871#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x122872#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f800002873#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x132874#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x12875#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x02876#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x62877#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x12878#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x82879#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x32880#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x302881#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x42882#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x402883#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x62884#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x7802885#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x72886#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x78002887#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb2888#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x80002889#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf2890#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x100002891#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102892#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x200002893#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x112894#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x400002895#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x122896#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f800002897#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x132898#define MC_HUB_WDP_SAM__ENABLE_MASK 0x12899#define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x02900#define MC_HUB_WDP_SAM__PRESCALE_MASK 0x62901#define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x12902#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x82903#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x32904#define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x302905#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x42906#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x402907#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x62908#define MC_HUB_WDP_SAM__MAXBURST_MASK 0x7802909#define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x72910#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x78002911#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb2912#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x80002913#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf2914#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x100002915#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102916#define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x12917#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x02918#define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x62919#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x12920#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x82921#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x32922#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x302923#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x42924#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x402925#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x62926#define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x7802927#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x72928#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x78002929#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb2930#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x80002931#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf2932#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x100002933#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102934#define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x12935#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x02936#define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x62937#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x12938#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x82939#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x32940#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x302941#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x42942#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x402943#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x62944#define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x7802945#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x72946#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x78002947#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb2948#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x80002949#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf2950#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x100002951#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102952#define MC_HUB_WDP_CPC__ENABLE_MASK 0x12953#define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x02954#define MC_HUB_WDP_CPC__PRESCALE_MASK 0x62955#define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x12956#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x82957#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x32958#define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x302959#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x42960#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x402961#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x62962#define MC_HUB_WDP_CPC__MAXBURST_MASK 0x7802963#define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x72964#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x78002965#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb2966#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x80002967#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf2968#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x100002969#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102970#define MC_HUB_WDP_CPF__ENABLE_MASK 0x12971#define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x02972#define MC_HUB_WDP_CPF__PRESCALE_MASK 0x62973#define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x12974#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x82975#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x32976#define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x302977#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x42978#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x402979#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x62980#define MC_HUB_WDP_CPF__MAXBURST_MASK 0x7802981#define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x72982#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x78002983#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb2984#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x80002985#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf2986#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x100002987#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x102988#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x12989#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x02990#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x62991#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x12992#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x82993#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x32994#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x302995#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x42996#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x402997#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x62998#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x7802999#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x73000#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x78003001#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb3002#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x80003003#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf3004#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x100003005#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x103006#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x200003007#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x113008#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x400003009#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x123010#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f800003011#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x133012#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x13013#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x03014#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x63015#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x13016#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x83017#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x33018#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x303019#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x43020#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x403021#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x63022#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x7803023#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x73024#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x78003025#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb3026#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x80003027#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf3028#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x100003029#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x103030#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x200003031#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x113032#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x400003033#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x123034#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f800003035#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x133036#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x13037#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x03038#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x63039#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x13040#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x83041#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x33042#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x303043#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x43044#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x403045#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x63046#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x7803047#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x73048#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x78003049#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb3050#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x80003051#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf3052#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x100003053#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x103054#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x200003055#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x113056#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x400003057#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x123058#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f800003059#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x133060#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x13061#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x03062#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x63063#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x13064#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x83065#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x33066#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x303067#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x43068#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x403069#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x63070#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x7803071#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x73072#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x78003073#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb3074#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x80003075#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf3076#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x100003077#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x103078#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x200003079#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x113080#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x400003081#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x123082#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f800003083#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x133084#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x13085#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x03086#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x63087#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x13088#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x83089#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x33090#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x303091#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x43092#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x403093#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x63094#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x7803095#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x73096#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x78003097#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb3098#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x80003099#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf3100#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x100003101#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x103102#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x200003103#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x113104#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x400003105#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x123106#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f800003107#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x133108#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x13109#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x03110#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x63111#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x13112#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x83113#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x33114#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x303115#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x43116#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x403117#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x63118#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x7803119#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x73120#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x78003121#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb3122#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x80003123#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf3124#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x100003125#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x103126#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x200003127#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x113128#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x400003129#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x123130#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f800003131#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x133132#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x13133#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x03134#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x63135#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x13136#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x83137#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x33138#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x303139#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x43140#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x403141#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x63142#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x7803143#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x73144#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x78003145#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb3146#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x80003147#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf3148#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x100003149#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x103150#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x200003151#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x113152#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x400003153#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x123154#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f800003155#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x133156#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x13157#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x03158#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x23159#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x13160#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x43161#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x23162#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x783163#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x33164#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x7803165#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x73166#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f8003167#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb3168#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc00003169#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x123170#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe0000003171#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x193172#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x13173#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x03174#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x23175#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x13176#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x43177#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x23178#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x783179#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x33180#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x7803181#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x73182#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f8003183#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb3184#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc00003185#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x123186#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe0000003187#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x193188#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x13189#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x03190#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x23191#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x13192#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x43193#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x23194#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x783195#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x33196#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x7803197#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x73198#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f8003199#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb3200#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc00003201#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x123202#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe0000003203#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x193204#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x13205#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x03206#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x23207#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x13208#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x43209#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x23210#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x783211#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x33212#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x7803213#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x73214#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f8003215#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb3216#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc00003217#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x123218#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe0000003219#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x193220#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x13221#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x03222#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x23223#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x13224#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x43225#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x23226#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x783227#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x33228#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f803229#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x73230#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e0003231#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd3232#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe00003233#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x113234#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f0000003235#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x183236#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x13237#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x03238#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x23239#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x13240#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x43241#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x23242#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x783243#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x33244#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f803245#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x73246#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e0003247#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd3248#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe00003249#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x113250#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f0000003251#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x183252#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x13253#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x03254#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x23255#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x13256#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x43257#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x23258#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x783259#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x33260#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f803261#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x73262#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e0003263#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd3264#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe00003265#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x113266#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f0000003267#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x183268#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x13269#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x03270#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x23271#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x13272#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x43273#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x23274#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x783275#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x33276#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f803277#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x73278#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e0003279#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd3280#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe00003281#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x113282#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f0000003283#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x183284#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x13285#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x03286#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe3287#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x13288#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x13289#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x03290#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe3291#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x13292#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x13293#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x03294#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe3295#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x13296#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x13297#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x03298#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe3299#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x13300#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f3301#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x03302#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f803303#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x73304#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f3305#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x03306#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f803307#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x73308#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f3309#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x03310#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f803311#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x73312#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f3313#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x03314#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f803315#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x73316#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f3317#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x03318#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f803319#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x73320#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f3321#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x03322#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f803323#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x73324#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f3325#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x03326#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f803327#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x73328#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f3329#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x03330#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f803331#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x73332#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff3333#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x03334#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x80003335#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf3336#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x100003337#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x103338#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x200003339#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x113340#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff3341#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x03342#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff003343#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x83344#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff3345#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x03346#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff003347#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x83348#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff000003349#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x143350#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff3351#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x03352#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff003353#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x83354#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff3355#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x03356#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff003357#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x83358#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff00003359#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x103360#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff3361#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x03362#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff003363#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x83364#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff3365#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x03366#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff003367#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x83368#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff00003369#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x103370#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff0000003371#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x183372#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x13373#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x03374#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x63375#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x13376#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x783377#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x33378#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x803379#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x73380#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff3381#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x03382#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff003383#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x83384#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff00003385#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x103386#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff0000003387#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x183388#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff3389#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x03390#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x1003391#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x83392#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x6003393#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x93394#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x18003395#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb3396#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x20003397#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd3398#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff3399#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x03400#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x3003401#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x83402#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc003403#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa3404#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x33405#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x03406#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x43407#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x23408#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x83409#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x33410#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x103411#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x43412#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e03413#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x53414#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e003415#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x93416#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c0003417#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe3418#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf800003419#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x133420#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f0000003421#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x183422#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff3423#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x03424#define MC_RPB_CID_QUEUE_EX__START_MASK 0x13425#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x03426#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e3427#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x13428#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff3429#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x03430#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff00003431#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x103432#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x13433#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x03434#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x63435#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x13436#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x83437#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x33438#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf03439#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x43440#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff003441#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x83442#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff00003443#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x103444#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff0000003445#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x183446#define MC_SHARED_CHMAP__CHAN0_MASK 0xf3447#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x03448#define MC_SHARED_CHMAP__CHAN1_MASK 0xf03449#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x43450#define MC_SHARED_CHMAP__CHAN2_MASK 0xf003451#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x83452#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf0003453#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc3454#define MC_SHARED_CHMAP__CHAN3_MASK 0xf00003455#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x103456#define MC_SHARED_CHMAP__CHAN4_MASK 0xf000003457#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x143458#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf3459#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x03460#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf03461#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x43462#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf003463#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x83464#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf0003465#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc3466#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf00003467#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x103468#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf000003469#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x143470#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf0000003471#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x183472#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf00000003473#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c3474#define MC_RD_GRP_GFX__CP_MASK 0xf3475#define MC_RD_GRP_GFX__CP__SHIFT 0x03476#define MC_RD_GRP_GFX__SH_MASK 0xf03477#define MC_RD_GRP_GFX__SH__SHIFT 0x43478#define MC_RD_GRP_GFX__IA_MASK 0xf003479#define MC_RD_GRP_GFX__IA__SHIFT 0x83480#define MC_RD_GRP_GFX__ACPG_MASK 0xf0003481#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc3482#define MC_RD_GRP_GFX__ACPO_MASK 0xf00003483#define MC_RD_GRP_GFX__ACPO__SHIFT 0x103484#define MC_RD_GRP_GFX__ISP_MASK 0xf000003485#define MC_RD_GRP_GFX__ISP__SHIFT 0x143486#define MC_RD_GRP_GFX__XDMAM_MASK 0xf0000003487#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x183488#define MC_WR_GRP_GFX__CP_MASK 0xf3489#define MC_WR_GRP_GFX__CP__SHIFT 0x03490#define MC_WR_GRP_GFX__SH_MASK 0xf03491#define MC_WR_GRP_GFX__SH__SHIFT 0x43492#define MC_WR_GRP_GFX__ACPG_MASK 0xf003493#define MC_WR_GRP_GFX__ACPG__SHIFT 0x83494#define MC_WR_GRP_GFX__ACPO_MASK 0xf0003495#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc3496#define MC_WR_GRP_GFX__ISP_MASK 0xf00003497#define MC_WR_GRP_GFX__ISP__SHIFT 0x103498#define MC_WR_GRP_GFX__XDMA_MASK 0xf000003499#define MC_WR_GRP_GFX__XDMA__SHIFT 0x143500#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000003501#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x183502#define MC_RD_GRP_SYS__RLC_MASK 0xf3503#define MC_RD_GRP_SYS__RLC__SHIFT 0x03504#define MC_RD_GRP_SYS__VMC_MASK 0xf03505#define MC_RD_GRP_SYS__VMC__SHIFT 0x43506#define MC_RD_GRP_SYS__SDMA1_MASK 0xf003507#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x83508#define MC_RD_GRP_SYS__DMIF_MASK 0xf0003509#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc3510#define MC_RD_GRP_SYS__MCIF_MASK 0xf00003511#define MC_RD_GRP_SYS__MCIF__SHIFT 0x103512#define MC_RD_GRP_SYS__SMU_MASK 0xf000003513#define MC_RD_GRP_SYS__SMU__SHIFT 0x143514#define MC_RD_GRP_SYS__VCE_MASK 0xf0000003515#define MC_RD_GRP_SYS__VCE__SHIFT 0x183516#define MC_RD_GRP_SYS__VCEU_MASK 0xf00000003517#define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c3518#define MC_WR_GRP_SYS__IH_MASK 0xf3519#define MC_WR_GRP_SYS__IH__SHIFT 0x03520#define MC_WR_GRP_SYS__MCIF_MASK 0xf03521#define MC_WR_GRP_SYS__MCIF__SHIFT 0x43522#define MC_WR_GRP_SYS__RLC_MASK 0xf003523#define MC_WR_GRP_SYS__RLC__SHIFT 0x83524#define MC_WR_GRP_SYS__SAM_MASK 0xf0003525#define MC_WR_GRP_SYS__SAM__SHIFT 0xc3526#define MC_WR_GRP_SYS__SMU_MASK 0xf00003527#define MC_WR_GRP_SYS__SMU__SHIFT 0x103528#define MC_WR_GRP_SYS__SDMA1_MASK 0xf000003529#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x143530#define MC_WR_GRP_SYS__VCE_MASK 0xf0000003531#define MC_WR_GRP_SYS__VCE__SHIFT 0x183532#define MC_WR_GRP_SYS__VCEU_MASK 0xf00000003533#define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c3534#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf3535#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x03536#define MC_RD_GRP_OTH__SDMA0_MASK 0xf03537#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x43538#define MC_RD_GRP_OTH__HDP_MASK 0xf003539#define MC_RD_GRP_OTH__HDP__SHIFT 0x83540#define MC_RD_GRP_OTH__SEM_MASK 0xf0003541#define MC_RD_GRP_OTH__SEM__SHIFT 0xc3542#define MC_RD_GRP_OTH__UMC_MASK 0xf00003543#define MC_RD_GRP_OTH__UMC__SHIFT 0x103544#define MC_RD_GRP_OTH__UVD_MASK 0xf000003545#define MC_RD_GRP_OTH__UVD__SHIFT 0x143546#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf0000003547#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x183548#define MC_RD_GRP_OTH__SAM_MASK 0xf00000003549#define MC_RD_GRP_OTH__SAM__SHIFT 0x1c3550#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf3551#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x03552#define MC_WR_GRP_OTH__SDMA0_MASK 0xf03553#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x43554#define MC_WR_GRP_OTH__HDP_MASK 0xf003555#define MC_WR_GRP_OTH__HDP__SHIFT 0x83556#define MC_WR_GRP_OTH__SEM_MASK 0xf0003557#define MC_WR_GRP_OTH__SEM__SHIFT 0xc3558#define MC_WR_GRP_OTH__UMC_MASK 0xf00003559#define MC_WR_GRP_OTH__UMC__SHIFT 0x103560#define MC_WR_GRP_OTH__UVD_MASK 0xf000003561#define MC_WR_GRP_OTH__UVD__SHIFT 0x143562#define MC_WR_GRP_OTH__XDP_MASK 0xf0000003563#define MC_WR_GRP_OTH__XDP__SHIFT 0x183564#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf00000003565#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c3566#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff3567#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x03568#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff00003569#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x103570#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff3571#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x03572#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff3573#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x03574#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff3575#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x03576#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff3577#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x03578#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff3579#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x03580#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff3581#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x03582#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x33583#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x03584#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc3585#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x23586#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x303587#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x43588#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc03589#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x63590#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x1003591#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x83592#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x2003593#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x93594#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff3595#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x03596#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff3597#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x03598#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff3599#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x03600#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff3601#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x03602#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff3603#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x03604#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff3605#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x03606#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff3607#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x03608#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff3609#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x03610#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x13611#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x03612#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x23613#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x13614#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x183615#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x33616#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x203617#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x53618#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x403619#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x63620#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x7803621#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x73622#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff3623#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x03624#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x33625#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x03626#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf3627#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x03628#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf03629#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x43630#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf003631#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x83632#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf0003633#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc3634#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf00003635#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x103636#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf000003637#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x143638#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf0000003639#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x183640#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf00000003641#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c3642#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x13643#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x03644#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x23645#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x13646#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x43647#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x23648#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x83649#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x33650#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x103651#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x43652#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x203653#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x53654#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x403655#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x63656#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x803657#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x73658#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x7003659#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x83660#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x8003661#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb3662#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x10003663#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc3664#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x20003665#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd3666#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x800000003667#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f3668#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x13669#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x03670#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x23671#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x13672#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x43673#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x23674#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x83675#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x33676#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x103677#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x43678#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x203679#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x53680#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x403681#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x63682#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x803683#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x73684#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x7003685#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x83686#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x8003687#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb3688#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe0003689#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd3690#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f3691#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x03692#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc03693#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x63694#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x73695#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x03696#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x13697#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x03698#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x1003699#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x83700#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe003701#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x93702#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x70003703#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc3704#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x780003705#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf3706#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x800003707#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x133708#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x13709#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x03710#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x1003711#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x83712#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe003713#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x93714#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x70003715#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc3716#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x780003717#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf3718#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x800003719#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x133720#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x13721#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x03722#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x13723#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x03724#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x13725#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x03726#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f3727#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x03728#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x13729#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x03730#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x1003731#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x83732#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe003733#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x93734#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x70003735#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc3736#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x780003737#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf3738#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x800003739#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x133740#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x13741#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x03742#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x13743#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x03744#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x1003745#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x83746#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe003747#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x93748#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x70003749#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc3750#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x780003751#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf3752#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x800003753#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x133754#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x13755#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x03756#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x1003757#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x83758#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe003759#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x93760#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x70003761#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc3762#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x780003763#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf3764#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x800003765#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x133766#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x13767#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x03768#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x1003769#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x83770#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe003771#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x93772#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x70003773#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc3774#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x780003775#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf3776#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x800003777#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x133778#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x13779#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x03780#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x13781#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x03782#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x13783#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x03784#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f3785#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x03786#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x13787#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x03788#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x1003789#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x83790#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe003791#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x93792#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x70003793#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc3794#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x780003795#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf3796#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x800003797#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x133798#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x13799#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x03800#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff3801#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x03802#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff3803#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x03804#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff3805#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x03806#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff3807#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x03808#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff3809#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x03810#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff3811#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x03812#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff3813#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x03814#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff3815#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x03816#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff3817#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x03818#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff3819#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x03820#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff3821#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x03822#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff3823#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x03824#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff3825#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x03826#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff3827#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x03828#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x13829#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x03830#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe3831#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x13832#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf000003833#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x143834#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x10000003835#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x183836#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x20000003837#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x193838#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c0000003839#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a3840#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x13841#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x03842#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe3843#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x13844#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf000003845#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x143846#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x10000003847#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x183848#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x20000003849#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x193850#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c0000003851#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a3852#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x13853#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x03854#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe3855#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x13856#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf000003857#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x143858#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x10000003859#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x183860#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x20000003861#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x193862#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c0000003863#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a3864#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x13865#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x03866#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe3867#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x13868#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf000003869#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x143870#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x10000003871#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x183872#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x20000003873#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x193874#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c0000003875#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a3876#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x13877#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x03878#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe3879#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x13880#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf000003881#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x143882#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x10000003883#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x183884#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x20000003885#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x193886#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c0000003887#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a3888#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x13889#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x03890#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe3891#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x13892#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf000003893#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x143894#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x10000003895#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x183896#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x20000003897#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x193898#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c0000003899#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a3900#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x13901#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x03902#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe3903#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x13904#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf000003905#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x143906#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x10000003907#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x183908#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x20000003909#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x193910#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c0000003911#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a3912#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x13913#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x03914#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe3915#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x13916#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf000003917#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x143918#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x10000003919#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x183920#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x20000003921#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x193922#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c0000003923#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a3924#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x13925#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x03926#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe3927#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x13928#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf000003929#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x143930#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x10000003931#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x183932#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x20000003933#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x193934#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c0000003935#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a3936#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x13937#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x03938#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe3939#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x13940#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf000003941#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x143942#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x10000003943#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x183944#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x20000003945#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x193946#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c0000003947#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a3948#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x13949#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x03950#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe3951#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x13952#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf000003953#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x143954#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x10000003955#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x183956#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x20000003957#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x193958#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c0000003959#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a3960#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x13961#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x03962#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe3963#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x13964#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf000003965#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x143966#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x10000003967#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x183968#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x20000003969#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x193970#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c0000003971#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a3972#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x13973#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x03974#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe3975#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x13976#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf000003977#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x143978#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x10000003979#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x183980#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x20000003981#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x193982#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c0000003983#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a3984#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x13985#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x03986#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe3987#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x13988#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf000003989#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x143990#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x10000003991#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x183992#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x20000003993#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x193994#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c0000003995#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a3996#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf3997#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x03998#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x703999#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x44000#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x3804001#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x74002#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c004003#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa4004#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c0004005#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe4006#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf4007#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x04008#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x704009#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x44010#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x3804011#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x74012#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c004013#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa4014#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c0004015#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe4016#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf4017#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x04018#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x704019#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x44020#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x3804021#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x74022#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c004023#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa4024#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c0004025#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe4026#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf4027#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x04028#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x704029#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x44030#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x3804031#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x74032#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c004033#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa4034#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c0004035#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe4036#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf4037#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x04038#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x704039#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x44040#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x3804041#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x74042#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c004043#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa4044#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c0004045#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe4046#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf4047#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x04048#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x704049#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x44050#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x3804051#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x74052#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c004053#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa4054#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c0004055#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe4056#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf4057#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x04058#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x704059#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x44060#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x3804061#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x74062#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c004063#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa4064#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c0004065#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe4066#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf4067#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x04068#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x704069#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x44070#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x3804071#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x74072#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c004073#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa4074#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c0004075#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe4076#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf4077#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x04078#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x704079#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x44080#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x3804081#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x74082#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c004083#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa4084#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c0004085#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe4086#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf4087#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x04088#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x704089#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x44090#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x3804091#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x74092#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c004093#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa4094#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c0004095#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe4096#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf4097#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x04098#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x704099#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x44100#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x3804101#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x74102#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c004103#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa4104#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c0004105#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe4106#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf4107#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x04108#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x704109#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x44110#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x3804111#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x74112#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c004113#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa4114#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c0004115#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe4116#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf4117#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x04118#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x704119#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x44120#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x3804121#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x74122#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c004123#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa4124#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c0004125#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe4126#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf4127#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x04128#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x704129#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x44130#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x3804131#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x74132#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c004133#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa4134#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c0004135#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe4136#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf4137#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x04138#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x704139#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x44140#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x3804141#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x74142#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c004143#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa4144#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c0004145#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe4146#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf4147#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x04148#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x704149#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x44150#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x3804151#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x74152#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c004153#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa4154#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c0004155#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe4156#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf4157#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x04158#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x704159#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x44160#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x3804161#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x74162#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c004163#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa4164#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c0004165#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe4166#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf4167#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x04168#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x704169#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x44170#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x3804171#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x74172#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c004173#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa4174#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c0004175#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe4176#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf4177#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x04178#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x704179#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x44180#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x3804181#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x74182#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c004183#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa4184#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c0004185#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe4186#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf4187#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x04188#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x704189#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x44190#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x3804191#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x74192#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c004193#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa4194#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c0004195#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe4196#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff4197#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x04198#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff004199#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x84200#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x100004201#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x104202#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe00004203#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x114204#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x20000004205#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x194206#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff4207#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x04208#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc004209#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa4210#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f000004211#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x144212#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc0000004213#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a4214#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f4215#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x04216#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc04217#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x64218#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f0004219#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc4220#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f4221#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x04222#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc04223#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x64224#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f0004225#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc4226#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff4227#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x04228#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f00004229#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x104230#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f8000004231#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x174232#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff4233#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x04234#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x300004235#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x104236#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc00004237#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x124238#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf4239#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x04240#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x304241#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x44242#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x404243#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x64244#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x804245#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x74246#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x1004247#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x84248#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x2004249#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x94250#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x4004251#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa4252#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x8004253#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb4254#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x10004255#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc4256#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf4257#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x04258#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf04259#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x44260#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf004261#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x84262#define MC_XPB_P2P_BAR0__VALID_MASK 0x10004263#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc4264#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x20004265#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd4266#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x40004267#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe4268#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x80004269#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf4270#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff00004271#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x104272#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf4273#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x04274#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf04275#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x44276#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf004277#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x84278#define MC_XPB_P2P_BAR1__VALID_MASK 0x10004279#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc4280#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x20004281#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd4282#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x40004283#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe4284#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x80004285#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf4286#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff00004287#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x104288#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf4289#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x04290#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf04291#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x44292#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf004293#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x84294#define MC_XPB_P2P_BAR2__VALID_MASK 0x10004295#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc4296#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x20004297#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd4298#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x40004299#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe4300#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x80004301#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf4302#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff00004303#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x104304#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf4305#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x04306#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf04307#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x44308#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf004309#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x84310#define MC_XPB_P2P_BAR3__VALID_MASK 0x10004311#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc4312#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x20004313#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd4314#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x40004315#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe4316#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x80004317#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf4318#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff00004319#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x104320#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf4321#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x04322#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf04323#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x44324#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf004325#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x84326#define MC_XPB_P2P_BAR4__VALID_MASK 0x10004327#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc4328#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x20004329#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd4330#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x40004331#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe4332#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x80004333#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf4334#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff00004335#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x104336#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf4337#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x04338#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf04339#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x44340#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf004341#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x84342#define MC_XPB_P2P_BAR5__VALID_MASK 0x10004343#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc4344#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x20004345#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd4346#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x40004347#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe4348#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x80004349#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf4350#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff00004351#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x104352#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf4353#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x04354#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf04355#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x44356#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf004357#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x84358#define MC_XPB_P2P_BAR6__VALID_MASK 0x10004359#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc4360#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x20004361#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd4362#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x40004363#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe4364#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x80004365#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf4366#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff00004367#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x104368#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf4369#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x04370#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf04371#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x44372#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf004373#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x84374#define MC_XPB_P2P_BAR7__VALID_MASK 0x10004375#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc4376#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x20004377#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd4378#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x40004379#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe4380#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x80004381#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf4382#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff00004383#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x104384#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff4385#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x04386#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf004387#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x84388#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x10004389#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc4390#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x20004391#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd4392#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x40004393#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe4394#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x80004395#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf4396#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff00004397#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x104398#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff4399#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x04400#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf004401#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x84402#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf0004403#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc4404#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff4405#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x04406#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff004407#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x84408#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff4409#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x04410#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff004411#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x84412#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x14413#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x04414#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x24415#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x14416#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc4417#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x24418#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x14419#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x04420#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x24421#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x14422#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc4423#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x24424#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x14425#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x04426#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x24427#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x14428#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc4429#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x24430#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x14431#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x04432#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x24433#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x14434#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc4435#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x24436#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x14437#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x04438#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x24439#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x14440#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc4441#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x24442#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x14443#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x04444#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x24445#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x14446#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc4447#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x24448#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x14449#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x04450#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x24451#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x14452#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc4453#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x24454#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x14455#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x04456#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x24457#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x14458#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc4459#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x24460#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x14461#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x04462#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x24463#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x14464#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc4465#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x24466#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x14467#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x04468#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x24469#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x14470#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc4471#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x24472#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x14473#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x04474#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x24475#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x14476#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc4477#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x24478#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x14479#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x04480#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x24481#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x14482#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc4483#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x24484#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x14485#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x04486#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x24487#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x14488#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc4489#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x24490#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x14491#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x04492#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x24493#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x14494#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc4495#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x24496#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f4497#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x04498#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc04499#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x64500#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f0004501#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc4502#define MC_XPB_CLK_GAT__ENABLE_MASK 0x400004503#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x124504#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x800004505#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x134506#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff4507#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x04508#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff004509#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x84510#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f00004511#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x104512#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x8000004513#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x174514#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x10000004515#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x184516#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x20000004517#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x194518#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x40000004519#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a4520#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x180000004521#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b4522#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x200000004523#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d4524#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x400000004525#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e4526#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x800000004527#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f4528#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff4529#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x04530#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f004531#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x84532#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x80004533#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf4534#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x100004535#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x104536#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x200004537#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x114538#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x400004539#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x124540#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f800004541#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x134542#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x14543#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x04544#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe4545#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x14546#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f004547#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x84548#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x80004549#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf4550#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x100004551#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x104552#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x200004553#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x114554#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x400004555#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x124556#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x800004557#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x134558#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x1000004559#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x144560#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x2000004561#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x154562#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x4000004563#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x164564#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x8000004565#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x174566#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff0000004567#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x184568#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x14569#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x04570#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x24571#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x14572#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x44573#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x24574#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x84575#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x34576#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x104577#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x44578#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x204579#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x54580#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x404581#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x64582#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x804583#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x74584#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x1004585#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x84586#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x2004587#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x94588#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x4004589#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa4590#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x8004591#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb4592#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x10004593#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc4594#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x20004595#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd4596#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x40004597#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe4598#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x80004599#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf4600#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x100004601#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x104602#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x200004603#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x114604#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x400004605#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x124606#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x800004607#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x134608#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff4609#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x04610#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f4611#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x04612#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc04613#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x64614#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f0004615#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc4616#define MC_XPB_STICKY__BITS_MASK 0xffffffff4617#define MC_XPB_STICKY__BITS__SHIFT 0x04618#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff4619#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x04620#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff4621#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x04622#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff004623#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x84624#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff00004625#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x104626#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f0000004627#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x184628#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x800000004629#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f4630#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf4631#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x04632#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x704633#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x44634#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x3804635#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x74636#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c004637#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa4638#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c0004639#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe4640#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf4641#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x04642#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x704643#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x44644#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x3804645#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x74646#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c004647#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa4648#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c0004649#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe4650#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf4651#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x04652#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x704653#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x44654#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x3804655#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x74656#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c004657#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa4658#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c0004659#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe4660#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf4661#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x04662#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x704663#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x44664#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x3804665#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x74666#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c004667#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa4668#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c0004669#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe4670#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf4671#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x04672#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x704673#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x44674#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x3804675#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x74676#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c004677#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa4678#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c0004679#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe4680#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf4681#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x04682#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x704683#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x44684#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x3804685#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x74686#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c004687#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa4688#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c0004689#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe4690#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf4691#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x04692#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x704693#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x44694#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x3804695#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x74696#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c004697#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa4698#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c0004699#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe4700#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf4701#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x04702#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x704703#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x44704#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x3804705#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x74706#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c004707#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa4708#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c0004709#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe4710#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf4711#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x04712#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x704713#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x44714#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x3804715#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x74716#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c004717#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa4718#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c0004719#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe4720#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf4721#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x04722#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x704723#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x44724#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x3804725#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x74726#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c004727#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa4728#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c0004729#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe4730#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf4731#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x04732#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x704733#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x44734#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x3804735#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x74736#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c004737#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa4738#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c0004739#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe4740#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf4741#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x04742#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x704743#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x44744#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x3804745#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x74746#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c004747#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa4748#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c0004749#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe4750#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff4751#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x04752#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff4753#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x04754#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff004755#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x84756#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x100004757#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x104758#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe00004759#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x114760#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x20000004761#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x194762#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf4763#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x04764#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x704765#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x44766#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x3804767#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x74768#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c004769#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa4770#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c0004771#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe4772#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf4773#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x04774#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x704775#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x44776#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x3804777#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x74778#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c004779#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa4780#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c0004781#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe4782#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf4783#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x04784#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x704785#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x44786#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x3804787#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x74788#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c004789#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa4790#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c0004791#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe4792#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf4793#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x04794#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x704795#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x44796#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x3804797#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x74798#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c004799#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa4800#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c0004801#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe4802#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf4803#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x04804#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x704805#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x44806#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x3804807#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x74808#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c004809#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa4810#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c0004811#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe4812#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x14813#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x04814#define MC_XBAR_ADDR_DEC__GECC_MASK 0x24815#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x14816#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x44817#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x24818#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x84819#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x34820#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x14821#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x04822#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x24823#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x14824#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff4825#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x04826#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff004827#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x84828#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff00004829#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x104830#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff0000004831#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x184832#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff4833#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x04834#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff004835#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x84836#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff00004837#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x104838#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff0000004839#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x184840#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff4841#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x04842#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff004843#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x84844#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff00004845#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x104846#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff0000004847#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x184848#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff4849#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x04850#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff004851#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x84852#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff00004853#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x104854#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff0000004855#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x184856#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff4857#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x04858#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff004859#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x84860#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff4861#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x04862#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff004863#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x84864#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff00004865#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x104866#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff0000004867#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x184868#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff4869#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x04870#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff004871#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x84872#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff00004873#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x104874#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff4875#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x04876#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff004877#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x84878#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff00004879#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x104880#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff0000004881#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x184882#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff4883#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x04884#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff004885#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x84886#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x34887#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x04888#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc4889#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x24890#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x304891#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x44892#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x14893#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x04894#define MC_XBAR_TWOCHAN__CH0_MASK 0x64895#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x14896#define MC_XBAR_TWOCHAN__CH1_MASK 0x184897#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x34898#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x14899#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x04900#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x24901#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x14902#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x44903#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x24904#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf4905#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x04906#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf04907#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x44908#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf004909#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x84910#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf0004911#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc4912#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf00004913#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x104914#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf000004915#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x144916#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf0000004917#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x184918#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf00000004919#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c4920#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff4921#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x04922#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff0004923#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc4924#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x30000004925#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x184926#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc0000004927#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a4928#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x100000004929#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c4930#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff4931#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x04932#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff004933#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x84934#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff00004935#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x104936#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff4937#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x04938#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff004939#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x84940#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff00004941#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x104942#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff0000004943#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x184944#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff4945#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x04946#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff4947#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x04948#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff4949#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x04950#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff4951#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x04952#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff4953#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x04954#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff004955#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x84956#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff00004957#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x104958#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff0000004959#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x184960#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff4961#define MC_XBAR_SPARE0__BIT__SHIFT 0x04962#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff4963#define MC_XBAR_SPARE1__BIT__SHIFT 0x04964#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff4965#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x04966#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff4967#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x04968#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff4969#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x04970#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff4971#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x04972#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff4973#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x04974#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff4975#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x04976#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff4977#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x04978#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff4979#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x04980#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff4981#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x04982#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00004983#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x104984#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff4985#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x04986#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00004987#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x104988#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff4989#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x04990#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00004991#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x104992#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff4993#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x04994#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00004995#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x104996#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff4997#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x04998#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00004999#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x105000#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff5001#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x05002#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00005003#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x105004#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff5005#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x05006#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00005007#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x105008#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff5009#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x05010#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00005011#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x105012#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5013#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05014#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005015#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85016#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005017#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185018#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005019#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5020#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005021#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5022#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5023#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05024#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005025#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85026#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005027#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185028#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005029#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5030#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005031#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5032#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff5033#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x05034#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff005035#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x85036#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf0000005037#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x185038#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x100000005039#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c5040#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x200000005041#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d5042#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff5043#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x05044#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff005045#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x85046#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf0000005047#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x185048#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x100000005049#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c5050#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x200000005051#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d5052#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5053#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05054#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005055#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85056#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005057#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185058#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005059#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5060#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005061#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5062#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5063#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05064#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005065#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85066#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005067#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185068#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005069#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5070#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005071#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5072#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff5073#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x05074#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff005075#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x85076#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf0000005077#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x185078#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x100000005079#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c5080#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x200000005081#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d5082#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff5083#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x05084#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff005085#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x85086#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf0000005087#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x185088#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x100000005089#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c5090#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x200000005091#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d5092#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5093#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05094#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005095#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85096#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005097#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185098#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005099#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5100#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005101#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5102#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5103#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05104#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005105#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85106#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005107#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185108#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005109#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5110#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005111#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5112#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff5113#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x05114#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff005115#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x85116#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf0000005117#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x185118#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x100000005119#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c5120#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x200000005121#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d5122#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff5123#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x05124#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff005125#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x85126#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf0000005127#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x185128#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x100000005129#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c5130#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x200000005131#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d5132#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5133#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05134#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005135#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85136#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005137#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185138#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005139#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5140#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005141#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5142#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5143#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05144#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005145#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85146#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005147#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185148#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005149#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5150#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005151#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5152#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff5153#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x05154#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff005155#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x85156#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf0000005157#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x185158#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x100000005159#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c5160#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x200000005161#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d5162#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff5163#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x05164#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff005165#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x85166#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf0000005167#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x185168#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x100000005169#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c5170#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x200000005171#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d5172#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5173#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05174#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005175#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85176#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005177#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185178#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005179#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5180#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005181#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5182#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5183#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05184#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005185#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85186#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005187#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185188#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005189#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5190#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005191#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5192#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff5193#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x05194#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff005195#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x85196#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf0000005197#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x185198#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x100000005199#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c5200#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x200000005201#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d5202#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff5203#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x05204#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff005205#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x85206#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf0000005207#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x185208#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x100000005209#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c5210#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x200000005211#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d5212#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5213#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05214#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005215#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85216#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005217#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185218#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005219#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5220#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005221#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5222#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5223#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05224#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005225#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85226#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005227#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185228#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005229#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5230#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005231#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5232#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff5233#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x05234#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff005235#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x85236#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf0000005237#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x185238#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x100000005239#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c5240#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x200000005241#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d5242#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff5243#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x05244#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff005245#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x85246#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf0000005247#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x185248#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x100000005249#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c5250#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x200000005251#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d5252#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5253#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05254#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005255#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85256#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005257#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185258#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005259#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5260#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005261#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5262#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5263#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05264#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005265#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85266#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005267#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185268#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005269#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5270#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005271#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5272#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff5273#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x05274#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff005275#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x85276#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf0000005277#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x185278#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x100000005279#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c5280#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x200000005281#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d5282#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff5283#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x05284#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff005285#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x85286#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf0000005287#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x185288#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x100000005289#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c5290#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x200000005291#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d5292#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5293#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05294#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005295#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85296#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005297#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185298#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005299#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5300#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005301#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5302#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5303#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05304#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005305#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85306#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005307#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185308#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005309#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5310#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005311#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5312#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5313#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05314#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005315#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85316#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005317#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105318#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005319#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185320#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005321#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195322#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005323#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5324#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5325#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05326#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005327#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85328#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005329#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105330#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005331#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185332#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005333#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195334#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005335#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5336#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5337#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05338#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005339#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85340#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005341#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105342#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005343#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185344#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005345#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195346#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005347#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5348#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5349#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05350#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005351#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85352#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005353#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105354#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005355#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185356#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005357#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195358#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005359#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5360#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5361#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05362#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005363#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85364#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005365#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105366#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005367#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185368#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005369#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195370#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005371#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5372#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5373#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05374#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005375#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85376#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005377#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105378#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005379#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185380#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005381#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195382#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005383#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5384#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5385#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05386#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005387#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85388#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005389#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105390#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005391#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185392#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005393#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195394#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005395#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5396#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5397#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05398#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005399#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85400#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005401#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105402#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005403#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185404#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005405#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195406#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005407#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5408#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff5409#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x05410#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff5411#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x05412#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff00005413#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x105414#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff5415#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x05416#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff005417#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x85418#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf0000005419#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x185420#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x100000005421#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c5422#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x200000005423#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d5424#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff5425#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x05426#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff005427#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x85428#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf0000005429#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x185430#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x100000005431#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c5432#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x200000005433#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d5434#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf5435#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x05436#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff005437#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x85438#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff00005439#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x105440#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x10000005441#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x185442#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x20000005443#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x195444#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x40000005445#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a5446#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x15447#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x05448#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff5449#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x05450#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff5451#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x05452#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff5453#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x05454#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff5455#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x05456#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x35457#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x05458#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x35459#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x05460#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff5461#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x05462#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff5463#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x05464#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x15465#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x05466#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x25467#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x15468#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x45469#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x25470#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f005471#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x85472#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf00005473#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x105474#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x15475#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x05476#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x25477#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x15478#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x45479#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x25480#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x205481#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x55482#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x405483#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x65484#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x805485#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x75486#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x1005487#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x85488#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x2005489#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x95490#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c005491#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa5492#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x40005493#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe5494#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x80005495#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf5496#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x100005497#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x105498#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x200005499#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x115500#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x400005501#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x125502#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f5503#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x05504#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x1005505#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x85506#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x100005507#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x105508#define ATC_ATS_STATUS__BUSY_MASK 0x15509#define ATC_ATS_STATUS__BUSY__SHIFT 0x05510#define ATC_ATS_STATUS__CRASHED_MASK 0x25511#define ATC_ATS_STATUS__CRASHED__SHIFT 0x15512#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x45513#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x25514#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f5515#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x05516#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc005517#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa5518#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f000005519#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x145520#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f5521#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x05522#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c005523#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa5524#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x80005525#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf5526#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x100005527#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x105528#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x200005529#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x115530#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x400005531#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x125532#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf800005533#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x135534#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf0000005535#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x185536#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff5537#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x05538#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff5539#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x05540#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x15541#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x05542#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c5543#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x25544#define ATC_MISC_CG__OFFDLY_MASK 0xfc05545#define ATC_MISC_CG__OFFDLY__SHIFT 0x65546#define ATC_MISC_CG__ENABLE_MASK 0x400005547#define ATC_MISC_CG__ENABLE__SHIFT 0x125548#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x800005549#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x135550#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x35551#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x05552#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x305553#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x45554#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x1005555#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x85556#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x2005557#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x95558#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f5559#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x05560#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc05561#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x65562#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x1005563#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x85564#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe005565#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x95566#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x70005567#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc5568#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f80005569#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf5570#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f5571#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x05572#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f5573#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x05574#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe05575#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x55576#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x1005577#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x85578#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x2005579#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x95580#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x8005581#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb5582#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x10005583#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc5584#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x40005585#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe5586#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x180005587#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf5588#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x600005589#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x115590#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x35591#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x05592#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x45593#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x25594#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x105595#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x45596#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff5597#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x05598#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x15599#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x05600#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x25601#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x15602#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf05603#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x45604#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x7005605#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x85606#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f0005607#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc5608#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff000005609#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x145610#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x300000005611#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c5612#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x400000005613#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e5614#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x800000005615#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f5616#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x15617#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x05618#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x25619#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x15620#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf05621#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x45622#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x7005623#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x85624#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f0005625#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc5626#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff000005627#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x145628#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x300000005629#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c5630#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x400000005631#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e5632#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x800000005633#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f5634#define ATC_L1RD_STATUS__BUSY_MASK 0x15635#define ATC_L1RD_STATUS__BUSY__SHIFT 0x05636#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x25637#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x15638#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x1005639#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x85640#define ATC_L1WR_STATUS__BUSY_MASK 0x15641#define ATC_L1WR_STATUS__BUSY__SHIFT 0x05642#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x25643#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x15644#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x1005645#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x85646#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x15647#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x05648#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x25649#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x15650#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x45651#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x25652#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x85653#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x35654#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x105655#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x45656#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x205657#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x55658#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x405659#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x65660#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x805661#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x75662#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x1005663#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x85664#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x2005665#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x95666#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x4005667#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa5668#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x8005669#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb5670#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x10005671#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc5672#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x20005673#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd5674#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x40005675#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe5676#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x80005677#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf5678#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff5679#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x05680#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x800000005681#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f5682#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff5683#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x05684#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x800000005685#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f5686#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff5687#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x05688#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x800000005689#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f5690#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff5691#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x05692#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x800000005693#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f5694#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff5695#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x05696#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x800000005697#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f5698#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff5699#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x05700#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x800000005701#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f5702#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff5703#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x05704#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x800000005705#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f5706#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff5707#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x05708#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x800000005709#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f5710#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff5711#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x05712#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x800000005713#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f5714#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff5715#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x05716#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x800000005717#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f5718#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff5719#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x05720#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x800000005721#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f5722#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff5723#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x05724#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x800000005725#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f5726#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff5727#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x05728#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x800000005729#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f5730#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff5731#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x05732#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x800000005733#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f5734#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff5735#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x05736#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x800000005737#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f5738#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff5739#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x05740#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x800000005741#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f5742#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff5743#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x05744#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff5745#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x05746#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x15747#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x05748#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x25749#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x15750#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc5751#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x25752#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff0005753#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc5754#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc000005755#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x165756#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x4005757#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa5758#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x8005759#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb5760#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf0005761#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc5762#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x100005763#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x105764#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x600005765#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x115766#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x1800005767#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x135768#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x2000005769#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x155770#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x4000005771#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x165772#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x8000005773#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x175774#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x10000005775#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x185776#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x20000005777#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x195778#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x40000005779#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a5780#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x80000005781#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b5782#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x700000005783#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c5784#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x800000005785#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f5786#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f5787#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x05788#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c05789#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x65790#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f8005791#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb5792#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe00005793#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x115794#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x200000005795#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d5796#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x400000005797#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e5798#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x800000005799#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f5800#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff5801#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x05802#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff00005803#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x105804#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff5805#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x05806#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff00005807#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x105808#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff5809#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x05810#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff00005811#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x105812#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff5813#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x05814#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff00005815#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x105816#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff5817#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x05818#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff00005819#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x105820#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff5821#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x05822#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff0005823#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc5824#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x30000005825#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x185826#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc0000005827#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a5828#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x100000005829#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c5830#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x200000005831#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d5832#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x400000005833#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e5834#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x800000005835#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f5836#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f5837#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x05838#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc05839#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x65840#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f0005841#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc5842#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc00005843#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x125844#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe0000005845#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x195846#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff5847#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x05848#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff5849#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x05850#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff5851#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x05852#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x1005853#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x85854#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x2005855#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x95856#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x4005857#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa5858#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x8005859#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb5860#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x10005861#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc5862#define GMCON_PGFSM_CONFIG__READ_MASK 0x20005863#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd5864#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc0005865#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe5866#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x80000005867#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b5868#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf00000005869#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c5870#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff5871#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x05872#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff5873#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x05874#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf0000005875#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x185876#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x100000005877#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c5878#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff5879#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x05880#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff005881#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x85882#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff00005883#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x105884#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x100000005885#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c5886#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x200000005887#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d5888#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x400000005889#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e5890#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x15891#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x05892#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x25893#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x15894#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x45895#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x25896#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x85897#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x35898#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff05899#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x45900#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff5901#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x05902#define GMCON_DEBUG__GFX_STALL_MASK 0x15903#define GMCON_DEBUG__GFX_STALL__SHIFT 0x05904#define GMCON_DEBUG__GFX_CLEAR_MASK 0x25905#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x15906#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc5907#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x25908#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x15909#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x05910#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x25911#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x15912#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc5913#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x25914#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x305915#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x45916#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x1005917#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x85918#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x2005919#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x95920#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x4005921#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa5922#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x8005923#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb5924#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x70005925#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc5926#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x380005927#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf5928#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x400005929#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x125930#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x1800005931#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x135932#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e000005933#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x155934#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc0000005935#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a5936#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x700000005937#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c5938#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x15939#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x05940#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x25941#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x15942#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x2000005943#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x155944#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x4000005945#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x165946#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x38000005947#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x175948#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc0000005949#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a5950#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x700000005951#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c5952#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f5953#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x05954#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc05955#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x65956#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f005957#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x85958#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf80005959#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf5960#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x1000005961#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x145962#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe000005963#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x155964#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf0000005965#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x185966#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x100000005967#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c5968#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x200000005969#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d5970#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x400000005971#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e5972#define VM_L2_STATUS__L2_BUSY_MASK 0x15973#define VM_L2_STATUS__L2_BUSY__SHIFT 0x05974#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe5975#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x15976#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x15977#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x05978#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x65979#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x15980#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x85981#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x35982#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x105983#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x45984#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x405985#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x65986#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x805987#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x75988#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x2005989#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x95990#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x4005991#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa5992#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x8005993#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb5994#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10005995#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc5996#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20005997#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd5998#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x40005999#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe6000#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x80006001#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf6002#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x100006003#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x106004#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x200006005#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x116006#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x400006007#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x126008#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x800006009#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x136010#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x1000006011#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x146012#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x2000006013#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x156014#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x4000006015#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x166016#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x8000006017#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x176018#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf0000006019#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x186020#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x16021#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x06022#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x66023#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x16024#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x86025#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x36026#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x106027#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x46028#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x406029#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x66030#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x806031#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x76032#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x2006033#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x96034#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x4006035#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa6036#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x8006037#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb6038#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10006039#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc6040#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20006041#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd6042#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x40006043#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe6044#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x80006045#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf6046#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x100006047#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x106048#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x200006049#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x116050#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x400006051#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x126052#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x800006053#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x136054#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x1000006055#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x146056#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x2000006057#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x156058#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x4000006059#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x166060#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x8000006061#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x176062#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf0000006063#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x186064#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x16065#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x06066#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x26067#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x16068#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc6069#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x26070#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff6071#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x06072#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x16073#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x06074#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x26075#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x16076#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x46077#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x26078#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x86079#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x36080#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x106081#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x46082#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x16083#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x06084#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x26085#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x16086#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x46087#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x26088#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x86089#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x36090#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x106091#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x46092#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6093#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06094#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6095#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06096#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6097#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06098#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6099#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06100#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6101#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06102#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6103#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06104#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6105#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06106#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6107#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06108#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x16109#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x06110#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x26111#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x16112#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x46113#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x26114#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x86115#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x36116#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x106117#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x46118#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x206119#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x56120#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x406121#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x66122#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x806123#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x76124#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x1006125#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x86126#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x2006127#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x96128#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x4006129#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa6130#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x8006131#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb6132#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x10006133#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc6134#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x20006135#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd6136#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x40006137#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe6138#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x80006139#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf6140#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x16141#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x06142#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x26143#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x16144#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x46145#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x26146#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x86147#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x36148#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x106149#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x46150#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x206151#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x56152#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x406153#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x66154#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x806155#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x76156#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x1006157#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x86158#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x2006159#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x96160#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x4006161#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa6162#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x8006163#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb6164#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x10006165#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc6166#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x20006167#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd6168#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x40006169#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe6170#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x80006171#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf6172#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6173#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06174#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6175#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06176#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6177#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06178#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6179#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06180#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6181#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06182#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6183#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06184#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6185#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06186#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6187#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06188#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x16189#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x06190#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x26191#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x16192#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x46193#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x26194#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x86195#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x36196#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x106197#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x46198#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x206199#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x56200#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x406201#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x66202#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x16203#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x06204#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x26205#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x16206#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x46207#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x26208#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x86209#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x36210#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x106211#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x46212#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x206213#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x56214#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x406215#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x66216#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x806217#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x76218#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x1006219#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x86220#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x2006221#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x96222#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x4006223#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa6224#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x8006225#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb6226#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x10006227#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc6228#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x20006229#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd6230#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x40006231#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe6232#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x80006233#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf6234#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff6235#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x06236#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff0006237#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc6238#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x10000006239#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x186240#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e0000006241#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x196242#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff6243#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x06244#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff0006245#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc6246#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x10000006247#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x186248#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e0000006249#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x196250#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff6251#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x06252#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff6253#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x06254#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff6255#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x06256#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff6257#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x06258#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff6259#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x06260#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff6261#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x06262#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff6263#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x06264#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe006265#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x96266#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6267#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06268#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6269#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06270#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6271#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06272#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6273#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06274#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6275#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06276#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6277#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06278#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6279#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06280#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff6281#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x06282#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6283#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06284#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6285#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06286#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6287#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06288#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6289#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06290#define VM_DEBUG__FLAGS_MASK 0xffffffff6291#define VM_DEBUG__FLAGS__SHIFT 0x06292#define VM_L2_CG__OFFDLY_MASK 0xfc06293#define VM_L2_CG__OFFDLY__SHIFT 0x66294#define VM_L2_CG__ENABLE_MASK 0x400006295#define VM_L2_CG__ENABLE__SHIFT 0x126296#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x800006297#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x136298#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff6299#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x06300#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x1ff6301#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x06302#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6303#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06304#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff6305#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x06306#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff6307#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x06308#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x36309#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x06310#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc6311#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x26312#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x306313#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x46314#define MC_SEQ_CNTL__DAT_INV_MASK 0x406315#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x66316#define MC_SEQ_CNTL__MSK_DF1_MASK 0x806317#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x76318#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x3006319#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x86320#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x40006321#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe6322#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x80006323#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf6324#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x100006325#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x106326#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x200006327#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x116328#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x400006329#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x126330#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x800006331#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x136332#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf000006333#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x146334#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf0000006335#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x186336#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf00000006337#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c6338#define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf6339#define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x06340#define MC_SEQ_CNTL_2__DRST_PU_MASK 0x106341#define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x46342#define MC_SEQ_CNTL_2__DRST_PD_MASK 0x206343#define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x56344#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x3006345#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x86346#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc006347#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa6348#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f00006349#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x106350#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x4000006351#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x166352#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x8000006353#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x176354#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf0000006355#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x186356#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf00000006357#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c6358#define MC_SEQ_DRAM__ADR_2CK_MASK 0x16359#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x06360#define MC_SEQ_DRAM__ADR_MUX_MASK 0x26361#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x16362#define MC_SEQ_DRAM__ADR_DF1_MASK 0x46363#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x26364#define MC_SEQ_DRAM__AP8_MASK 0x86365#define MC_SEQ_DRAM__AP8__SHIFT 0x36366#define MC_SEQ_DRAM__DAT_DF1_MASK 0x106367#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x46368#define MC_SEQ_DRAM__DQS_DF1_MASK 0x206369#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x56370#define MC_SEQ_DRAM__DQM_DF1_MASK 0x406371#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x66372#define MC_SEQ_DRAM__DQM_ACT_MASK 0x806373#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x76374#define MC_SEQ_DRAM__STB_CNT_MASK 0xf006375#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x86376#define MC_SEQ_DRAM__CKE_DYN_MASK 0x10006377#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc6378#define MC_SEQ_DRAM__CKE_ACT_MASK 0x20006379#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd6380#define MC_SEQ_DRAM__BO4_MASK 0x40006381#define MC_SEQ_DRAM__BO4__SHIFT 0xe6382#define MC_SEQ_DRAM__DLL_CLR_MASK 0x80006383#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf6384#define MC_SEQ_DRAM__DLL_CNT_MASK 0xff00006385#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x106386#define MC_SEQ_DRAM__DAT_INV_MASK 0x10000006387#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x186388#define MC_SEQ_DRAM__INV_ACM_MASK 0x20000006389#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x196390#define MC_SEQ_DRAM__ODT_ENB_MASK 0x40000006391#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a6392#define MC_SEQ_DRAM__ODT_ACT_MASK 0x80000006393#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b6394#define MC_SEQ_DRAM__RST_CTL_MASK 0x100000006395#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c6396#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x200000006397#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d6398#define MC_SEQ_DRAM__TRI_CKE_MASK 0x400000006399#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e6400#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x800000006401#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f6402#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x16403#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x06404#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x26405#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x16406#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x46407#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x26408#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x86409#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x36410#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x106411#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x46412#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x206413#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x56414#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x406415#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x66416#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x806417#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x76418#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x1006419#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x86420#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x2006421#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x96422#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x4006423#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa6424#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x8006425#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb6426#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x10006427#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc6428#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x20006429#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd6430#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x40006431#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe6432#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x80006433#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf6434#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff00006435#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x106436#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x10000006437#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x186438#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x20000006439#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x196440#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x40000006441#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a6442#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x80000006443#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b6444#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x100000006445#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c6446#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x200000006447#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d6448#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x400000006449#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e6450#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x800000006451#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f6452#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f6453#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x06454#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e06455#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x56456#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c006457#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa6458#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf80006459#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf6460#define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf000006461#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x146462#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f0000006463#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x186464#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x36465#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x06466#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc6467#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x26468#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f06469#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x46470#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe006471#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x96472#define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf0006473#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc6474#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f00006475#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x106476#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f0000006477#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x186478#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f6479#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x06480#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f006481#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x86482#define MC_SEQ_MISC_TIMING__TRP_MASK 0xf80006483#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf6484#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff000006485#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x146486#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x76487#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x06488#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x706489#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x46490#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f006491#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x86492#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe0006493#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd6494#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f00006495#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x106496#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e000006497#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x156498#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf00000006499#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c6500#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x76501#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x06502#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x706503#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x46504#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf006505#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x86506#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f0006507#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc6508#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c00006509#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x126510#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x8000006511#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x176512#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff0000006513#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x186514#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x76515#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x06516#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf86517#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x36518#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x3006519#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x86520#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc006521#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa6522#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf0006523#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc6524#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x100006525#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x106526#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x200006527#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x116528#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f000006529#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x146530#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e0000006531#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x196532#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x76533#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x06534#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf86535#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x36536#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x3006537#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x86538#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc006539#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa6540#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf0006541#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc6542#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x100006543#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x106544#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x200006545#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x116546#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f000006547#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x146548#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e0000006549#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x196550#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf6551#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x06552#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf06553#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x46554#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x1006555#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x86556#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x2006557#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x96558#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x4006559#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa6560#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x8006561#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb6562#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf0006563#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc6564#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf00006565#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x106566#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x3000006567#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x146568#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf0000006569#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x186570#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x100000006571#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c6572#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x200000006573#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d6574#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x400000006575#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e6576#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf6577#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x06578#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf06579#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x46580#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x1006581#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x86582#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x2006583#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x96584#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x4006585#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa6586#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x8006587#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb6588#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf0006589#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc6590#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf00006591#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x106592#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x3000006593#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x146594#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf0000006595#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x186596#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x100000006597#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c6598#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x200000006599#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d6600#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x400000006601#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e6602#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x16603#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x06604#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x26605#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x16606#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x46607#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x26608#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x86609#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x36610#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x106611#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x46612#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x206613#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x56614#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x406615#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x66616#define MC_SEQ_CMD__ADR_MASK 0xffff6617#define MC_SEQ_CMD__ADR__SHIFT 0x06618#define MC_SEQ_CMD__MOP_MASK 0xf00006619#define MC_SEQ_CMD__MOP__SHIFT 0x106620#define MC_SEQ_CMD__END_MASK 0x1000006621#define MC_SEQ_CMD__END__SHIFT 0x146622#define MC_SEQ_CMD__CSB_MASK 0x6000006623#define MC_SEQ_CMD__CSB__SHIFT 0x156624#define MC_SEQ_CMD__CHAN0_MASK 0x10000006625#define MC_SEQ_CMD__CHAN0__SHIFT 0x186626#define MC_SEQ_CMD__CHAN1_MASK 0x20000006627#define MC_SEQ_CMD__CHAN1__SHIFT 0x196628#define MC_SEQ_CMD__ADR_MSB1_MASK 0x100000006629#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c6630#define MC_SEQ_CMD__ADR_MSB0_MASK 0x200000006631#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d6632#define MC_PMG_CMD_EMRS__ADR_MASK 0xffff6633#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x06634#define MC_PMG_CMD_EMRS__MOP_MASK 0x700006635#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x106636#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x800006637#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x136638#define MC_PMG_CMD_EMRS__END_MASK 0x1000006639#define MC_PMG_CMD_EMRS__END__SHIFT 0x146640#define MC_PMG_CMD_EMRS__CSB_MASK 0x6000006641#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x156642#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x100000006643#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c6644#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x200000006645#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d6646#define MC_PMG_CMD_MRS__ADR_MASK 0xffff6647#define MC_PMG_CMD_MRS__ADR__SHIFT 0x06648#define MC_PMG_CMD_MRS__MOP_MASK 0x700006649#define MC_PMG_CMD_MRS__MOP__SHIFT 0x106650#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x800006651#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x136652#define MC_PMG_CMD_MRS__END_MASK 0x1000006653#define MC_PMG_CMD_MRS__END__SHIFT 0x146654#define MC_PMG_CMD_MRS__CSB_MASK 0x6000006655#define MC_PMG_CMD_MRS__CSB__SHIFT 0x156656#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x100000006657#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c6658#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x200000006659#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d6660#define MC_PMG_CMD_MRS1__ADR_MASK 0xffff6661#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x06662#define MC_PMG_CMD_MRS1__MOP_MASK 0x700006663#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x106664#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x800006665#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x136666#define MC_PMG_CMD_MRS1__END_MASK 0x1000006667#define MC_PMG_CMD_MRS1__END__SHIFT 0x146668#define MC_PMG_CMD_MRS1__CSB_MASK 0x6000006669#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x156670#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x100000006671#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c6672#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x200000006673#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d6674#define MC_PMG_CMD_MRS2__ADR_MASK 0xffff6675#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x06676#define MC_PMG_CMD_MRS2__MOP_MASK 0x700006677#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x106678#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x800006679#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x136680#define MC_PMG_CMD_MRS2__END_MASK 0x1000006681#define MC_PMG_CMD_MRS2__END__SHIFT 0x146682#define MC_PMG_CMD_MRS2__CSB_MASK 0x6000006683#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x156684#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x100000006685#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c6686#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x200000006687#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d6688#define MC_PMG_CFG__SYC_CLK_MASK 0x16689#define MC_PMG_CFG__SYC_CLK__SHIFT 0x06690#define MC_PMG_CFG__RST_MRS_MASK 0x26691#define MC_PMG_CFG__RST_MRS__SHIFT 0x16692#define MC_PMG_CFG__RST_EMRS_MASK 0x46693#define MC_PMG_CFG__RST_EMRS__SHIFT 0x26694#define MC_PMG_CFG__TRI_MIO_MASK 0x86695#define MC_PMG_CFG__TRI_MIO__SHIFT 0x36696#define MC_PMG_CFG__XSR_TMR_MASK 0xf06697#define MC_PMG_CFG__XSR_TMR__SHIFT 0x46698#define MC_PMG_CFG__RST_MRS1_MASK 0x1006699#define MC_PMG_CFG__RST_MRS1__SHIFT 0x86700#define MC_PMG_CFG__RST_MRS2_MASK 0x2006701#define MC_PMG_CFG__RST_MRS2__SHIFT 0x96702#define MC_PMG_CFG__DPM_WAKE_MASK 0x4006703#define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa6704#define MC_PMG_CFG__RFS_SRX_MASK 0x10006705#define MC_PMG_CFG__RFS_SRX__SHIFT 0xc6706#define MC_PMG_CFG__PREA_SRX_MASK 0x20006707#define MC_PMG_CFG__PREA_SRX__SHIFT 0xd6708#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf00006709#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x106710#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x1000006711#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x146712#define MC_PMG_CFG__YCLK_ON_MASK 0x2000006713#define MC_PMG_CFG__YCLK_ON__SHIFT 0x156714#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x4000006715#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x166716#define MC_PMG_CFG__RXPDNB_MASK 0x20000006717#define MC_PMG_CFG__RXPDNB__SHIFT 0x196718#define MC_PMG_CFG__ZQCL_SEND_MASK 0xc0000006719#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a6720#define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff6721#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x06722#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x100000006723#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c6724#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x200000006725#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d6726#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x16727#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x06728#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x26729#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x16730#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x46731#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x26732#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf06733#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x46734#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x1006735#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x86736#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x2006737#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x96738#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x4006739#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa6740#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x8006741#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb6742#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x10006743#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc6744#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x20006745#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd6746#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x40006747#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe6748#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x80006749#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf6750#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf00006751#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x106752#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x1000006753#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x146754#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x2000006755#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x156756#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x4000006757#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x166758#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x8000006759#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x176760#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff0000006761#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x186762#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f6763#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x06764#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x206765#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x56766#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x406767#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x66768#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x1006769#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x86770#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x2006771#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x96772#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe0006773#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd6774#define MC_IMP_CNTL__CAL_VREF_MASK 0x7f00006775#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x106776#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x200000006777#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d6778#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x400000006779#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e6780#define MC_IMP_CNTL__CAL_PWRON_MASK 0x800000006781#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f6782#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff6783#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x06784#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff006785#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x86786#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff00006787#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x106788#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x100000006789#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c6790#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x200000006791#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d6792#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x400000006793#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e6794#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x800000006795#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f6796#define MC_IMP_STATUS__PSTR_CAL_MASK 0xff6797#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x06798#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff006799#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x86800#define MC_IMP_STATUS__NSTR_CAL_MASK 0xff00006801#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x106802#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff0000006803#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x186804#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff6805#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x06806#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff006807#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x86808#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff00006809#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x106810#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff0000006811#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x186812#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff6813#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x06814#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf006815#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x86816#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x10006817#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc6818#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x20006819#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd6820#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x40006821#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe6822#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x80006823#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf6824#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf00006825#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x106826#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x1000006827#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x146828#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x2000006829#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x156830#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf0000006831#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x186832#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf00000006833#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c6834#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x16835#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x06836#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x26837#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x16838#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x46839#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x26840#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x86841#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x36842#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x106843#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x46844#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x206845#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x56846#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x406847#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x66848#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x806849#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x76850#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x1006851#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x86852#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x2006853#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x96854#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x4006855#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa6856#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x8006857#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb6858#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x10006859#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc6860#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x20006861#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd6862#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x40006863#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe6864#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x80006865#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf6866#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x100006867#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x106868#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x200006869#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x116870#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x400006871#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x126872#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x800006873#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x136874#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x1000006875#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x146876#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x2000006877#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x156878#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x4000006879#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x166880#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x10000006881#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x186882#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x20000006883#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x196884#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x40000006885#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a6886#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x80000006887#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b6888#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x100000006889#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c6890#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x200000006891#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d6892#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x400000006893#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e6894#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x800000006895#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f6896#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff6897#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x06898#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff00006899#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x106900#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff6901#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x06902#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x16903#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x06904#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x26905#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x16906#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x46907#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x26908#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x86909#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x36910#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x306911#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x46912#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x1006913#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x86914#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x2006915#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x96916#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x16917#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x06918#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x26919#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x16920#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x46921#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x26922#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x86923#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x36924#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x106925#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x46926#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x206927#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x56928#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x406929#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x66930#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x806931#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x76932#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x1006933#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x86934#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x2006935#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x96936#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x4006937#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa6938#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x8006939#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb6940#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x10006941#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc6942#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x20006943#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd6944#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x40006945#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe6946#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x80006947#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf6948#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x200006949#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x116950#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x400006951#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x126952#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x800006953#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x136954#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x1000006955#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x146956#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x2000006957#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x156958#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x4000006959#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x166960#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x8000006961#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x176962#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x10000006963#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x186964#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x20000006965#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x196966#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x40000006967#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a6968#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x80000006969#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b6970#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x16971#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x06972#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x26973#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x16974#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x46975#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x26976#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x86977#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x36978#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x106979#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x46980#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x206981#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x56982#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x406983#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x66984#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x806985#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x76986#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x1006987#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x86988#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x2006989#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x96990#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x4006991#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa6992#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x8006993#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb6994#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x10006995#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc6996#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x20006997#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd6998#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x40006999#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe7000#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x80007001#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf7002#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x200007003#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x117004#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x400007005#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x127006#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x800007007#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x137008#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x1000007009#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x147010#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x2000007011#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x157012#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x4000007013#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x167014#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x8000007015#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x177016#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x10000007017#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x187018#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x20000007019#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x197020#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x40000007021#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a7022#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x80000007023#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b7024#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x17025#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x07026#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x27027#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x17028#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x47029#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x27030#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x87031#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x37032#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x107033#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x47034#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x207035#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x57036#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x407037#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x67038#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x807039#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x77040#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x1007041#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x87042#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x2007043#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x97044#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x4007045#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa7046#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x8007047#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb7048#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x10007049#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc7050#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x20007051#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd7052#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x40007053#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe7054#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x80007055#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf7056#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x200007057#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x117058#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x400007059#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x127060#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x800007061#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x137062#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x1000007063#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x147064#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x2000007065#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x157066#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x4000007067#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x167068#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x8000007069#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x177070#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x10000007071#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x187072#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x20000007073#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x197074#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x40000007075#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a7076#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x80000007077#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b7078#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x17079#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x07080#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x27081#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x17082#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x47083#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x27084#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x87085#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x37086#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x107087#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x47088#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x207089#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x57090#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x407091#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x67092#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x807093#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x77094#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x1007095#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x87096#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x2007097#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x97098#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x4007099#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa7100#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x8007101#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb7102#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x10007103#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc7104#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x20007105#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd7106#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x40007107#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe7108#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x80007109#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf7110#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x100007111#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x107112#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x200007113#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x117114#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x400007115#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x127116#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x800007117#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x137118#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x1000007119#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x147120#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x2000007121#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x157122#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x4000007123#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x167124#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x8000007125#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x177126#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x10000007127#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x187128#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x20000007129#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x197130#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x40000007131#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a7132#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x80000007133#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b7134#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f7135#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x07136#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e07137#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x57138#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c007139#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa7140#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf80007141#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf7142#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff7143#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x07144#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff007145#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x87146#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff00007147#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x107148#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff0000007149#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x187150#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff7151#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x07152#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff007153#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x87154#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff00007155#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x107156#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff0000007157#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x187158#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff7159#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x07160#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf7161#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x07162#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf07163#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x47164#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf007165#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x87166#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf0007167#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc7168#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x100000007169#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c7170#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x200000007171#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d7172#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x400000007173#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e7174#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x17175#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x07176#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x27177#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x17178#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x307179#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x47180#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x1007181#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x87182#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x2007183#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x97184#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x4007185#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa7186#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x8007187#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb7188#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff00007189#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x107190#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x100000007191#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c7192#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff7193#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x07194#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff00007195#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x107196#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff7197#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x07198#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf7199#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x07200#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf07201#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x47202#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf007203#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x87204#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf0007205#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc7206#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x100000007207#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c7208#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x200000007209#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d7210#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x400000007211#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e7212#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x17213#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x07214#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x27215#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x17216#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x307217#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x47218#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x1007219#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x87220#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x2007221#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x97222#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x4007223#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa7224#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x8007225#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb7226#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff00007227#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x107228#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x100000007229#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c7230#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff7231#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x07232#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff00007233#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x107234#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x37235#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x07236#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc7237#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x27238#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x107239#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x47240#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x207241#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x57242#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x407243#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x67244#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x807245#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x77246#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf007247#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x87248#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf0007249#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc7250#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf00007251#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x107252#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf000007253#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x147254#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x10000007255#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x187256#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x20000007257#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x197258#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x40000007259#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a7260#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x80000007261#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b7262#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf00000007263#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c7264#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x37265#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x07266#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc7267#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x27268#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x107269#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x47270#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x207271#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x57272#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x407273#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x67274#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x807275#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x77276#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf007277#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x87278#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf0007279#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc7280#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf00007281#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x107282#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf000007283#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x147284#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x10000007285#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x187286#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x20000007287#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x197288#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x40000007289#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a7290#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x80000007291#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b7292#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf00000007293#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c7294#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x37295#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x07296#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc7297#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x27298#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x107299#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x47300#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x207301#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x57302#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x407303#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x67304#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x807305#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x77306#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf007307#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x87308#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x10007309#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc7310#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe0007311#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd7312#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf00007313#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x107314#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x7000007315#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x147316#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x8000007317#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x177318#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x10000007319#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x187320#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x20000007321#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x197322#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x40000007323#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a7324#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x380000007325#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b7326#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x400000007327#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e7328#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x800000007329#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f7330#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x37331#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x07332#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x47333#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x27334#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x87335#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x37336#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x307337#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x47338#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x407339#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x67340#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x807341#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x77342#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf007343#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x87344#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf0007345#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc7346#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x100007347#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x107348#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc00007349#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x127350#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x7000007351#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x147352#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x70000007353#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x187354#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x100000007355#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c7356#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x200000007357#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d7358#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc00000007359#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e7360#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf7361#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x07362#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf07363#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x47364#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff007365#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x87366#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x100007367#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x107368#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x200007369#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x117370#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x400007371#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x127372#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x800007373#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x137374#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x1000007375#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x147376#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x2000007377#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x157378#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x4000007379#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x167380#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x8000007381#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x177382#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe0000007383#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x197384#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf00000007385#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c7386#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x37387#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x07388#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x47389#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x27390#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x87391#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x37392#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x307393#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x47394#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x407395#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x67396#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x807397#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x77398#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf007399#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x87400#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf0007401#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc7402#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x100007403#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x107404#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc00007405#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x127406#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x7000007407#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x147408#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x70000007409#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x187410#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x100000007411#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c7412#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x200000007413#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d7414#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc00000007415#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e7416#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf7417#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x07418#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf07419#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x47420#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff007421#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x87422#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x100007423#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x107424#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x200007425#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x117426#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x400007427#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x127428#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x800007429#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x137430#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x1000007431#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x147432#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x2000007433#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x157434#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x4000007435#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x167436#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x8000007437#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x177438#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe0000007439#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x197440#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf00000007441#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c7442#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f7443#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x07444#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc07445#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x67446#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f0007447#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc7448#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc00007449#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x127450#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x10000007451#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x187452#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x20000007453#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x197454#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc0000007455#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a7456#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x100000007457#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c7458#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x200000007459#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d7460#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x400000007461#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e7462#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f7463#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x07464#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc07465#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x67466#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f0007467#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc7468#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x10000007469#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x187470#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x20000007471#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x197472#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc0000007473#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a7474#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x100000007475#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c7476#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x200000007477#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d7478#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x37479#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x07480#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc7481#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x27482#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x107483#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x47484#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x207485#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x57486#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x407487#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x67488#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x807489#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x77490#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf007491#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x87492#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf0007493#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc7494#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf00007495#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x107496#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf000007497#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x147498#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x10000007499#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x187500#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x20000007501#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x197502#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x40000007503#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a7504#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x80000007505#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b7506#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf00000007507#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c7508#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x37509#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x07510#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc7511#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x27512#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x107513#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x47514#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x207515#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x57516#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x407517#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x67518#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x807519#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x77520#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf007521#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x87522#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf0007523#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc7524#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf00007525#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x107526#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf000007527#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x147528#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x10000007529#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x187530#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x20000007531#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x197532#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x40000007533#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a7534#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x80000007535#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b7536#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf00000007537#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c7538#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x37539#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x07540#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc7541#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x27542#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x107543#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x47544#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x207545#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x57546#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x407547#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x67548#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x807549#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x77550#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf007551#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x87552#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x10007553#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc7554#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe0007555#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd7556#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf00007557#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x107558#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x7000007559#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x147560#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x8000007561#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x177562#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x10000007563#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x187564#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x20000007565#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x197566#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x40000007567#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a7568#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x380000007569#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b7570#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x400000007571#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e7572#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x800000007573#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f7574#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x37575#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x07576#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x47577#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x27578#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x87579#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x37580#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x307581#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x47582#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x407583#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x67584#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x807585#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x77586#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf007587#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x87588#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf0007589#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc7590#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x100007591#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x107592#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc00007593#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x127594#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x7000007595#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x147596#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x70000007597#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x187598#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x100000007599#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c7600#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x200000007601#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d7602#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc00000007603#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e7604#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf7605#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x07606#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf07607#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x47608#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff007609#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x87610#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x100007611#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x107612#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x200007613#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x117614#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x400007615#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x127616#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x800007617#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x137618#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x1000007619#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x147620#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x2000007621#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x157622#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x4000007623#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x167624#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x8000007625#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x177626#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe0000007627#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x197628#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf00000007629#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c7630#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x37631#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x07632#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x47633#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x27634#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x87635#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x37636#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x307637#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x47638#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x407639#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x67640#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x807641#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x77642#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf007643#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x87644#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf0007645#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc7646#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x100007647#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x107648#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc00007649#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x127650#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x7000007651#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x147652#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x70000007653#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x187654#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x100000007655#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c7656#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x200000007657#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d7658#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc00000007659#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e7660#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf7661#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x07662#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf07663#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x47664#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff007665#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x87666#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x100007667#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x107668#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x200007669#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x117670#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x400007671#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x127672#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x800007673#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x137674#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x1000007675#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x147676#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x2000007677#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x157678#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x4000007679#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x167680#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x8000007681#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x177682#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe0000007683#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x197684#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf00000007685#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c7686#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f7687#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x07688#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc07689#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x67690#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f0007691#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc7692#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc00007693#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x127694#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x10000007695#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x187696#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x20000007697#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x197698#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc0000007699#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a7700#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x100000007701#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c7702#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x200000007703#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d7704#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x400000007705#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e7706#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f7707#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x07708#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc07709#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x67710#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f0007711#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc7712#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x10000007713#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x187714#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x20000007715#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x197716#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc0000007717#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a7718#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x100000007719#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c7720#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x200000007721#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d7722#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf7723#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x07724#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf07725#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x47726#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x1007727#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x87728#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x2007729#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x97730#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x4007731#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa7732#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x8007733#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb7734#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf0007735#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc7736#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf00007737#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x107738#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x1000007739#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x147740#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x2000007741#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x157742#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x4000007743#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x167744#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x8000007745#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x177746#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x10000007747#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x187748#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x20000007749#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x197750#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x40000007751#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a7752#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x80000007753#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b7754#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x100000007755#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c7756#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x200000007757#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d7758#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x400000007759#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e7760#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x800000007761#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f7762#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff7763#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x07764#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff007765#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x87766#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff00007767#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x107768#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff0000007769#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x187770#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x17771#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x07772#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x27773#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x17774#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x47775#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x27776#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x87777#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x37778#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x107779#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x47780#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x207781#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x57782#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x407783#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x67784#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x807785#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x77786#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf007787#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x87788#define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf0007789#define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc7790#define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf00007791#define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x107792#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf7793#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x07794#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf07795#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x47796#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x1007797#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x87798#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x2007799#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x97800#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x4007801#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa7802#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x8007803#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb7804#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf0007805#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc7806#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf00007807#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x107808#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x1000007809#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x147810#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x2000007811#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x157812#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x4000007813#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x167814#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x8000007815#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x177816#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x10000007817#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x187818#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x20000007819#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x197820#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x40000007821#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a7822#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x80000007823#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b7824#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x100000007825#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c7826#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x200000007827#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d7828#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x400000007829#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e7830#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x800000007831#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f7832#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff7833#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x07834#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff007835#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x87836#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff00007837#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x107838#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff0000007839#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x187840#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x17841#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x07842#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x27843#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x17844#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x47845#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x27846#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x87847#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x37848#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x107849#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x47850#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x207851#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x57852#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x407853#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x67854#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x807855#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x77856#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf007857#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x87858#define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf0007859#define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc7860#define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf00007861#define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x107862#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x37863#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x07864#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc7865#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x27866#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x307867#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x47868#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc07869#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x67870#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x1007871#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x87872#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x2007873#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x97874#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc007875#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa7876#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x70007877#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc7878#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x300007879#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x107880#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc00007881#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x127882#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf000007883#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x147884#define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf0000007885#define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x187886#define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x100000007887#define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c7888#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf7889#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x07890#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf07891#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x47892#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf007893#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x87894#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf0007895#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc7896#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf00007897#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x107898#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf000007899#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x147900#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf0000007901#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x187902#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf00000007903#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c7904#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf7905#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x07906#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf07907#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x47908#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf007909#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x87910#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf0007911#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc7912#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf00007913#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x107914#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf000007915#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x147916#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf0000007917#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x187918#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf00000007919#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c7920#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf7921#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x07922#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf07923#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x47924#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf007925#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x87926#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf0007927#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc7928#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf00007929#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x107930#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf000007931#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x147932#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf0000007933#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x187934#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf00000007935#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c7936#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf7937#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x07938#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf07939#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x47940#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf007941#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x87942#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf0007943#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc7944#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf00007945#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x107946#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf000007947#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x147948#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf0000007949#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x187950#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf00000007951#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c7952#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf7953#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x07954#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf07955#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x47956#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf007957#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x87958#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf0007959#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc7960#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf7961#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x07962#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf07963#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x47964#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf007965#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x87966#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf0007967#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc7968#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf00007969#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x107970#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf000007971#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x147972#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf0000007973#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x187974#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf00000007975#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c7976#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf7977#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x07978#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf07979#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x47980#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf007981#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x87982#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf0007983#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc7984#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf7985#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x07986#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf07987#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x47988#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf007989#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x87990#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf0007991#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc7992#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf00007993#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x107994#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf000007995#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x147996#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf0000007997#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x187998#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf00000007999#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c8000#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf8001#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x08002#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf08003#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x48004#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf008005#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x88006#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf0008007#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc8008#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf00008009#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x108010#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf000008011#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x148012#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf0000008013#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x188014#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf00000008015#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c8016#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf8017#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x08018#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf08019#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x48020#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf008021#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x88022#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf0008023#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc8024#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf00008025#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x108026#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf000008027#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x148028#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf0000008029#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x188030#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf00000008031#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c8032#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf8033#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x08034#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf08035#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x48036#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf008037#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x88038#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf0008039#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc8040#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf00008041#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x108042#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf000008043#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x148044#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf0000008045#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x188046#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf00000008047#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c8048#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf8049#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x08050#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf08051#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x48052#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf008053#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x88054#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf0008055#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc8056#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf8057#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x08058#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf08059#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x48060#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf008061#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x88062#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf0008063#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc8064#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf00008065#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x108066#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf000008067#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x148068#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf0000008069#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x188070#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf00000008071#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c8072#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf8073#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x08074#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf08075#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x48076#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf008077#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x88078#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf0008079#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc8080#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf8081#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x08082#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf08083#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x48084#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf008085#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x88086#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf0008087#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc8088#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf00008089#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x108090#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf000008091#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x148092#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf0000008093#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x188094#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf00000008095#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c8096#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf8097#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x08098#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf08099#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x48100#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf008101#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x88102#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf0008103#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc8104#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf00008105#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x108106#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf000008107#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x148108#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf0000008109#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x188110#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf00000008111#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c8112#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf8113#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x08114#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf08115#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x48116#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf008117#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x88118#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf0008119#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc8120#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf00008121#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x108122#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf000008123#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x148124#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf0000008125#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x188126#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf00000008127#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c8128#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf8129#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x08130#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf08131#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x48132#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf008133#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x88134#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf0008135#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc8136#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf00008137#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x108138#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf000008139#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x148140#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf0000008141#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x188142#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf00000008143#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c8144#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf8145#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x08146#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf08147#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x48148#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf008149#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x88150#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf0008151#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc8152#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf8153#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x08154#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf08155#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x48156#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf008157#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x88158#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf0008159#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc8160#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf00008161#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x108162#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf000008163#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x148164#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf0000008165#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x188166#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf00000008167#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c8168#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf8169#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x08170#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf08171#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x48172#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf008173#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x88174#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf0008175#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc8176#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf00008177#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x108178#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf000008179#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x148180#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf0000008181#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x188182#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf00000008183#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c8184#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf8185#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x08186#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf08187#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x48188#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf008189#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x88190#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf0008191#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc8192#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf00008193#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x108194#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf000008195#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x148196#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf0000008197#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x188198#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf00000008199#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c8200#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf8201#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x08202#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf08203#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x48204#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf008205#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x88206#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf0008207#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc8208#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf00008209#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x108210#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf000008211#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x148212#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf0000008213#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x188214#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf00000008215#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c8216#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf8217#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x08218#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf08219#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x48220#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf008221#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x88222#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf0008223#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc8224#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf00008225#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x108226#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf000008227#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x148228#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf0000008229#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x188230#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf00000008231#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c8232#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf8233#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x08234#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf08235#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x48236#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf008237#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x88238#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf0008239#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc8240#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf8241#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x08242#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf08243#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x48244#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf008245#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x88246#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf0008247#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc8248#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf00008249#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x108250#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf000008251#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x148252#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf0000008253#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x188254#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf00000008255#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c8256#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff8257#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x08258#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff008259#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x88260#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x100008261#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x108262#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x200008263#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x118264#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x400008265#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x128266#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x800008267#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x138268#define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf000008269#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x148270#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f0000008271#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x188272#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x400000008273#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e8274#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x800000008275#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f8276#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x48277#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x28278#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x88279#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x38280#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x108281#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x48282#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x808283#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x78284#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x1008285#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x88286#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x2008287#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x98288#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x4008289#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa8290#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x8008291#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb8292#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x10008293#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc8294#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x20008295#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd8296#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x40008297#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe8298#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf80008299#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf8300#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x1000008301#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x148302#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x2000008303#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x158304#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc000008305#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x168306#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x30000008307#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x188308#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x80000008309#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b8310#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x100000008311#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c8312#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x200000008313#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d8314#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x400000008315#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e8316#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x800000008317#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f8318#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x18319#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x08320#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x28321#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x18322#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x48323#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x28324#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x88325#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x38326#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x108327#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x48328#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x208329#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x58330#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x408331#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x68332#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x808333#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x78334#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x1008335#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x88336#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x2008337#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x98338#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x4008339#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa8340#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x8008341#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb8342#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x10008343#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc8344#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x20008345#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd8346#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x40008347#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe8348#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf80008349#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf8350#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x1000008351#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x148352#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x2000008353#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x158354#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc000008355#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x168356#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x30000008357#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x188358#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x80000008359#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b8360#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x100000008361#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c8362#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x200000008363#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d8364#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x400000008365#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e8366#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x800000008367#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f8368#define MC_NPL_STATUS__D0_PDELAY_MASK 0x38369#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x08370#define MC_NPL_STATUS__D0_NDELAY_MASK 0xc8371#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x28372#define MC_NPL_STATUS__D0_PEARLY_MASK 0x108373#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x48374#define MC_NPL_STATUS__D0_NEARLY_MASK 0x208375#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x58376#define MC_NPL_STATUS__D1_PDELAY_MASK 0xc08377#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x68378#define MC_NPL_STATUS__D1_NDELAY_MASK 0x3008379#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x88380#define MC_NPL_STATUS__D1_PEARLY_MASK 0x4008381#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa8382#define MC_NPL_STATUS__D1_NEARLY_MASK 0x8008383#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb8384#define MC_BIST_CMD_CNTL__RESET_MASK 0x18385#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x08386#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x28387#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x18388#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x48389#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x28390#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x88391#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x38392#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff08393#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x48394#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x100008395#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x108396#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x200008397#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x118398#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc00008399#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x128400#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x100000008401#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c8402#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x200000008403#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d8404#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x400000008405#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e8406#define MC_BIST_CMD_CNTL__DONE_MASK 0x800000008407#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f8408#define MC_BIST_CNTL__RESET_MASK 0x18409#define MC_BIST_CNTL__RESET__SHIFT 0x08410#define MC_BIST_CNTL__RUN_MASK 0x28411#define MC_BIST_CNTL__RUN__SHIFT 0x18412#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x48413#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x28414#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x88415#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x38416#define MC_BIST_CNTL__MOP_MODE_MASK 0x108417#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x48418#define MC_BIST_CNTL__ADR_MODE_MASK 0x208419#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x58420#define MC_BIST_CNTL__DAT_MODE_MASK 0x408421#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x68422#define MC_BIST_CNTL__LOOP_MASK 0xc008423#define MC_BIST_CNTL__LOOP__SHIFT 0xa8424#define MC_BIST_CNTL__ENABLE_D0_MASK 0x10008425#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc8426#define MC_BIST_CNTL__ENABLE_D1_MASK 0x20008427#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd8428#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x40008429#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe8430#define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff00008431#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x108432#define MC_BIST_CNTL__DONE_MASK 0x400000008433#define MC_BIST_CNTL__DONE__SHIFT 0x1e8434#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x800000008435#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f8436#define MC_BIST_AUTO_CNTL__MOP_MASK 0x38437#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x08438#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf08439#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x48440#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff008441#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x88442#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x10000008443#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x188444#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x20000008445#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x198446#define MC_BIST_DIR_CNTL__MOP_MASK 0x78447#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x08448#define MC_BIST_DIR_CNTL__EOB_MASK 0x88449#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x38450#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x108451#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x48452#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x208453#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x58454#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x408455#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x68456#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x808457#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x78458#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x1008459#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x88460#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x2008461#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x98462#define MC_BIST_DIR_CNTL__MOP3_MASK 0x4008463#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa8464#define MC_BIST_SADDR__COL_MASK 0x3ff8465#define MC_BIST_SADDR__COL__SHIFT 0x08466#define MC_BIST_SADDR__ROW_MASK 0xfffc008467#define MC_BIST_SADDR__ROW__SHIFT 0xa8468#define MC_BIST_SADDR__BANK_MASK 0xf0000008469#define MC_BIST_SADDR__BANK__SHIFT 0x188470#define MC_BIST_SADDR__RANK_MASK 0x100000008471#define MC_BIST_SADDR__RANK__SHIFT 0x1c8472#define MC_BIST_SADDR__COLH_MASK 0x200000008473#define MC_BIST_SADDR__COLH__SHIFT 0x1d8474#define MC_BIST_SADDR__ROWH_MASK 0xc00000008475#define MC_BIST_SADDR__ROWH__SHIFT 0x1e8476#define MC_BIST_EADDR__COL_MASK 0x3ff8477#define MC_BIST_EADDR__COL__SHIFT 0x08478#define MC_BIST_EADDR__ROW_MASK 0xfffc008479#define MC_BIST_EADDR__ROW__SHIFT 0xa8480#define MC_BIST_EADDR__BANK_MASK 0xf0000008481#define MC_BIST_EADDR__BANK__SHIFT 0x188482#define MC_BIST_EADDR__RANK_MASK 0x100000008483#define MC_BIST_EADDR__RANK__SHIFT 0x1c8484#define MC_BIST_EADDR__COLH_MASK 0x200000008485#define MC_BIST_EADDR__COLH__SHIFT 0x1d8486#define MC_BIST_EADDR__ROWH_MASK 0xc00000008487#define MC_BIST_EADDR__ROWH__SHIFT 0x1e8488#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf8489#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x08490#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff08491#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x48492#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x10008493#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc8494#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x20008495#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd8496#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x40008497#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe8498#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x80008499#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf8500#define MC_BIST_CMP_CNTL__CMP_MASK 0x300008501#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x108502#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x400008503#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x128504#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x800008505#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x138506#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x3000008507#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x148508#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc000008509#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x168510#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f8511#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x08512#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x1008513#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x88514#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f0008515#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc8516#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x1000008517#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x148518#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff8519#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x08520#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff8521#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x08522#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff8523#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x08524#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff8525#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x08526#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff8527#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x08528#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff8529#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x08530#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff8531#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x08532#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff8533#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x08534#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff8535#define MC_BIST_DATA_MASK__MASK__SHIFT 0x08536#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff8537#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x08538#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc008539#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa8540#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf0000008541#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x188542#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x100000008543#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c8544#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x200000008545#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d8546#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc00000008547#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e8548#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff8549#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x08550#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff8551#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x08552#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff8553#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x08554#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff8555#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x08556#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff8557#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x08558#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff8559#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x08560#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff8561#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x08562#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff8563#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x08564#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff8565#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x08566#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff8567#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x08568#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff8569#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x08570#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc00000008571#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e8572#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x18573#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x08574#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x1008575#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x88576#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x2008577#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x98578#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x4008579#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa8580#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x8008581#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb8582#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x10008583#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc8584#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x20008585#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd8586#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x40008587#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe8588#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x80008589#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf8590#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf8591#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x08592#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf08593#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x48594#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf008595#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x88596#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf0008597#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc8598#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf00008599#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x108600#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf000008601#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x148602#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf0000008603#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x188604#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf00000008605#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c8606#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff8607#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x08608#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff8609#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x08610#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff8611#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x08612#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff8613#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x08614#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff8615#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x08616#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff8617#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x08618#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff8619#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x08620#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff8621#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x08622#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x18623#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x08624#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x28625#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x18626#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x48627#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x28628#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x88629#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x38630#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x108631#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x48632#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x208633#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x58634#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x408635#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x68636#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x808637#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x78638#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x1008639#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x88640#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x2008641#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x98642#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x10008643#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc8644#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x20008645#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd8646#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x40008647#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe8648#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x80008649#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf8650#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x100008651#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x108652#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f000008653#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x148654#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x20000008655#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x198656#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x40000008657#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a8658#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x80000008659#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b8660#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x100000008661#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c8662#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x18663#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x08664#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x28665#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x18666#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x108667#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x48668#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x208669#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x58670#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x1008671#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x88672#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x2008673#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x98674#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff8675#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x08676#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff8677#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x08678#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff8679#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x08680#define MC_SEQ_MISC0__VALUE_MASK 0xffffffff8681#define MC_SEQ_MISC0__VALUE__SHIFT 0x08682#define MC_SEQ_MISC1__VALUE_MASK 0xffffffff8683#define MC_SEQ_MISC1__VALUE__SHIFT 0x08684#define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL_MASK 0x18685#define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL__SHIFT 0x08686#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xfffffffe8687#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x18688#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff8689#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x08690#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff8691#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x08692#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff8693#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x08694#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff0008695#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc8696#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff0000008697#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x188698#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff8699#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x08700#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff0008701#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc8702#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff0000008703#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x188704#define MC_SEQ_SUP_CNTL__RUN_MASK 0x18705#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x08706#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x28707#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x18708#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x48709#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x28710#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x88711#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x38712#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x108713#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x48714#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x208715#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x58716#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x408717#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x68718#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x808719#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x78720#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff8000008721#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x178722#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff8723#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x08724#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff8725#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x08726#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff8727#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x08728#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff8729#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x08730#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff8731#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x08732#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff8733#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x08734#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff8735#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x08736#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff8737#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x08738#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff8739#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x08740#define MC_SEQ_MISC3__VALUE_MASK 0xffffffff8741#define MC_SEQ_MISC3__VALUE__SHIFT 0x08742#define MC_SEQ_MISC4__VALUE_MASK 0xffffffff8743#define MC_SEQ_MISC4__VALUE__SHIFT 0x08744#define MC_SEQ_MISC5__VALUE_MASK 0xffffffff8745#define MC_SEQ_MISC5__VALUE__SHIFT 0x08746#define MC_SEQ_MISC6__VALUE_MASK 0xffffffff8747#define MC_SEQ_MISC6__VALUE__SHIFT 0x08748#define MC_SEQ_MISC7__VALUE_MASK 0xffffffff8749#define MC_SEQ_MISC7__VALUE__SHIFT 0x08750#define MC_SEQ_MISC8__VALUE_MASK 0xffffffff8751#define MC_SEQ_MISC8__VALUE__SHIFT 0x08752#define MC_SEQ_MISC9__VALUE_MASK 0xffffffff8753#define MC_SEQ_MISC9__VALUE__SHIFT 0x08754#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff8755#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x08756#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff008757#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x88758#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff00008759#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x108760#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff0000008761#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x188762#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x38763#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x08764#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc8765#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x28766#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x308767#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x48768#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc08769#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x68770#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x38771#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x08772#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc8773#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x28774#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x308775#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x48776#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc08777#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x68778#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x78779#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x08780#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x388781#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x38782#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c08783#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x68784#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe008785#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x98786#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x70008787#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc8788#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x380008789#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf8790#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c00008791#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x128792#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe000008793#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x158794#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x78795#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x08796#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x388797#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x38798#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c08799#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x68800#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe008801#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x98802#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x70008803#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc8804#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x380008805#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf8806#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c00008807#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x128808#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe000008809#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x158810#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x78811#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x08812#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x388813#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x38814#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c08815#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x68816#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe008817#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x98818#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x70008819#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc8820#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x380008821#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf8822#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c00008823#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x128824#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe000008825#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x158826#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x78827#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x08828#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x388829#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x38830#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c08831#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x68832#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe008833#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x98834#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x70008835#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc8836#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x380008837#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf8838#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c00008839#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x128840#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe000008841#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x158842#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x78843#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x08844#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x388845#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x38846#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c08847#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x68848#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe008849#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x98850#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x70008851#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc8852#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x380008853#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf8854#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c00008855#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x128856#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe000008857#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x158858#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x78859#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x08860#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x388861#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x38862#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c08863#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x68864#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe008865#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x98866#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x70008867#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc8868#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x380008869#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf8870#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c00008871#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x128872#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe000008873#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x158874#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x78875#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x08876#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x388877#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x38878#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c08879#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x68880#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe008881#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x98882#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x70008883#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc8884#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x380008885#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf8886#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c00008887#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x128888#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe000008889#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x158890#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x78891#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x08892#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x388893#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x38894#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c08895#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x68896#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe008897#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x98898#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x70008899#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc8900#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x380008901#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf8902#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c00008903#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x128904#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe000008905#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x158906#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f8907#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x08908#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e08909#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x58910#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c008911#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa8912#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf80008913#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf8914#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf000008915#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x148916#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f0000008917#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x188918#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x38919#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x08920#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc8921#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x28922#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f08923#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x48924#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe008925#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x98926#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf0008927#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc8928#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f00008929#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x108930#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f0000008931#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x188932#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f8933#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x08934#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f008935#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x88936#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf80008937#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf8938#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff000008939#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x148940#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x78941#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x08942#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x708943#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x48944#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f008945#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x88946#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe0008947#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd8948#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f00008949#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x108950#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe000008951#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x158952#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf0000008953#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x188954#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf00000008955#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c8956#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x78957#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x08958#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf88959#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x38960#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x3008961#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x88962#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc008963#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa8964#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf0008965#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc8966#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x100008967#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x108968#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x200008969#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x118970#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f000008971#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x148972#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e0000008973#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x198974#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x78975#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x08976#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf88977#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x38978#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x3008979#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x88980#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc008981#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa8982#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf0008983#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc8984#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x100008985#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x108986#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x200008987#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x118988#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f000008989#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x148990#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e0000008991#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x198992#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf8993#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x08994#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf08995#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x48996#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x1008997#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x88998#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x2008999#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x99000#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x4009001#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa9002#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x8009003#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb9004#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf0009005#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc9006#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf00009007#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x109008#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x3000009009#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x149010#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf0000009011#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x189012#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x100000009013#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c9014#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x200000009015#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d9016#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x400000009017#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e9018#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf9019#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x09020#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf09021#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x49022#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x1009023#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x89024#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x2009025#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x99026#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x4009027#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa9028#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x8009029#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb9030#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf0009031#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc9032#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf00009033#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x109034#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x3000009035#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x149036#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf0000009037#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x189038#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x100000009039#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c9040#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x200000009041#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d9042#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x400000009043#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e9044#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x19045#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x09046#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x29047#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x19048#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x49049#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x29050#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x89051#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x39052#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x109053#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x49054#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x209055#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x59056#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x409057#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x69058#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff9059#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x09060#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x700009061#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x109062#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x800009063#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x139064#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x1000009065#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x149066#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x6000009067#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x159068#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x100000009069#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c9070#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x200000009071#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d9072#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff9073#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x09074#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x700009075#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x109076#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x800009077#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x139078#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x1000009079#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x149080#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x6000009081#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x159082#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x100000009083#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c9084#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x200000009085#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d9086#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff9087#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x09088#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x700009089#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x109090#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x800009091#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x139092#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x1000009093#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x149094#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x6000009095#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x159096#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x100000009097#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c9098#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x200000009099#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d9100#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff9101#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x09102#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x700009103#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x109104#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x800009105#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x139106#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x1000009107#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x149108#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x6000009109#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x159110#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x100000009111#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c9112#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x200000009113#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d9114#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x79115#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x09116#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x709117#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x49118#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf009119#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x89120#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f0009121#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc9122#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c00009123#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x129124#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x8000009125#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x179126#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff0000009127#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x189128#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff9129#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x09130#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff9131#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x09132#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff9133#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x09134#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff9135#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x09136#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff9137#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x09138#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff9139#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x09140#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff9141#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x09142#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff9143#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x09144#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff9145#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x09146#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff9147#define MC_SEQ_IO_REDC__EDC__SHIFT 0x09148#define MC_SEQ_TCG_CNTL__RESET_MASK 0x19149#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x09150#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x29151#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x19152#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x49153#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x29154#define MC_SEQ_TCG_CNTL__START_MASK 0x89155#define MC_SEQ_TCG_CNTL__START__SHIFT 0x39156#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x709157#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x49158#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x809159#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x79160#define MC_SEQ_TCG_CNTL__MOP_MASK 0xf009161#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x89162#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf0009163#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc9164#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x100009165#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x109166#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x200009167#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x119168#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x400009169#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x129170#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x3800009171#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x139172#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x4000009173#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x169174#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x8000009175#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x179176#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x10000009177#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x189178#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x20000009179#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x199180#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x40000009181#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a9182#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x100000009183#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c9184#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x200000009185#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d9186#define MC_SEQ_TCG_CNTL__DONE_MASK 0x800000009187#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f9188#define MC_SEQ_TSM_CTRL__START_MASK 0x19189#define MC_SEQ_TSM_CTRL__START__SHIFT 0x09190#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x29191#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x19192#define MC_SEQ_TSM_CTRL__DONE_MASK 0x49193#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x29194#define MC_SEQ_TSM_CTRL__ERR_MASK 0x89195#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x39196#define MC_SEQ_TSM_CTRL__STEP_MASK 0x109197#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x49198#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x209199#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x59200#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x409201#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x69202#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x809203#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x79204#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x3009205#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x89206#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x4009207#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa9208#define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x8009209#define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb9210#define MC_SEQ_TSM_CTRL__DONE0_MASK 0x10009211#define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc9212#define MC_SEQ_TSM_CTRL__DONE1_MASK 0x20009213#define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd9214#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff00009215#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x109216#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf9217#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x09218#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf09219#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x49220#define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff009221#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x89222#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff00009223#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x109224#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf9225#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x09226#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf09227#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x49228#define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff009229#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x89230#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff00009231#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x109232#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf9233#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x09234#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf09235#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x49236#define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff009237#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x89238#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf00009239#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x109240#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf000009241#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x149242#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf0000009243#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x189244#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf9245#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x09246#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf09247#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x49248#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff009249#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x89250#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff00009251#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x109252#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff0000009253#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x189254#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf9255#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x09256#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf09257#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x49258#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff009259#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x89260#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf00009261#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x109262#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff0000009263#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x189264#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf9265#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x09266#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf09267#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x49268#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff009269#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x89270#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff00009271#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x109272#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff0000009273#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x189274#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff9275#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x09276#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff9277#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x09278#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff9279#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x09280#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff9281#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x09282#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf00009283#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x109284#define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f000009285#define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x149286#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc0000009287#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a9288#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff9289#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x09290#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff9291#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x09292#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff9293#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x09294#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff00009295#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x109296#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf9297#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x09298#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf09299#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x49300#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf009301#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x89302#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf0009303#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc9304#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x700009305#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x109306#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf000009307#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x149308#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x70000009309#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x189310#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf00000009311#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c9312#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf9313#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x09314#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf09315#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x49316#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf009317#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x89318#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf0009319#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc9320#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x700009321#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x109322#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf000009323#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x149324#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x70000009325#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x189326#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf00000009327#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c9328#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f9329#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x09330#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x1009331#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x89332#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x2009333#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x99334#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x4009335#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa9336#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x8009337#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb9338#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x10009339#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc9340#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x20009341#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd9342#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x40009343#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe9344#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x80009345#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf9346#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x100009347#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x109348#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x200009349#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x119350#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x400009351#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x129352#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x800009353#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x139354#define MC_PHY_TIMING_2__WR_DLY_MASK 0xf000009355#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x149356#define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x10000009357#define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x189358#define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x20000009359#define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x199360#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x19361#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x09362#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x29363#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x19364#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x49365#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x29366#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x89367#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x39368#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x109369#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x49370#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x209371#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x59372#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x409373#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x69374#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x809375#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x79376#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f9377#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x09378#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x409379#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x69380#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x809381#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x79382#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x1009383#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x89384#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x2009385#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x99386#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x100009387#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x109388#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x200009389#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x119390#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x10000009391#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x189392#define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff9393#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x09394#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff0009395#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc9396#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x10000009397#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x189398#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x20000009399#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x199400#define DLL_CNTL__PWR2_MODE_MASK 0x40000009401#define DLL_CNTL__PWR2_MODE__SHIFT 0x1a9402#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf9403#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x09404#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf09405#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x49406#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf009407#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x89408#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf0009409#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc9410#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf00009411#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x109412#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf000009413#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x149414#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf0000009415#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x189416#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf00000009417#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c9418#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf9419#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x09420#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf09421#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x49422#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf009423#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x89424#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf0009425#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc9426#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf00009427#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x109428#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf000009429#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x149430#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf0000009431#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x189432#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf00000009433#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c9434#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff9435#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x09436#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x1009437#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x89438#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x8009439#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb9440#define MPLL_CNTL_MODE__SPARE_1_MASK 0x10009441#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc9442#define MPLL_CNTL_MODE__QDR_MASK 0x20009443#define MPLL_CNTL_MODE__QDR__SHIFT 0xd9444#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x40009445#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe9446#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x100009447#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x109448#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x200009449#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x119450#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x1000009451#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x149452#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x6000009453#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x159454#define MPLL_CNTL_MODE__SPARE_2_MASK 0x8000009455#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x179456#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x30000009457#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x189458#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x40000009459#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a9460#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x80000009461#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b9462#define MPLL_CNTL_MODE__SPARE_3_MASK 0x700000009463#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c9464#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x800000009465#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f9466#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x209467#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x59468#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf009469#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x89470#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf00009471#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x109472#define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff000009473#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x149474#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc00000009475#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e9476#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x39477#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x09478#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc9479#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x29480#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff09481#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x49482#define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff00009483#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x109484#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf00000009485#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c9486#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x19487#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x09488#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x29489#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x19490#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x49491#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x29492#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x89493#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x39494#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x109495#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x49496#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x209497#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x59498#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x409499#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x69500#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x809501#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x79502#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x1009503#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x89504#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x2009505#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x99506#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc009507#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa9508#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x30009509#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc9510#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x40009511#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe9512#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x80009513#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf9514#define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x100009515#define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x109516#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe00009517#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x119518#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f000009519#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x149520#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf80000009521#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b9522#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x79523#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x09524#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff89525#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x39526#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x79527#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x09528#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x89529#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x39530#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x109531#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x49532#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe09533#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x59534#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff9535#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x09536#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff00009537#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x109538#define MPLL_SS1__CLKV_MASK 0x3ffffff9539#define MPLL_SS1__CLKV__SHIFT 0x09540#define MPLL_SS1__SPARE_MASK 0xfc0000009541#define MPLL_SS1__SPARE__SHIFT 0x1a9542#define MPLL_SS2__CLKS_MASK 0xfff9543#define MPLL_SS2__CLKS__SHIFT 0x09544#define MPLL_SS2__SPARE_MASK 0xfffff0009545#define MPLL_SS2__SPARE__SHIFT 0xc9546#define MPLL_CONTROL__GDDR_PWRON_MASK 0x19547#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x09548#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x29549#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x19550#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x49551#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x29552#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x10009553#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc9554#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x20009555#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd9556#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x40009557#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe9558#define MPLL_CONTROL__SPARE_AD_0_MASK 0x80009559#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf9560#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x100009561#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x109562#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x200009563#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x119564#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x400009565#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x129566#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x800009567#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x139568#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x1000009569#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x149570#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x2000009571#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x159572#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x4000009573#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x169574#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x8000009575#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x179576#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x10000009577#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x189578#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x20000009579#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x199580#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x40000009581#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a9582#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x80000009583#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b9584#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x100000009585#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c9586#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x200000009587#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d9588#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x400000009589#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e9590#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x800000009591#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f9592#define MPLL_AD_STATUS__VCTRLADC_MASK 0x79593#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x09594#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x709595#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x49596#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff809597#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x79598#define MPLL_AD_STATUS__OINT_RESET_MASK 0x200009599#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x119600#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x400009601#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x129602#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x800009603#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x139604#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x79605#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x09606#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x709607#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x49608#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff809609#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x79610#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x200009611#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x119612#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x400009613#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x129614#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x800009615#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x139616#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x79617#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x09618#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x709619#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x49620#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff809621#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x79622#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x200009623#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x119624#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x400009625#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x129626#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x800009627#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x139628#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x79629#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x09630#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x709631#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x49632#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff809633#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x79634#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x200009635#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x119636#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x400009637#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x129638#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x800009639#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x139640#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x79641#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x09642#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x709643#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x49644#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff809645#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x79646#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x200009647#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x119648#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x400009649#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x129650#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x800009651#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x139652#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x19653#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x09654#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x29655#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x19656#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c9657#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x29658#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc09659#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x69660#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x3009661#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x89662#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c009663#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa9664#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x100009665#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x109666#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x200009667#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x119668#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x400009669#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x129670#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x19671#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x09672#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x29673#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x19674#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x49675#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x29676#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x89677#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x39678#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x109679#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x49680#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x209681#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x59682#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x409683#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x69684#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x809685#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x79686#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x1009687#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x89688#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x2009689#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x99690#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x4009691#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa9692#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x8009693#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb9694#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x10009695#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc9696#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x20009697#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd9698#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x40009699#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe9700#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x80009701#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf9702#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x100009703#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x109704#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x800000009705#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f9706#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x19707#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x09708#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x29709#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x19710#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x49711#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x29712#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x89713#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x39714#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x109715#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x49716#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x209717#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x59718#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x409719#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x69720#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x809721#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x79722#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x1009723#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x89724#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x2009725#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x99726#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x4009727#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa9728#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x8009729#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb9730#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x10009731#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc9732#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x20009733#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd9734#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x40009735#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe9736#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x80009737#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf9738#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x100009739#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x109740#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x800000009741#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f9742#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f9743#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x09744#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff9745#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x09746#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff9747#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x09748#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff9749#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x09750#define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff9751#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x09752#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf009753#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x89754#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf0009755#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc9756#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff9757#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x09758#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff009759#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x89760#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff00009761#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x109762#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff0000009763#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x189764#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff9765#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x09766#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff009767#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x89768#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff00009769#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x109770#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff0000009771#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x189772#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff9773#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x09774#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff009775#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x89776#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff00009777#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x109778#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff0000009779#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x189780#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff9781#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x09782#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff009783#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x89784#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff00009785#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x109786#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff0000009787#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x189788#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff9789#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x09790#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff009791#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x89792#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff00009793#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x109794#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff0000009795#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x189796#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff9797#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x09798#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff009799#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x89800#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff00009801#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x109802#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff0000009803#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x189804#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff9805#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x09806#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff009807#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x89808#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff00009809#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x109810#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff0000009811#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x189812#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff9813#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x09814#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff009815#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x89816#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff00009817#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x109818#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff0000009819#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x189820#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff9821#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x09822#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff009823#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x89824#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff00009825#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x109826#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff0000009827#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x189828#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff9829#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x09830#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff009831#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x89832#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff00009833#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x109834#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff0000009835#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x189836#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff9837#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x09838#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff009839#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x89840#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff00009841#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x109842#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff0000009843#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x189844#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff9845#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x09846#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff9847#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x09848#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff9849#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x09850#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff9851#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x09852#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff9853#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x09854#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff9855#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x09856#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff9857#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x09858#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff009859#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x89860#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff00009861#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x109862#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff0000009863#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x189864#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff9865#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x09866#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff009867#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x89868#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff00009869#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x109870#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff0000009871#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x189872#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff9873#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x09874#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff009875#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x89876#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff00009877#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x109878#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff0000009879#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x189880#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff9881#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x09882#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff009883#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x89884#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff00009885#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x109886#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff0000009887#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x189888#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff9889#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x09890#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff009891#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x89892#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff00009893#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x109894#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff0000009895#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x189896#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff9897#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x09898#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff009899#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x89900#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff00009901#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x109902#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff0000009903#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x189904#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff9905#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x09906#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff009907#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x89908#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff00009909#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x109910#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff0000009911#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x189912#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff9913#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x09914#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff009915#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x89916#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff00009917#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x109918#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff0000009919#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x189920#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff9921#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x09922#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff009923#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x89924#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff00009925#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x109926#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff0000009927#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x189928#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff9929#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x09930#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff009931#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x89932#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff00009933#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x109934#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff0000009935#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x189936#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff9937#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x09938#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff009939#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x89940#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff00009941#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x109942#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff0000009943#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x189944#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff9945#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x09946#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff009947#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x89948#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff00009949#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x109950#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff0000009951#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x189952#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff9953#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x09954#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff009955#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x89956#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff00009957#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x109958#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff0000009959#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x189960#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff9961#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x09962#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff009963#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x89964#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff00009965#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x109966#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff0000009967#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x189968#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff9969#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x09970#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff009971#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x89972#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff00009973#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x109974#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff0000009975#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x189976#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff9977#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x09978#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff009979#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x89980#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff00009981#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x109982#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff0000009983#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x189984#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff9985#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x09986#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff009987#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x89988#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff00009989#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x109990#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff0000009991#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x189992#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff9993#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x09994#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff009995#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x89996#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff00009997#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x109998#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff0000009999#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x1810000#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff10001#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x010002#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff0010003#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x810004#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff000010005#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x1010006#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff00000010007#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x1810008#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff10009#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x010010#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff0010011#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x810012#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff000010013#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x1010014#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff00000010015#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x1810016#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff10017#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x010018#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff0010019#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x810020#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff000010021#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x1010022#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff00000010023#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x1810024#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff10025#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x010026#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff0010027#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x810028#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff000010029#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x1010030#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff00000010031#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x1810032#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff10033#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x010034#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff0010035#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x810036#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff000010037#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x1010038#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff00000010039#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x1810040#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff10041#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x010042#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff0010043#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x810044#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff000010045#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x1010046#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff00000010047#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x1810048#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff10049#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x010050#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff0010051#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x810052#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff000010053#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x1010054#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff00000010055#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x1810056#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff10057#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x010058#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff0010059#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x810060#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff000010061#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x1010062#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff00000010063#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x1810064#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff10065#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x010066#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff0010067#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x810068#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff000010069#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x1010070#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff00000010071#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x1810072#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff10073#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x010074#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff0010075#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x810076#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff000010077#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x1010078#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff00000010079#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x1810080#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff10081#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x010082#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff0010083#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x810084#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff000010085#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x1010086#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff00000010087#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x1810088#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff10089#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x010090#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff0010091#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x810092#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff000010093#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x1010094#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff00000010095#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x1810096#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff10097#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x010098#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff0010099#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x810100#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff000010101#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x1010102#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff00000010103#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x1810104#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff10105#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x010106#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff0010107#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x810108#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff000010109#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x1010110#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff00000010111#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x1810112#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff10113#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x010114#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff0010115#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x810116#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff000010117#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x1010118#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff00000010119#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x1810120#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff10121#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x010122#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff0010123#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x810124#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff000010125#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x1010126#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff00000010127#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x1810128#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff10129#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x010130#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff0010131#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x810132#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff000010133#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x1010134#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff00000010135#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x1810136#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff10137#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x010138#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff0010139#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x810140#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff000010141#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x1010142#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff00000010143#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x1810144#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff10145#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x010146#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff0010147#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x810148#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff000010149#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x1010150#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff00000010151#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x1810152#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff10153#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x010154#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff0010155#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x810156#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff000010157#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x1010158#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff00000010159#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x1810160#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff10161#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x010162#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff0010163#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x810164#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff000010165#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x1010166#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff00000010167#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x1810168#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff10169#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x010170#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff0010171#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x810172#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff000010173#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x1010174#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff00000010175#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x1810176#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff10177#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x010178#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff0010179#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x810180#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff000010181#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x1010182#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff00000010183#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x1810184#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff10185#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x010186#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff0010187#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x810188#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff000010189#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x1010190#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff00000010191#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x1810192#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff10193#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x010194#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff0010195#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x810196#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff000010197#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x1010198#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff00000010199#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x1810200#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff10201#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x010202#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff0010203#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x810204#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff000010205#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x1010206#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff00000010207#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x1810208#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff10209#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x010210#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff0010211#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x810212#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff000010213#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x1010214#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff00000010215#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x1810216#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff10217#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x010218#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff0010219#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x810220#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff000010221#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x1010222#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff00000010223#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x1810224#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff10225#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x010226#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff0010227#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x810228#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff000010229#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x1010230#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff00000010231#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x1810232#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff10233#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x010234#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff0010235#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x810236#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff000010237#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x1010238#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff00000010239#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x1810240#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff10241#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x010242#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff0010243#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x810244#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff000010245#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x1010246#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff00000010247#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x1810248#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff10249#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x010250#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff0010251#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x810252#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff000010253#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x1010254#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff00000010255#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x1810256#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff10257#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x010258#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff0010259#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x810260#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff000010261#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x1010262#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff00000010263#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x1810264#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff10265#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x010266#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff0010267#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x810268#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff000010269#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x1010270#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff00000010271#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x1810272#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff10273#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x010274#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff0010275#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x810276#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff000010277#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x1010278#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff00000010279#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x1810280#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff10281#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x010282#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff0010283#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x810284#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff000010285#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x1010286#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff00000010287#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x1810288#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff10289#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x010290#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff0010291#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x810292#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff000010293#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x1010294#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff00000010295#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x1810296#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff10297#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x010298#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff0010299#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x810300#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff000010301#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x1010302#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff00000010303#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x1810304#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff10305#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x010306#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff0010307#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x810308#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff000010309#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x1010310#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff00000010311#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x1810312#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff10313#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x010314#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff0010315#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x810316#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff000010317#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x1010318#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff00000010319#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x1810320#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff10321#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x010322#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff0010323#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x810324#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff000010325#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x1010326#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff00000010327#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x1810328#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff10329#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x010330#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff0010331#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x810332#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff000010333#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x1010334#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff00000010335#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x1810336#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff10337#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x010338#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff0010339#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x810340#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff000010341#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x1010342#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff00000010343#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x1810344#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff10345#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x010346#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff0010347#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x810348#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff000010349#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x1010350#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff00000010351#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x1810352#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff10353#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x010354#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff0010355#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x810356#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff000010357#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x1010358#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff00000010359#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x1810360#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff10361#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x010362#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff0010363#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x810364#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff000010365#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x1010366#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff00000010367#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x1810368#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff10369#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x010370#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff0010371#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x810372#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff000010373#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x1010374#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff00000010375#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x1810376#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff10377#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x010378#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff0010379#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x810380#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff000010381#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x1010382#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff00000010383#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x1810384#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff10385#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x010386#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff0010387#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x810388#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff000010389#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x1010390#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff00000010391#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x1810392#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff10393#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x010394#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff0010395#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x810396#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff000010397#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x1010398#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff00000010399#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x1810400#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff10401#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x010402#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff0010403#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x810404#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff000010405#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x1010406#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff00000010407#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x1810408#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff10409#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x010410#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff0010411#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x810412#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff000010413#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x1010414#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff00000010415#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x1810416#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff10417#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x010418#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff0010419#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x810420#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff000010421#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x1010422#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff00000010423#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x1810424#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff10425#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x010426#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff0010427#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x810428#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff000010429#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x1010430#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff00000010431#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x1810432#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff10433#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x010434#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff0010435#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x810436#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff000010437#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x1010438#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff00000010439#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x1810440#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff10441#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x010442#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff0010443#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x810444#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff000010445#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x1010446#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff00000010447#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x1810448#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff10449#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x010450#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff0010451#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x810452#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff000010453#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x1010454#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff00000010455#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x1810456#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff10457#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x010458#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff0010459#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x810460#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff000010461#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x1010462#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff00000010463#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x1810464#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff10465#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x010466#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff0010467#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x810468#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff000010469#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x1010470#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff00000010471#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x1810472#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff10473#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x010474#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff0010475#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x810476#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff000010477#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x1010478#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff00000010479#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x1810480#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff10481#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x010482#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff0010483#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x810484#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff000010485#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x1010486#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff00000010487#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x1810488#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff10489#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x010490#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff0010491#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x810492#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff000010493#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x1010494#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff00000010495#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x1810496#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff10497#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x010498#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff0010499#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x810500#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff000010501#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x1010502#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff00000010503#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x1810504#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff10505#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x010506#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff0010507#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x810508#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff000010509#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x1010510#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff00000010511#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x1810512#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff10513#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x010514#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff0010515#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x810516#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff000010517#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x1010518#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff00000010519#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x1810520#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff10521#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x010522#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff0010523#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x810524#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff000010525#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x1010526#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff00000010527#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x1810528#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff10529#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x010530#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff0010531#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x810532#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff000010533#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x1010534#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff00000010535#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x1810536#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff10537#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x010538#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff0010539#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x810540#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff000010541#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x1010542#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff00000010543#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x1810544#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff10545#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x010546#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff0010547#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x810548#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff000010549#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x1010550#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff00000010551#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x1810552#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff10553#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x010554#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff0010555#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x810556#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff000010557#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x1010558#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff00000010559#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x1810560#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff10561#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x010562#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff0010563#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x810564#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff000010565#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x1010566#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff00000010567#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x1810568#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff10569#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x010570#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff0010571#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x810572#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff000010573#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x1010574#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff00000010575#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x1810576#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff10577#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x010578#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff0010579#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x810580#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff000010581#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x1010582#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff00000010583#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x1810584#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff10585#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x010586#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff0010587#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x810588#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff000010589#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x1010590#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff00000010591#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x1810592#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff10593#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x010594#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff0010595#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x810596#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff000010597#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x1010598#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff00000010599#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x1810600#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff10601#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x010602#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff0010603#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x810604#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff000010605#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x1010606#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff00000010607#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x1810608#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff10609#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x010610#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff0010611#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x810612#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff000010613#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x1010614#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff00000010615#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x1810616#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff10617#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x010618#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff0010619#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x810620#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff000010621#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x1010622#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff00000010623#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x1810624#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff10625#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x010626#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff0010627#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x810628#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff000010629#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x1010630#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff00000010631#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x1810632#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff10633#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x010634#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff0010635#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x810636#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff000010637#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x1010638#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff00000010639#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x1810640#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff10641#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x010642#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff0010643#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x810644#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff000010645#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x1010646#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff00000010647#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x1810648#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff10649#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x010650#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff0010651#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x810652#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff000010653#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x1010654#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff00000010655#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x1810656#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff10657#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x010658#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff0010659#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x810660#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff000010661#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x1010662#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff00000010663#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x1810664#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff10665#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x010666#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff0010667#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x810668#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff000010669#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x1010670#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff00000010671#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x1810672#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff10673#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x010674#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff0010675#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x810676#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff000010677#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x1010678#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff00000010679#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x1810680#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff10681#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x010682#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff0010683#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x810684#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff000010685#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x1010686#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff00000010687#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x1810688#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff10689#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x010690#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff0010691#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x810692#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff000010693#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x1010694#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff00000010695#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x1810696#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff10697#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x010698#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff0010699#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x810700#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff000010701#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x1010702#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff00000010703#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x1810704#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff10705#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x010706#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff0010707#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x810708#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff000010709#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x1010710#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff00000010711#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x1810712#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff10713#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x010714#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff0010715#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x810716#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff000010717#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x1010718#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff00000010719#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x1810720#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff10721#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x010722#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff0010723#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x810724#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff000010725#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x1010726#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff00000010727#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x1810728#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff10729#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x010730#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff0010731#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x810732#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff000010733#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x1010734#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff00000010735#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x1810736#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff10737#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x010738#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff0010739#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x810740#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff000010741#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x1010742#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff00000010743#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x1810744#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff10745#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x010746#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff0010747#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x810748#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff000010749#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x1010750#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff00000010751#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x1810752#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff10753#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x010754#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff0010755#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x810756#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff000010757#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x1010758#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff00000010759#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x1810760#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff10761#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x010762#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff0010763#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x810764#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff000010765#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x1010766#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff00000010767#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x1810768#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff10769#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x010770#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff0010771#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x810772#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff000010773#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x1010774#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff00000010775#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x1810776#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff10777#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x010778#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff0010779#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x810780#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff000010781#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x1010782#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff00000010783#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x1810784#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff10785#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x010786#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff0010787#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x810788#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff000010789#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x1010790#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff00000010791#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x1810792#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff10793#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x010794#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff0010795#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x810796#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff000010797#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x1010798#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff00000010799#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x1810800#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff10801#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x010802#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff0010803#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x810804#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff000010805#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x1010806#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff00000010807#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x1810808#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff10809#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x010810#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff0010811#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x810812#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff000010813#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x1010814#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff00000010815#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x1810816#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff10817#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x010818#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff0010819#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x810820#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff000010821#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x1010822#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff00000010823#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x1810824#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff10825#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x010826#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff0010827#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x810828#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff000010829#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x1010830#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff00000010831#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x1810832#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff10833#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x010834#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff0010835#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x810836#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff000010837#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x1010838#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff00000010839#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x1810840#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff10841#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x010842#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff0010843#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x810844#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff000010845#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x1010846#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff00000010847#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x1810848#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff10849#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x010850#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff0010851#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x810852#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff000010853#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x1010854#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff00000010855#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x1810856#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff10857#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x010858#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff0010859#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x810860#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff000010861#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x1010862#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff00000010863#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x1810864#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff10865#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x010866#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff0010867#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x810868#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff000010869#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x1010870#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff00000010871#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x1810872#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff10873#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x010874#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff0010875#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x810876#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff000010877#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x1010878#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff00000010879#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x1810880#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff10881#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x010882#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff0010883#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x810884#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff000010885#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x1010886#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff00000010887#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x1810888#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff10889#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x010890#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff0010891#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x810892#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff000010893#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x1010894#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff00000010895#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x1810896#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff10897#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x010898#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff0010899#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x810900#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff000010901#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x1010902#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff00000010903#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x1810904#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff10905#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x010906#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff0010907#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x810908#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff000010909#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x1010910#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff00000010911#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x1810912#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff10913#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x010914#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff0010915#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x810916#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff000010917#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x1010918#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff00000010919#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x1810920#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff10921#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x010922#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff0010923#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x810924#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff000010925#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x1010926#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff00000010927#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x1810928#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff10929#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x010930#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff0010931#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x810932#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff000010933#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x1010934#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff00000010935#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x1810936#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff10937#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x010938#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff0010939#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x810940#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff000010941#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x1010942#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff00000010943#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x1810944#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff10945#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x010946#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff0010947#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x810948#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff000010949#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x1010950#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff00000010951#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x1810952#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff10953#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x010954#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff0010955#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x810956#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff000010957#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x1010958#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff00000010959#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x1810960#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff10961#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x010962#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff0010963#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x810964#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff000010965#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x1010966#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff00000010967#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x1810968#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff10969#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x010970#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff0010971#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x810972#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff000010973#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x1010974#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff00000010975#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x1810976#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff10977#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x010978#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff0010979#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x810980#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff000010981#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x1010982#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff00000010983#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x1810984#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff10985#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x010986#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff0010987#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x810988#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff000010989#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x1010990#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff00000010991#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x1810992#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff10993#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x010994#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff0010995#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x810996#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff000010997#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x1010998#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff00000010999#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x1811000#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff11001#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x011002#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff0011003#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x811004#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff000011005#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x1011006#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff00000011007#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x1811008#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff11009#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x011010#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff0011011#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x811012#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff000011013#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x1011014#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff00000011015#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x1811016#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff11017#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x011018#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff0011019#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x811020#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff000011021#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x1011022#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff00000011023#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x1811024#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff11025#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x011026#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff0011027#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x811028#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff000011029#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x1011030#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff00000011031#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x1811032#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff11033#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x011034#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff0011035#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x811036#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff000011037#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x1011038#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff00000011039#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x1811040#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff11041#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x011042#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff0011043#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x811044#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff000011045#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x1011046#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff00000011047#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x1811048#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff11049#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x011050#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff0011051#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x811052#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff000011053#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x1011054#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff00000011055#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x1811056#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff11057#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x011058#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff0011059#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x811060#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff000011061#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x1011062#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff00000011063#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x1811064#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff11065#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x011066#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff0011067#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x811068#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff000011069#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x1011070#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff00000011071#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x1811072#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff11073#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x011074#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff0011075#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x811076#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff000011077#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x1011078#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff00000011079#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x1811080#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff11081#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x011082#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff0011083#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x811084#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff000011085#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x1011086#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff00000011087#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x1811088#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff11089#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x011090#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff0011091#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x811092#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff000011093#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x1011094#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff00000011095#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x1811096#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff11097#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x011098#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff0011099#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x811100#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff000011101#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x1011102#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff00000011103#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x1811104#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff11105#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x011106#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff0011107#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x811108#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff000011109#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x1011110#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff00000011111#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x1811112#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff11113#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x011114#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff0011115#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x811116#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff000011117#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x1011118#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff00000011119#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x1811120#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff11121#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x011122#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff0011123#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x811124#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff000011125#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x1011126#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff00000011127#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x1811128#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff11129#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x011130#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff0011131#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x811132#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff000011133#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x1011134#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff00000011135#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x1811136#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff11137#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x011138#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff0011139#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x811140#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff000011141#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x1011142#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff00000011143#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x1811144#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff11145#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x011146#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff0011147#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x811148#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff000011149#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x1011150#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff00000011151#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x1811152#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff11153#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x011154#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff0011155#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x811156#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff000011157#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x1011158#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff00000011159#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x1811160#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff11161#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x011162#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff0011163#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x811164#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff000011165#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x1011166#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff00000011167#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x1811168#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff11169#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x011170#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff0011171#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x811172#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff000011173#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x1011174#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff00000011175#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x1811176#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff11177#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x011178#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff0011179#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x811180#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff000011181#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x1011182#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff00000011183#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x1811184#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff11185#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x011186#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff0011187#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x811188#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff000011189#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x1011190#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff00000011191#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x1811192#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff11193#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x011194#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff0011195#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x811196#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff000011197#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x1011198#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff00000011199#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x1811200#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff11201#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x011202#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff0011203#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x811204#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff000011205#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x1011206#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff00000011207#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x1811208#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff11209#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x011210#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff0011211#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x811212#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff000011213#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x1011214#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff00000011215#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x1811216#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff11217#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x011218#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff0011219#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x811220#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff000011221#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x1011222#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff00000011223#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x1811224#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff11225#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x011226#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff0011227#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x811228#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff000011229#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x1011230#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff00000011231#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x1811232#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff11233#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x011234#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff0011235#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x811236#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff000011237#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x1011238#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff00000011239#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x1811240#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff11241#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x011242#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff0011243#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x811244#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff000011245#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x1011246#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff00000011247#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x1811248#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff11249#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x011250#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff0011251#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x811252#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff000011253#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x1011254#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff00000011255#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x1811256#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff11257#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x011258#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff0011259#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x811260#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff000011261#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x1011262#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff00000011263#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x1811264#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff11265#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x011266#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff0011267#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x811268#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff000011269#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x1011270#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff00000011271#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x1811272#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff11273#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x011274#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff0011275#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x811276#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff000011277#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x1011278#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff00000011279#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x1811280#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff11281#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x011282#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff0011283#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x811284#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff000011285#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x1011286#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff00000011287#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x1811288#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff11289#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x011290#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff0011291#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x811292#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff000011293#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x1011294#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff00000011295#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x1811296#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff11297#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x011298#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff0011299#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x811300#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff000011301#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x1011302#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff00000011303#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x1811304#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff11305#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x011306#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff0011307#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x811308#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff000011309#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x1011310#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff00000011311#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x1811312#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff11313#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x011314#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff0011315#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x811316#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff000011317#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x1011318#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff00000011319#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x1811320#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff11321#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x011322#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff0011323#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x811324#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff000011325#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x1011326#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff00000011327#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x1811328#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff11329#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x011330#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff0011331#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x811332#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff000011333#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x1011334#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff00000011335#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x1811336#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff11337#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x011338#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff0011339#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x811340#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff000011341#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x1011342#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff00000011343#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x1811344#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff11345#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x011346#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff0011347#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x811348#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff000011349#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x1011350#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff00000011351#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x1811352#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff11353#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x011354#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff0011355#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x811356#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff000011357#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x1011358#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff00000011359#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x1811360#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff11361#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x011362#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff0011363#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x811364#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff000011365#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x1011366#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff00000011367#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x1811368#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff11369#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x011370#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff0011371#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x811372#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff000011373#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x1011374#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff00000011375#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x1811376#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff11377#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x011378#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff0011379#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x811380#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff000011381#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x1011382#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff00000011383#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x1811384#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff11385#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x011386#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff0011387#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x811388#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff000011389#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x1011390#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff00000011391#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x1811392#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff11393#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x011394#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff0011395#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x811396#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff000011397#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x1011398#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff00000011399#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x1811400#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff11401#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x011402#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff0011403#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x811404#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff000011405#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x1011406#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff00000011407#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x1811408#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff11409#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x011410#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff0011411#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x811412#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff000011413#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x1011414#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff00000011415#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x1811416#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff11417#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x011418#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff0011419#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x811420#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff000011421#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x1011422#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff00000011423#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x1811424#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff11425#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x011426#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff0011427#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x811428#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff000011429#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x1011430#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff00000011431#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x1811432#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff11433#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x011434#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff0011435#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x811436#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff000011437#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x1011438#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff00000011439#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x1811440#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff11441#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x011442#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff0011443#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x811444#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff000011445#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x1011446#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff00000011447#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x1811448#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff11449#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x011450#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff0011451#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x811452#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff000011453#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x1011454#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff00000011455#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x1811456#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff11457#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x011458#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff0011459#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x811460#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff000011461#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x1011462#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff00000011463#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x1811464#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff11465#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x011466#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff0011467#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x811468#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff000011469#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x1011470#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff00000011471#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x1811472#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff11473#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x011474#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff0011475#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x811476#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff000011477#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x1011478#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff00000011479#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x1811480#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff11481#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x011482#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff0011483#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x811484#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff000011485#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x1011486#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff00000011487#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x1811488#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff11489#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x011490#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff0011491#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x811492#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff000011493#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x1011494#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff00000011495#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x1811496#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff11497#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x011498#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff0011499#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x811500#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff000011501#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x1011502#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff00000011503#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x1811504#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff11505#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x011506#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff0011507#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x811508#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff000011509#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x1011510#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff00000011511#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x1811512#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff11513#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x011514#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff0011515#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x811516#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff000011517#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x1011518#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff00000011519#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x1811520#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff11521#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x011522#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff0011523#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x811524#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff000011525#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x1011526#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff00000011527#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x1811528#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff11529#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x011530#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff0011531#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x811532#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff000011533#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x1011534#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff00000011535#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x1811536#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff11537#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x011538#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff0011539#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x811540#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff000011541#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x1011542#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff00000011543#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x1811544#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff11545#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x011546#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff0011547#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x811548#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff000011549#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x1011550#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff00000011551#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x1811552#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff11553#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x011554#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff0011555#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x811556#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff000011557#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x1011558#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff00000011559#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x1811560#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff11561#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x011562#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff0011563#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x811564#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff000011565#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x1011566#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff00000011567#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x1811568#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff11569#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x011570#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff0011571#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x811572#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff000011573#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x1011574#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff00000011575#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x1811576#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff11577#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x011578#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff0011579#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x811580#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff000011581#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x1011582#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff00000011583#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x1811584#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff11585#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x011586#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff0011587#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x811588#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff000011589#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x1011590#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff00000011591#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x1811592#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff11593#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x011594#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff0011595#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x811596#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff000011597#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x1011598#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff00000011599#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x1811600#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff11601#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x011602#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff0011603#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x811604#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff000011605#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x1011606#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff00000011607#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x1811608#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff11609#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x011610#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff0011611#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x811612#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff000011613#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x1011614#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff00000011615#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x1811616#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff11617#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x011618#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff0011619#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x811620#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff000011621#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x1011622#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff00000011623#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x1811624#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff11625#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x011626#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff0011627#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x811628#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff000011629#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x1011630#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff00000011631#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x1811632#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff11633#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x011634#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff0011635#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x811636#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff000011637#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x1011638#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff00000011639#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x1811640#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff11641#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x011642#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff0011643#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x811644#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff000011645#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x1011646#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff00000011647#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x1811648#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff11649#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x011650#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff0011651#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x811652#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff000011653#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x1011654#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff00000011655#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x1811656#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff11657#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x011658#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff0011659#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x811660#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff000011661#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x1011662#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff00000011663#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x1811664#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff11665#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x011666#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff0011667#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x811668#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff000011669#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x1011670#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff00000011671#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x1811672#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff11673#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x011674#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff0011675#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x811676#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff000011677#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x1011678#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff00000011679#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x1811680#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff11681#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x011682#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff0011683#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x811684#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff000011685#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x1011686#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff00000011687#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x1811688#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff11689#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x011690#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff0011691#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x811692#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff000011693#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x1011694#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff00000011695#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x1811696#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff11697#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x011698#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff0011699#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x811700#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff000011701#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x1011702#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff00000011703#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x1811704#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff11705#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x011706#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff0011707#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x811708#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff000011709#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x1011710#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff00000011711#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x1811712#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff11713#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x011714#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff0011715#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x811716#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff000011717#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x1011718#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff00000011719#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x1811720#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff11721#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x011722#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff0011723#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x811724#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff000011725#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x1011726#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff00000011727#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x1811728#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff11729#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x011730#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff0011731#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x811732#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff000011733#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x1011734#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff00000011735#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x1811736#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff11737#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x011738#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff0011739#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x811740#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff000011741#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x1011742#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff00000011743#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x1811744#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff11745#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x011746#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff0011747#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x811748#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff000011749#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x1011750#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff00000011751#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x1811752#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff11753#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x011754#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff0011755#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x811756#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff000011757#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x1011758#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff00000011759#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x1811760#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff11761#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x011762#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff0011763#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x811764#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff000011765#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x1011766#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff00000011767#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x1811768#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff11769#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x011770#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff0011771#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x811772#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff000011773#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x1011774#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff00000011775#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x1811776#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff11777#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x011778#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff0011779#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x811780#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff000011781#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x1011782#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff00000011783#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x1811784#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff11785#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x011786#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff0011787#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x811788#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff000011789#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x1011790#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff00000011791#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x1811792#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff11793#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x011794#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff0011795#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x811796#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff000011797#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x1011798#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff00000011799#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x1811800#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff11801#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x011802#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff0011803#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x811804#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff000011805#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x1011806#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff00000011807#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x1811808#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff11809#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x011810#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff0011811#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x811812#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff000011813#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x1011814#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff00000011815#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x1811816#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff11817#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x011818#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff0011819#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x811820#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff000011821#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x1011822#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff00000011823#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x1811824#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff11825#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x011826#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff0011827#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x811828#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff000011829#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x1011830#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff00000011831#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x1811832#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff11833#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x011834#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff0011835#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x811836#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff000011837#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x1011838#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff00000011839#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x1811840#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff11841#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x011842#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff0011843#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x811844#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff000011845#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x1011846#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff00000011847#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x1811848#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff11849#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x011850#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff0011851#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x811852#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff000011853#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x1011854#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff00000011855#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x1811856#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff11857#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x011858#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff0011859#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x811860#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff000011861#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x1011862#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff00000011863#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x1811864#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff11865#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x011866#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff0011867#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x811868#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff000011869#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x1011870#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff00000011871#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x1811872#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff11873#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x011874#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff0011875#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x811876#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff000011877#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x1011878#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff00000011879#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x1811880#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff11881#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x011882#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff0011883#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x811884#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff000011885#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x1011886#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff00000011887#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x1811888#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff11889#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x011890#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff0011891#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x811892#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff000011893#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x1011894#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff00000011895#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x1811896#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff11897#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x011898#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff0011899#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x811900#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff000011901#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x1011902#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff00000011903#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x1811904#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff11905#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x011906#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff0011907#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x811908#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff000011909#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x1011910#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff00000011911#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x1811912#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff11913#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x011914#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff0011915#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x811916#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff000011917#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x1011918#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff00000011919#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x1811920#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff11921#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x011922#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff0011923#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x811924#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff000011925#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x1011926#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff00000011927#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x1811928#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff11929#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x011930#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff0011931#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x811932#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff000011933#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x1011934#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff00000011935#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x1811936#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff11937#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x011938#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff0011939#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x811940#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff000011941#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x1011942#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff00000011943#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x1811944#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff11945#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x011946#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff0011947#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x811948#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff000011949#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x1011950#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff00000011951#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x1811952#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff11953#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x011954#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff0011955#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x811956#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff000011957#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x1011958#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff00000011959#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x1811960#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff11961#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x011962#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff0011963#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x811964#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff000011965#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x1011966#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff00000011967#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x1811968#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff11969#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x011970#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff0011971#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x811972#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff000011973#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x1011974#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff00000011975#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x1811976#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff11977#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x011978#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff0011979#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x811980#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff000011981#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x1011982#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff00000011983#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x1811984#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff11985#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x011986#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff0011987#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x811988#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff000011989#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x1011990#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff00000011991#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x1811992#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff11993#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x011994#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff0011995#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x811996#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff000011997#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x1011998#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff00000011999#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x1812000#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff12001#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x012002#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff0012003#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x812004#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff000012005#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x1012006#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff00000012007#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x1812008#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff12009#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x012010#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff0012011#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x812012#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff000012013#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x1012014#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff00000012015#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x1812016#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff12017#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x012018#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff0012019#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x812020#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff000012021#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x1012022#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff00000012023#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x1812024#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff12025#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x012026#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff0012027#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x812028#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff000012029#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x1012030#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff00000012031#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x1812032#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff12033#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x012034#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff0012035#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x812036#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff000012037#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x1012038#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff00000012039#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x1812040#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff12041#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x012042#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff0012043#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x812044#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff000012045#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x1012046#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff00000012047#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x1812048#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff12049#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x012050#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff0012051#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x812052#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff000012053#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x1012054#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff00000012055#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x1812056#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff12057#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x012058#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff0012059#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x812060#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff000012061#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x1012062#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff00000012063#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x1812064#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff12065#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x012066#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff0012067#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x812068#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff000012069#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x1012070#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff00000012071#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x1812072#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff12073#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x012074#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff0012075#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x812076#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff000012077#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x1012078#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff00000012079#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x1812080#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff12081#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x012082#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff0012083#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x812084#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff000012085#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x1012086#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff00000012087#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x1812088#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff12089#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x012090#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff0012091#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x812092#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff000012093#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x1012094#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff00000012095#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x1812096#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff12097#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x012098#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff0012099#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x812100#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff000012101#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x1012102#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff00000012103#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x1812104#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff12105#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x012106#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff0012107#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x812108#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff000012109#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x1012110#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff00000012111#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x1812112#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff12113#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x012114#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff0012115#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x812116#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff000012117#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x1012118#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff00000012119#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x1812120#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff12121#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x012122#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff0012123#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x812124#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff000012125#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x1012126#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff00000012127#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x1812128#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff12129#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x012130#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff0012131#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x812132#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff000012133#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x1012134#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff00000012135#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x1812136#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff12137#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x012138#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff0012139#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x812140#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff000012141#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x1012142#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff00000012143#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x1812144#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff12145#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x012146#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff0012147#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x812148#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff000012149#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x1012150#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff00000012151#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x1812152#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff12153#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x012154#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff0012155#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x812156#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff000012157#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x1012158#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff00000012159#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x1812160#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff12161#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x012162#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff0012163#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x812164#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff000012165#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x1012166#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff00000012167#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x1812168#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff12169#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x012170#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff0012171#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x812172#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff000012173#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x1012174#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff00000012175#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x1812176#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff12177#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x012178#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff0012179#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x812180#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff000012181#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x1012182#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff00000012183#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x1812184#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff12185#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x012186#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff0012187#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x812188#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff000012189#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x1012190#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff00000012191#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x1812192#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff12193#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x012194#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff0012195#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x812196#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff000012197#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x1012198#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff00000012199#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x1812200#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff12201#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x012202#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff0012203#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x812204#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff000012205#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x1012206#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff00000012207#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x1812208#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff12209#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x012210#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff0012211#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x812212#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff000012213#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x1012214#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff00000012215#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x1812216#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff12217#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x012218#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff0012219#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x812220#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff000012221#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x1012222#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff00000012223#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x1812224#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff12225#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x012226#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff0012227#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x812228#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff000012229#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x1012230#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff00000012231#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x1812232#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff12233#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x012234#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff0012235#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x812236#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff000012237#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x1012238#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff00000012239#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x1812240#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff12241#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x012242#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff0012243#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x812244#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff000012245#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x1012246#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff00000012247#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x1812248#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff12249#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x012250#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff0012251#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x812252#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff000012253#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x1012254#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff00000012255#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x1812256#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff12257#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x012258#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff0012259#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x812260#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff000012261#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x1012262#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff00000012263#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x1812264#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff12265#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x012266#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff0012267#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x812268#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff000012269#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x1012270#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff00000012271#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x1812272#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff12273#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x012274#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff0012275#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x812276#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff000012277#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x1012278#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff00000012279#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x1812280#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff12281#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x012282#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff0012283#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x812284#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff000012285#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x1012286#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff00000012287#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x1812288#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff12289#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x012290#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff0012291#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x812292#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff000012293#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x1012294#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff00000012295#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x1812296#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff12297#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x012298#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff0012299#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x812300#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff000012301#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x1012302#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff00000012303#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x1812304#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff12305#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x012306#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff0012307#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x812308#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff000012309#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x1012310#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff00000012311#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x1812312#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff12313#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x012314#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff0012315#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x812316#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff000012317#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x1012318#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff00000012319#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x1812320#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff12321#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x012322#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff0012323#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x812324#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff000012325#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x1012326#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff00000012327#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x1812328#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff12329#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x012330#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff0012331#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x812332#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff000012333#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x1012334#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff00000012335#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x1812336#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff12337#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x012338#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff0012339#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x812340#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff000012341#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x1012342#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff00000012343#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x1812344#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff12345#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x012346#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff0012347#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x812348#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff000012349#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x1012350#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff00000012351#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x1812352#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff12353#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x012354#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff0012355#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x812356#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff000012357#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x1012358#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff00000012359#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x1812360#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff12361#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x012362#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff0012363#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x812364#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff000012365#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x1012366#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff00000012367#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x1812368#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff12369#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x012370#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff0012371#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x812372#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff000012373#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x1012374#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff00000012375#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x1812376#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff12377#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x012378#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff0012379#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x812380#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff000012381#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x1012382#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff00000012383#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x1812384#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff12385#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x012386#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff0012387#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x812388#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff000012389#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x1012390#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff00000012391#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x1812392#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff12393#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x012394#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff0012395#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x812396#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff000012397#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x1012398#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff00000012399#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x1812400#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff12401#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x012402#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff0012403#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x812404#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff000012405#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x1012406#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff00000012407#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x1812408#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff12409#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x012410#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff0012411#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x812412#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff000012413#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x1012414#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff00000012415#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x1812416#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff12417#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012418#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012419#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812420#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012421#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012422#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012423#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812424#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff12425#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012426#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012427#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812428#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012429#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012430#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012431#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812432#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff12433#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012434#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012435#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812436#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012437#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012438#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012439#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812440#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff12441#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012442#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012443#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812444#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012445#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012446#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012447#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812448#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff12449#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012450#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012451#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812452#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012453#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012454#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012455#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812456#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff12457#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012458#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012459#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812460#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012461#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012462#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012463#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812464#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff12465#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012466#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012467#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812468#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012469#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012470#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012471#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812472#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff12473#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012474#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012475#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812476#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012477#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012478#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012479#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812480#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff12481#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012482#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012483#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812484#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012485#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012486#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012487#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812488#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff12489#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012490#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012491#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812492#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012493#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012494#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012495#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812496#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff12497#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x012498#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff0012499#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x812500#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff000012501#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1012502#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000012503#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1812504#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff12505#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x012506#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff0012507#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x812508#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff000012509#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x1012510#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff00000012511#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x1812512#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff12513#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x012514#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff0012515#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x812516#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff000012517#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x1012518#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff00000012519#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x1812520#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff12521#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x012522#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff0012523#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x812524#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff000012525#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x1012526#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff00000012527#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x1812528#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff12529#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x012530#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff0012531#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x812532#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff000012533#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x1012534#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff00000012535#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x1812536#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff12537#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x012538#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff0012539#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x812540#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff000012541#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x1012542#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff00000012543#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x1812544#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff12545#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012546#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012547#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812548#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012549#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012550#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012551#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812552#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff12553#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012554#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012555#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812556#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012557#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012558#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012559#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812560#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff12561#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012562#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012563#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812564#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012565#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012566#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012567#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812568#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff12569#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012570#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012571#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812572#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012573#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012574#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012575#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812576#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff12577#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012578#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012579#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812580#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012581#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012582#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012583#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812584#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff12585#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012586#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012587#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812588#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012589#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012590#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012591#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812592#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff12593#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012594#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012595#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812596#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012597#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012598#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012599#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812600#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff12601#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012602#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012603#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812604#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012605#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012606#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012607#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812608#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff12609#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012610#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012611#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812612#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012613#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012614#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012615#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812616#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff12617#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012618#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012619#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812620#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012621#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012622#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012623#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812624#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff12625#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x012626#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff0012627#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x812628#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff000012629#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1012630#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000012631#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1812632#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff12633#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x012634#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff0012635#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x812636#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff000012637#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x1012638#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff00000012639#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x1812640#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff12641#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x012642#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff0012643#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x812644#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff000012645#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x1012646#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff00000012647#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x1812648#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff12649#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x012650#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff0012651#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x812652#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff000012653#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x1012654#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff00000012655#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x1812656#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff12657#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x012658#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff0012659#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x812660#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff000012661#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x1012662#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff00000012663#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x1812664#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff12665#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x012666#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff0012667#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x812668#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff000012669#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x1012670#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff00000012671#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x1812672#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff12673#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x012674#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff0012675#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x812676#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff000012677#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x1012678#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff00000012679#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x1812680#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff12681#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x012682#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff0012683#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x812684#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff000012685#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x1012686#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff00000012687#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x1812688#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff12689#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x012690#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff0012691#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x812692#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff000012693#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x1012694#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff00000012695#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x1812696#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff12697#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x012698#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff0012699#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x812700#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff000012701#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x1012702#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff00000012703#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x1812704#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff12705#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x012706#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff0012707#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x812708#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff000012709#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x1012710#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff00000012711#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x1812712#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff12713#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x012714#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff0012715#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x812716#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff000012717#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x1012718#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff00000012719#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x1812720#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff12721#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x012722#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff0012723#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x812724#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff000012725#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x1012726#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff00000012727#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x1812728#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff12729#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x012730#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff0012731#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x812732#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff000012733#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x1012734#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff00000012735#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x1812736#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff12737#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x012738#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff0012739#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x812740#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff000012741#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x1012742#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff00000012743#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x1812744#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff12745#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x012746#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff0012747#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x812748#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff000012749#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x1012750#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff00000012751#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x1812752#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff12753#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x012754#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff0012755#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x812756#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff000012757#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x1012758#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff00000012759#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x1812760#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff12761#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x012762#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff0012763#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x812764#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff000012765#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x1012766#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff00000012767#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x1812768#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff12769#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x012770#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff0012771#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x812772#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff000012773#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x1012774#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff00000012775#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x1812776#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff12777#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x012778#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff0012779#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x812780#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff000012781#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x1012782#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff00000012783#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x1812784#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff12785#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x012786#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff0012787#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x812788#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff000012789#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x1012790#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff00000012791#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x1812792#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff12793#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x012794#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff0012795#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x812796#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff000012797#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x1012798#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff00000012799#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x1812800#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff12801#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x012802#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff0012803#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x812804#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff000012805#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x1012806#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff00000012807#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x1812808#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff12809#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x012810#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff0012811#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x812812#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff000012813#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x1012814#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff00000012815#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x1812816#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff12817#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x012818#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff0012819#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x812820#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff000012821#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x1012822#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff00000012823#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x1812824#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff12825#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x012826#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff0012827#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x812828#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff000012829#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x1012830#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff00000012831#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x1812832#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff12833#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x012834#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff0012835#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x812836#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff000012837#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x1012838#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff00000012839#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x1812840#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff12841#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x012842#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff0012843#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x812844#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff000012845#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x1012846#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff00000012847#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x1812848#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff12849#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x012850#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff0012851#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x812852#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff000012853#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x1012854#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff00000012855#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x1812856#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff12857#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x012858#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff0012859#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x812860#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff000012861#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x1012862#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff00000012863#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x1812864#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff12865#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x012866#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff0012867#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x812868#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff000012869#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x1012870#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff00000012871#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x1812872#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff12873#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x012874#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff0012875#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x812876#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff000012877#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x1012878#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff00000012879#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x1812880#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff12881#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x012882#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff0012883#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x812884#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff000012885#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x1012886#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff00000012887#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x1812888#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff12889#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x012890#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff0012891#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x812892#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff000012893#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x1012894#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff00000012895#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x1812896#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff12897#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x012898#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff0012899#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x812900#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff000012901#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x1012902#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff00000012903#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x1812904#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff12905#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x012906#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff0012907#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x812908#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff000012909#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x1012910#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff00000012911#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x1812912#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff12913#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x012914#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff0012915#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x812916#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff000012917#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x1012918#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff00000012919#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x1812920#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff12921#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x012922#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff0012923#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x812924#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff000012925#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x1012926#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff00000012927#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x1812928#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff12929#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x012930#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff0012931#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x812932#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff000012933#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x1012934#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff00000012935#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x1812936#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff12937#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x012938#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff0012939#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x812940#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff000012941#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x1012942#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff00000012943#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x1812944#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff12945#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x012946#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff0012947#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x812948#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff000012949#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x1012950#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff00000012951#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x1812952#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff12953#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x012954#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff0012955#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x812956#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff000012957#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x1012958#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff00000012959#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x1812960#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff12961#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x012962#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff0012963#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x812964#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff000012965#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x1012966#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff00000012967#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x1812968#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff12969#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x012970#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff0012971#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x812972#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff000012973#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x1012974#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff00000012975#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x1812976#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff12977#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x012978#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff0012979#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x812980#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff000012981#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x1012982#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff00000012983#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x1812984#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff12985#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x012986#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff0012987#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x812988#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff000012989#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x1012990#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff00000012991#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x1812992#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff12993#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x012994#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff0012995#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x812996#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff000012997#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x1012998#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff00000012999#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x1813000#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff13001#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x013002#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff0013003#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x813004#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff000013005#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x1013006#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff00000013007#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x1813008#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff13009#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x013010#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff0013011#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x813012#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff000013013#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x1013014#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff00000013015#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x1813016#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff13017#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x013018#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff0013019#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x813020#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff000013021#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x1013022#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff00000013023#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x1813024#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff13025#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x013026#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff0013027#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x813028#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff000013029#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x1013030#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff00000013031#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x1813032#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff13033#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x013034#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff0013035#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x813036#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff000013037#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x1013038#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff00000013039#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x1813040#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff13041#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x013042#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff0013043#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x813044#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff000013045#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x1013046#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff00000013047#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x1813048#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff13049#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x013050#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff0013051#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x813052#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff000013053#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x1013054#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff00000013055#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x1813056#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff13057#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x013058#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff0013059#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x813060#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff000013061#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x1013062#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff00000013063#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x1813064#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff13065#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x013066#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff0013067#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x813068#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff000013069#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x1013070#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff00000013071#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x1813072#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff13073#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x013074#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff0013075#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x813076#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff000013077#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x1013078#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff00000013079#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x1813080#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff13081#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x013082#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff0013083#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x813084#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff000013085#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x1013086#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff00000013087#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x1813088#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff13089#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x013090#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff0013091#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x813092#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff000013093#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x1013094#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff00000013095#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x1813096#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff13097#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x013098#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff0013099#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x813100#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff000013101#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x1013102#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff00000013103#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x1813104#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff13105#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x013106#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff0013107#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x813108#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff000013109#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x1013110#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff00000013111#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x1813112#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff13113#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x013114#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff0013115#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x813116#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff000013117#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x1013118#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff00000013119#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x1813120#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff13121#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x013122#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff0013123#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x813124#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff000013125#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x1013126#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff00000013127#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x1813128#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff13129#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x013130#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff0013131#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x813132#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff000013133#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x1013134#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff00000013135#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x1813136#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff13137#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x013138#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff0013139#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x813140#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff000013141#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x1013142#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff00000013143#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x1813144#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff13145#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x013146#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff0013147#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x813148#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff000013149#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x1013150#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff00000013151#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x1813152#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff13153#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x013154#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff0013155#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x813156#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff000013157#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x1013158#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff00000013159#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x1813160#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff13161#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x013162#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff0013163#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x813164#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff000013165#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x1013166#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff00000013167#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x1813168#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff13169#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x013170#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff0013171#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x813172#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff000013173#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x1013174#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff00000013175#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x1813176#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff13177#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x013178#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff0013179#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x813180#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff000013181#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x1013182#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff00000013183#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x1813184#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff13185#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x013186#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff0013187#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x813188#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff000013189#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x1013190#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff00000013191#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x1813192#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff13193#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x013194#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff0013195#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x813196#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff000013197#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x1013198#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff00000013199#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x1813200#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff13201#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x013202#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff0013203#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x813204#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff000013205#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x1013206#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff00000013207#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x1813208#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff13209#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x013210#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff0013211#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x813212#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff000013213#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x1013214#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff00000013215#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x1813216#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff13217#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x013218#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff0013219#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x813220#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff000013221#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x1013222#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff00000013223#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x1813224#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff13225#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x013226#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff0013227#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x813228#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff000013229#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x1013230#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff00000013231#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x1813232#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff13233#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x013234#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff0013235#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x813236#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff000013237#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x1013238#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff00000013239#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x1813240#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff13241#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x013242#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff0013243#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x813244#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff000013245#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x1013246#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff00000013247#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x1813248#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff13249#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x013250#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff0013251#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x813252#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff000013253#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x1013254#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff00000013255#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x1813256#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff13257#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x013258#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff0013259#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x813260#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff000013261#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x1013262#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff00000013263#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x1813264#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff13265#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x013266#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff0013267#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x813268#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff000013269#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x1013270#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff00000013271#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x1813272#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff13273#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x013274#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff0013275#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x813276#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff000013277#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x1013278#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff00000013279#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x1813280#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff13281#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x013282#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff0013283#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x813284#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff000013285#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x1013286#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff00000013287#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x1813288#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff13289#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x013290#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff0013291#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x813292#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff000013293#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x1013294#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff00000013295#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x1813296#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff13297#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x013298#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff0013299#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x813300#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff000013301#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x1013302#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff00000013303#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x1813304#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff13305#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x013306#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff0013307#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x813308#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff000013309#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x1013310#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff00000013311#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x1813312#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff13313#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x013314#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff0013315#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x813316#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff000013317#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x1013318#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff00000013319#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x1813320#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff13321#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x013322#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff0013323#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x813324#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff000013325#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x1013326#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff00000013327#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x1813328#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff13329#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x013330#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff0013331#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x813332#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff000013333#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x1013334#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff00000013335#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x1813336#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff13337#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x013338#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff0013339#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x813340#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff000013341#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x1013342#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff00000013343#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x1813344#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff13345#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x013346#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff0013347#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x813348#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff000013349#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x1013350#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff00000013351#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x1813352#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff13353#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x013354#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff0013355#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x813356#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff000013357#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x1013358#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff00000013359#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x1813360#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff13361#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x013362#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff0013363#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x813364#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff000013365#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x1013366#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff00000013367#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x1813368#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff13369#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x013370#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff0013371#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x813372#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff000013373#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x1013374#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff00000013375#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x1813376#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff13377#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x013378#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff0013379#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x813380#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff000013381#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x1013382#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff00000013383#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x1813384#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff13385#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x013386#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff0013387#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x813388#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff000013389#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x1013390#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff00000013391#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x1813392#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff13393#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x013394#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff0013395#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x813396#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff000013397#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x1013398#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff00000013399#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x1813400#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff13401#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x013402#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff0013403#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x813404#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff000013405#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x1013406#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff00000013407#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x1813408#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff13409#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x013410#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff0013411#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x813412#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff000013413#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x1013414#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff00000013415#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x1813416#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff13417#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x013418#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff0013419#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x813420#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff000013421#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x1013422#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff00000013423#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x1813424#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff13425#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x013426#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff0013427#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x813428#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff000013429#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x1013430#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff00000013431#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x1813432#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff13433#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x013434#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff0013435#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x813436#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff000013437#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x1013438#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff00000013439#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x1813440#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff13441#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x013442#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff0013443#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x813444#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff000013445#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x1013446#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff00000013447#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x1813448#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff13449#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x013450#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff0013451#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x813452#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff000013453#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x1013454#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff00000013455#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x1813456#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff13457#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x013458#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff0013459#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x813460#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff000013461#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x1013462#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff00000013463#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x1813464#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff13465#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x013466#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff0013467#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x813468#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff000013469#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x1013470#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff00000013471#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x1813472#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff13473#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x013474#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff0013475#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x813476#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff000013477#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x1013478#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff00000013479#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x1813480#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff13481#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x013482#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff0013483#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x813484#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff000013485#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x1013486#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff00000013487#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x1813488#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff13489#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x013490#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff0013491#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x813492#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff000013493#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x1013494#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff00000013495#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x1813496#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff13497#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x013498#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff0013499#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x813500#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff000013501#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x1013502#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff00000013503#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x1813504#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff13505#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x013506#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff0013507#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x813508#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff000013509#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x1013510#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff00000013511#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x1813512#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff13513#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x013514#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff0013515#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x813516#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff000013517#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x1013518#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff00000013519#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x1813520#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff13521#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x013522#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff0013523#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x813524#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff000013525#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x1013526#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff00000013527#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x1813528#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff13529#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x013530#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff0013531#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x813532#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff000013533#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x1013534#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff00000013535#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x1813536#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff13537#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x013538#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff0013539#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x813540#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff000013541#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x1013542#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff00000013543#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x1813544#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff13545#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x013546#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff0013547#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x813548#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff000013549#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x1013550#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff00000013551#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x1813552#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff13553#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x013554#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff0013555#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x813556#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff000013557#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x1013558#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff00000013559#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x1813560#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff13561#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x013562#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff0013563#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x813564#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff000013565#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x1013566#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff00000013567#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x1813568#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff13569#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x013570#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff0013571#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x813572#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff000013573#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x1013574#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff00000013575#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x1813576#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff13577#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x013578#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff0013579#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x813580#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff000013581#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x1013582#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff00000013583#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x1813584#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff13585#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x013586#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff0013587#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x813588#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff000013589#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x1013590#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff00000013591#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x1813592#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff13593#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x013594#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff0013595#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x813596#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff000013597#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x1013598#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff00000013599#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x1813600#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff13601#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x013602#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff0013603#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x813604#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff000013605#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x1013606#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff00000013607#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x1813608#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff13609#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x013610#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff0013611#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x813612#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff000013613#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x1013614#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff00000013615#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x1813616#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff13617#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x013618#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff0013619#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x813620#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff000013621#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x1013622#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff00000013623#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x1813624#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff13625#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x013626#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff0013627#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x813628#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff000013629#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x1013630#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff00000013631#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x1813632#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff13633#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x013634#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff0013635#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x813636#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff000013637#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x1013638#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff00000013639#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x1813640#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff13641#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x013642#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff0013643#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x813644#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff000013645#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x1013646#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff00000013647#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x1813648#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff13649#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x013650#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff0013651#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x813652#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff000013653#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x1013654#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff00000013655#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x1813656#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff13657#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x013658#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff0013659#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x813660#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff000013661#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x1013662#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff00000013663#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x1813664#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff13665#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x013666#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff0013667#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x813668#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff000013669#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x1013670#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff00000013671#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x1813672#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff13673#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x013674#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff0013675#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x813676#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff000013677#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x1013678#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff00000013679#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x1813680#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff13681#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x013682#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff0013683#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x813684#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff000013685#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x1013686#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff00000013687#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x1813688#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff13689#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x013690#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff0013691#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x813692#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff000013693#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x1013694#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff00000013695#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x1813696#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff13697#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x013698#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff0013699#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x813700#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff000013701#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x1013702#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff00000013703#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x1813704#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff13705#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x013706#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff0013707#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x813708#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff000013709#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x1013710#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff00000013711#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x1813712#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff13713#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x013714#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff0013715#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x813716#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff000013717#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x1013718#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff00000013719#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x1813720#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff13721#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x013722#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff0013723#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x813724#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff000013725#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x1013726#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff00000013727#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x1813728#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff13729#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x013730#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff0013731#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x813732#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff000013733#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x1013734#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff00000013735#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x1813736#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff13737#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x013738#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff0013739#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x813740#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff000013741#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x1013742#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff00000013743#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x1813744#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff13745#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x013746#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff0013747#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x813748#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff000013749#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x1013750#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff00000013751#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x1813752#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff13753#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x013754#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff0013755#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x813756#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff000013757#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x1013758#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff00000013759#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x1813760#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff13761#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x013762#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff0013763#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x813764#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff000013765#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x1013766#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff00000013767#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x1813768#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff13769#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x013770#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff0013771#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x813772#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff000013773#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x1013774#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff00000013775#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x1813776#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff13777#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x013778#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff0013779#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x813780#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff000013781#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x1013782#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff00000013783#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x1813784#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff13785#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x013786#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff0013787#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x813788#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff000013789#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x1013790#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff00000013791#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x1813792#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff13793#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x013794#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff0013795#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x813796#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff000013797#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x1013798#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff00000013799#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x1813800#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff13801#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x013802#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff0013803#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x813804#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff000013805#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x1013806#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff00000013807#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x1813808#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff13809#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x013810#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff0013811#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x813812#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff000013813#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x1013814#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff00000013815#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x1813816#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff13817#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x013818#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff0013819#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x813820#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff000013821#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x1013822#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff00000013823#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x1813824#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff13825#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x013826#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff0013827#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x813828#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff000013829#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x1013830#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff00000013831#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x1813832#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff13833#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x013834#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff0013835#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x813836#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff000013837#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x1013838#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff00000013839#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x1813840#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff13841#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x013842#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff0013843#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x813844#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff000013845#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x1013846#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff00000013847#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x1813848#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff13849#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x013850#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff0013851#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x813852#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff000013853#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x1013854#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff00000013855#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x1813856#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff13857#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x013858#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff0013859#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x813860#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff000013861#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x1013862#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff00000013863#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x1813864#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff13865#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x013866#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff0013867#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x813868#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff000013869#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x1013870#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff00000013871#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x1813872#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff13873#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x013874#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff0013875#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x813876#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff000013877#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x1013878#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff00000013879#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x1813880#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff13881#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x013882#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff0013883#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x813884#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff000013885#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x1013886#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff00000013887#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x1813888#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff13889#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x013890#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff0013891#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x813892#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff000013893#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x1013894#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff00000013895#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x1813896#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff13897#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x013898#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff0013899#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x813900#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff000013901#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x1013902#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff00000013903#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x1813904#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x713905#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x013906#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x3813907#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x313908#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c013909#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x613910#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe0013911#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x913912#define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x100013913#define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc13914#define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x200013915#define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd13916#define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf000013917#define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x1013918#define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x10000013919#define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x1413920#define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x20000013921#define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x1513922#define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x40000013923#define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x1613924#define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x80000013925#define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x1713926#define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf00000013927#define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x1813928#define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x4000000013929#define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e13930#define MC_SEQ_CNTL_3__CAC_EN_MASK 0x8000000013931#define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f13932#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x113933#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x013934#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x213935#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x113936#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x413937#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x213938#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x813939#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x313940#define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f013941#define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x413942#define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf00013943#define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc13944#define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf000013945#define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x1013946#define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf0000013947#define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x1413948#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x113949#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x013950#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x213951#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x113952#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x413953#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x213954#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x813955#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x313956#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f013957#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x413958#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf00013959#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc13960#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf000013961#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x1013962#define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf0000013963#define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x1413964#define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff13965#define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x013966#define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff13967#define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x013968#define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff13969#define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x013970#define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff13971#define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x013972#define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff13973#define MC_SEQ_SREG_READ__DATA__SHIFT 0x013974#define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf13975#define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x013976#define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf0013977#define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x813978#define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf00013979#define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc13980#define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x113981#define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x013982#define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x213983#define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x113984#define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x8013985#define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x713986#define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x10013987#define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x813988#define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x20013989#define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x913990#define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x40013991#define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa13992#define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x80013993#define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb13994#define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x100013995#define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc13996#define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x200013997#define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd13998#define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x400013999#define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe14000#define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x800014001#define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf14002#define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x114003#define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x014004#define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e14005#define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x114006#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x114007#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x014008#define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e14009#define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x114010#define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff14011#define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x014012#define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x7000014013#define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x1014014#define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x8000014015#define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x1314016#define MC_SEQ_PMG_DVS_CMD__END_MASK 0x10000014017#define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x1414018#define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x60000014019#define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x1514020#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x80000014021#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x1714022#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x100000014023#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x1814024#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff14025#define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x014026#define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x7000014027#define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x1014028#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x8000014029#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x1314030#define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x10000014031#define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x1414032#define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x60000014033#define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x1514034#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x80000014035#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x1714036#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x100000014037#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x1814038#define MC_SEQ_DLL_STBY__EN_MASK 0x114039#define MC_SEQ_DLL_STBY__EN__SHIFT 0x014040#define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x214041#define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x114042#define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x414043#define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x214044#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x814045#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x314046#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x1014047#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x414048#define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe014049#define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x514050#define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf0014051#define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x814052#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf00014053#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc14054#define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff000014055#define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x1014056#define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f00000014057#define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x1814058#define MC_SEQ_DLL_STBY_LP__EN_MASK 0x114059#define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x014060#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x214061#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x114062#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x414063#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x214064#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x814065#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x314066#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x1014067#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x414068#define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe014069#define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x514070#define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf0014071#define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x814072#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf00014073#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc14074#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff000014075#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x1014076#define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f00000014077#define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x1814078#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x114079#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x014080#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x214081#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x114082#define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x414083#define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x214084#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x814085#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x314086#define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf014087#define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x414088#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f0014089#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x814090#define MC_DLB_MISCCTRL0__UDD_MASK 0xffff000014091#define MC_DLB_MISCCTRL0__UDD__SHIFT 0x1014092#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff14093#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x014094#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff14095#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x014096#define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x2000014097#define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x1114098#define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x4000014099#define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x1214100#define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x8000014101#define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x1314102#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x10000014103#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x1414104#define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x20000014105#define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x1514106#define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x300000014107#define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x1814108#define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x400000014109#define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a14110#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x1000000014111#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c14112#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x2000000014113#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d14114#define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x4000000014115#define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e14116#define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x114117#define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x014118#define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x214119#define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x114120#define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x414121#define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x214122#define MC_DLB_CONFIG0__MASK_MASK 0xf014123#define MC_DLB_CONFIG0__MASK__SHIFT 0x414124#define MC_DLB_CONFIG0__PTR_MASK 0x3ff0014125#define MC_DLB_CONFIG0__PTR__SHIFT 0x814126#define MC_DLB_CONFIG1__DATA_MASK 0xffffffff14127#define MC_DLB_CONFIG1__DATA__SHIFT 0x014128#define MC_DLB_SETUP__DLB_EN_MASK 0x114129#define MC_DLB_SETUP__DLB_EN__SHIFT 0x014130#define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x214131#define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x114132#define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x414133#define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x214134#define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x814135#define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x314136#define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x1014137#define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x414138#define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x2014139#define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x514140#define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x4014141#define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x614142#define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x8014143#define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x714144#define MC_DLB_SETUP__QDR_MODE_MASK 0x10014145#define MC_DLB_SETUP__QDR_MODE__SHIFT 0x814146#define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff000014147#define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x1014148#define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f00000014149#define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x1814150#define MC_DLB_SETUP__RXTXLP_EN_MASK 0x8000000014151#define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f14152#define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x114153#define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x014154#define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x214155#define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x114156#define MC_DLB_SETUPSWEEP__MASTER_MASK 0x414157#define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x214158#define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf014159#define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x414160#define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f0014161#define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x814162#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x114163#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x014164#define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x214165#define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x114166#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x414167#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x214168#define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x814169#define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x314170#define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x3014171#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x414172#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x4014173#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x614174#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x30014175#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x814176#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c0014177#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa14178#define MC_DLB_SETUPFIFO__STROBE_MASK 0xf000014179#define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x1014180#define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff14181#define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x014182#define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf00000014183#define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x1814184#define MC_DLB_STATUS__STICK_ERROR_MASK 0xf14185#define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x014186#define MC_DLB_STATUS__LOCK_MASK 0xf014187#define MC_DLB_STATUS__LOCK__SHIFT 0x414188#define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf0014189#define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x814190#define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff14191#define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x014192#define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff14193#define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x014194#define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff14195#define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x014196#define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff14197#define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x014198#define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff14199#define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x014200#define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff14201#define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x014202#define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff14203#define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x014204#define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff14205#define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x014206#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff14207#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x014208#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff0014209#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x814210#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff000014211#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x1014212#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff00000014213#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x1814214#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff14215#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x014216#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff0014217#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x814218#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff000014219#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x1014220#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff00000014221#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x1814222#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff14223#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x014224#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff0014225#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x814226#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff000014227#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x1014228#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff00000014229#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x1814230#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff14231#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x014232#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff0014233#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x814234#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff000014235#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x1014236#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff00000014237#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x1814238#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff14239#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x014240#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff0014241#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x814242#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff000014243#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x1014244#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff00000014245#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x1814246#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff14247#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x014248#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff0014249#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x814250#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff000014251#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x1014252#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff00000014253#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x1814254#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff14255#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x014256#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff0014257#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x814258#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff000014259#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x1014260#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff00000014261#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x1814262#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff14263#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x014264#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff0014265#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x814266#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff000014267#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x1014268#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff00000014269#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x1814270#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff14271#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x014272#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff0014273#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x814274#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff000014275#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x1014276#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff00000014277#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x1814278#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff14279#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x014280#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff0014281#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x814282#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff000014283#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x1014284#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff00000014285#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x1814286#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff14287#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x014288#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff0014289#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x814290#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff000014291#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x1014292#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff00000014293#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x1814294#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff14295#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x014296#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff0014297#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x814298#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff000014299#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x1014300#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff00000014301#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x1814302#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff14303#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x014304#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff0014305#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x814306#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff000014307#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x1014308#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff00000014309#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x1814310#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff14311#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x014312#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff0014313#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x814314#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff000014315#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x1014316#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff00000014317#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x1814318#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff14319#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x014320#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff0014321#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x814322#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff000014323#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x1014324#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff00000014325#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x1814326#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff14327#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x014328#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff0014329#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x814330#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff000014331#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x1014332#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff00000014333#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x1814334#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff14335#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x014336#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff0014337#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x814338#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff000014339#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x1014340#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff00000014341#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x1814342#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff14343#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x014344#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff0014345#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x814346#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff000014347#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x1014348#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff00000014349#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x1814350#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff14351#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x014352#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff0014353#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x814354#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff000014355#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x1014356#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff00000014357#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x1814358#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff14359#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x014360#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff0014361#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x814362#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff000014363#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x1014364#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff00000014365#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x1814366#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff14367#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x014368#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff0014369#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x814370#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff000014371#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x1014372#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff00000014373#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x1814374#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff14375#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x014376#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff0014377#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x814378#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff000014379#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x1014380#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff00000014381#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x1814382#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff14383#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x014384#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x10014385#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x814386#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x20014387#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x914388#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x40014389#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa14390#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x80014391#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb14392#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x300014393#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc14394#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc00014395#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe14396#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c0000014397#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x1614398#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff14399#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x014400#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x10014401#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x814402#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x20014403#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x914404#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x40014405#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa14406#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x80014407#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb14408#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x300014409#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc14410#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc00014411#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe14412#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c0000014413#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x161441414415#endif /* GMC_7_1_SH_MASK_H */144161441714418