/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */1/*2* cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header3*4* Copyright 2022 Cirrus Logic, Inc.5*/67#ifndef DT_CS35L45_H8#define DT_CS35L45_H910/*11* cirrus,asp-sdout-hiz-ctrl12*13* TX_HIZ_UNUSED: TX pin high-impedance during unused slots.14* TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.15*/16#define CS35L45_ASP_TX_HIZ_UNUSED 0x117#define CS35L45_ASP_TX_HIZ_DISABLED 0x21819/*20* Optional GPIOX Sub-nodes:21* The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])22* sub-nodes for configuring the GPIO pins.23*24* - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'25* is 1.26* 0 = Output27* 1 = Input (Default)28*29* - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.30*31* 0 = Low (Default)32* 1 = High33*34* - gpio-op-cfg : GPIO output configuration. Valid only when 'gpio-ctrl' is 135* and 'gpio-dir' is 0.36*37* 0 = CMOS (Default)38* 1 = Open Drain39*40* - gpio-pol : GPIO output polarity select. Valid only when 'gpio-ctrl' is 141* and 'gpio-dir' is 0.42*43* 0 = Non-inverted, Active High (Default)44* 1 = Inverted, Active Low45*46* - gpio-invert : Defines the polarity of the GPIO pin if configured47* as input.48*49* 0 = Not inverted (Default)50* 1 = Inverted51*52* - gpio-ctrl : Defines the function of the GPIO pin.53*54* GPIO1:55* 0 = High impedance input (Default)56* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'57* 2 = Pin acts as MDSYNC, direction controlled by MDSYNC58* 3-7 = Reserved59*60* GPIO2:61* 0 = High impedance input (Default)62* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'63* 2 = Pin acts as open drain INT64* 3 = Reserved65* 4 = Pin acts as push-pull output INT. Active low.66* 5 = Pin acts as push-pull output INT. Active high.67* 6,7 = Reserved68*69* GPIO3:70* 0 = High impedance input (Default)71* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'72* 2-7 = Reserved73*/74#define CS35L45_NUM_GPIOS 0x37576#endif /* DT_CS35L45_H */777879