CoCalc -- qcom,q6dsp-lpass-ports.h

GitHub Repository: torvalds/linux
Path: blob/master/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__
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#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__
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/* LPASS Audio virtual ports IDs */
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#define HDMI_RX		1
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#define SLIMBUS_0_RX    2
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#define SLIMBUS_0_TX    3
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#define SLIMBUS_1_RX    4
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#define SLIMBUS_1_TX    5
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#define SLIMBUS_2_RX    6
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#define SLIMBUS_2_TX    7
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#define SLIMBUS_3_RX    8
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#define SLIMBUS_3_TX    9
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#define SLIMBUS_4_RX    10
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#define SLIMBUS_4_TX    11
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#define SLIMBUS_5_RX    12
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#define SLIMBUS_5_TX    13
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#define SLIMBUS_6_RX    14
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#define SLIMBUS_6_TX    15
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#define PRIMARY_MI2S_RX		16
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#define PRIMARY_MI2S_TX		17
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#define SECONDARY_MI2S_RX	18
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#define SECONDARY_MI2S_TX	19
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#define TERTIARY_MI2S_RX	20
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#define TERTIARY_MI2S_TX	21
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#define QUATERNARY_MI2S_RX	22
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#define QUATERNARY_MI2S_TX	23
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#define PRIMARY_TDM_RX_0	24
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#define PRIMARY_TDM_TX_0	25
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#define PRIMARY_TDM_RX_1	26
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#define PRIMARY_TDM_TX_1	27
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#define PRIMARY_TDM_RX_2	28
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#define PRIMARY_TDM_TX_2	29
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#define PRIMARY_TDM_RX_3	30
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#define PRIMARY_TDM_TX_3	31
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#define PRIMARY_TDM_RX_4	32
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#define PRIMARY_TDM_TX_4	33
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#define PRIMARY_TDM_RX_5	34
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#define PRIMARY_TDM_TX_5	35
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#define PRIMARY_TDM_RX_6	36
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#define PRIMARY_TDM_TX_6	37
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#define PRIMARY_TDM_RX_7	38
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#define PRIMARY_TDM_TX_7	39
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#define SECONDARY_TDM_RX_0	40
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#define SECONDARY_TDM_TX_0	41
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#define SECONDARY_TDM_RX_1	42
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#define SECONDARY_TDM_TX_1	43
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#define SECONDARY_TDM_RX_2	44
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#define SECONDARY_TDM_TX_2	45
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#define SECONDARY_TDM_RX_3	46
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#define SECONDARY_TDM_TX_3	47
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#define SECONDARY_TDM_RX_4	48
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#define SECONDARY_TDM_TX_4	49
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#define SECONDARY_TDM_RX_5	50
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#define SECONDARY_TDM_TX_5	51
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#define SECONDARY_TDM_RX_6	52
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#define SECONDARY_TDM_TX_6	53
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#define SECONDARY_TDM_RX_7	54
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#define SECONDARY_TDM_TX_7	55
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#define TERTIARY_TDM_RX_0	56
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#define TERTIARY_TDM_TX_0	57
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#define TERTIARY_TDM_RX_1	58
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#define TERTIARY_TDM_TX_1	59
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#define TERTIARY_TDM_RX_2	60
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#define TERTIARY_TDM_TX_2	61
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#define TERTIARY_TDM_RX_3	62
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#define TERTIARY_TDM_TX_3	63
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#define TERTIARY_TDM_RX_4	64
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#define TERTIARY_TDM_TX_4	65
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#define TERTIARY_TDM_RX_5	66
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#define TERTIARY_TDM_TX_5	67
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#define TERTIARY_TDM_RX_6	68
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#define TERTIARY_TDM_TX_6	69
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#define TERTIARY_TDM_RX_7	70
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#define TERTIARY_TDM_TX_7	71
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#define QUATERNARY_TDM_RX_0	72
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#define QUATERNARY_TDM_TX_0	73
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#define QUATERNARY_TDM_RX_1	74
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#define QUATERNARY_TDM_TX_1	75
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#define QUATERNARY_TDM_RX_2	76
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#define QUATERNARY_TDM_TX_2	77
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#define QUATERNARY_TDM_RX_3	78
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#define QUATERNARY_TDM_TX_3	79
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#define QUATERNARY_TDM_RX_4	80
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#define QUATERNARY_TDM_TX_4	81
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#define QUATERNARY_TDM_RX_5	82
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#define QUATERNARY_TDM_TX_5	83
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#define QUATERNARY_TDM_RX_6	84
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#define QUATERNARY_TDM_TX_6	85
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#define QUATERNARY_TDM_RX_7	86
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#define QUATERNARY_TDM_TX_7	87
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#define QUINARY_TDM_RX_0	88
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#define QUINARY_TDM_TX_0	89
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#define QUINARY_TDM_RX_1	90
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#define QUINARY_TDM_TX_1	91
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#define QUINARY_TDM_RX_2	92
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#define QUINARY_TDM_TX_2	93
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#define QUINARY_TDM_RX_3	94
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#define QUINARY_TDM_TX_3	95
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#define QUINARY_TDM_RX_4	96
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#define QUINARY_TDM_TX_4	97
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#define QUINARY_TDM_RX_5	98
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#define QUINARY_TDM_TX_5	99
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#define QUINARY_TDM_RX_6	100
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#define QUINARY_TDM_TX_6	101
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#define QUINARY_TDM_RX_7	102
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#define QUINARY_TDM_TX_7	103
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#define DISPLAY_PORT_RX		104
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#define WSA_CODEC_DMA_RX_0	105
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#define WSA_CODEC_DMA_TX_0	106
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#define WSA_CODEC_DMA_RX_1	107
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#define WSA_CODEC_DMA_TX_1	108
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#define WSA_CODEC_DMA_TX_2	109
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#define VA_CODEC_DMA_TX_0	110
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#define VA_CODEC_DMA_TX_1	111
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#define VA_CODEC_DMA_TX_2	112
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#define RX_CODEC_DMA_RX_0	113
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#define TX_CODEC_DMA_TX_0	114
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#define RX_CODEC_DMA_RX_1	115
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#define TX_CODEC_DMA_TX_1	116
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#define RX_CODEC_DMA_RX_2	117
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#define TX_CODEC_DMA_TX_2	118
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#define RX_CODEC_DMA_RX_3	119
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#define TX_CODEC_DMA_TX_3	120
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#define RX_CODEC_DMA_RX_4	121
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#define TX_CODEC_DMA_TX_4	122
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#define RX_CODEC_DMA_RX_5	123
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#define TX_CODEC_DMA_TX_5	124
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#define RX_CODEC_DMA_RX_6	125
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#define RX_CODEC_DMA_RX_7	126
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#define QUINARY_MI2S_RX		127
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#define QUINARY_MI2S_TX		128
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#define DISPLAY_PORT_RX_0	DISPLAY_PORT_RX
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#define DISPLAY_PORT_RX_1	129
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#define DISPLAY_PORT_RX_2	130
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#define DISPLAY_PORT_RX_3	131
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#define DISPLAY_PORT_RX_4	132
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#define DISPLAY_PORT_RX_5	133
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#define DISPLAY_PORT_RX_6	134
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#define DISPLAY_PORT_RX_7	135
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#define USB_RX			136
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#define LPASS_CLK_ID_PRI_MI2S_IBIT	1
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#define LPASS_CLK_ID_PRI_MI2S_EBIT	2
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#define LPASS_CLK_ID_SEC_MI2S_IBIT	3
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#define LPASS_CLK_ID_SEC_MI2S_EBIT	4
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#define LPASS_CLK_ID_TER_MI2S_IBIT	5
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#define LPASS_CLK_ID_TER_MI2S_EBIT	6
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#define LPASS_CLK_ID_QUAD_MI2S_IBIT	7
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#define LPASS_CLK_ID_QUAD_MI2S_EBIT	8
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#define LPASS_CLK_ID_SPEAKER_I2S_IBIT	9
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#define LPASS_CLK_ID_SPEAKER_I2S_EBIT	10
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#define LPASS_CLK_ID_SPEAKER_I2S_OSR	11
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#define LPASS_CLK_ID_QUI_MI2S_IBIT	12
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#define LPASS_CLK_ID_QUI_MI2S_EBIT	13
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#define LPASS_CLK_ID_SEN_MI2S_IBIT	14
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#define LPASS_CLK_ID_SEN_MI2S_EBIT	15
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#define LPASS_CLK_ID_INT0_MI2S_IBIT	16
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#define LPASS_CLK_ID_INT1_MI2S_IBIT	17
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#define LPASS_CLK_ID_INT2_MI2S_IBIT	18
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#define LPASS_CLK_ID_INT3_MI2S_IBIT	19
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#define LPASS_CLK_ID_INT4_MI2S_IBIT	20
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#define LPASS_CLK_ID_INT5_MI2S_IBIT	21
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#define LPASS_CLK_ID_INT6_MI2S_IBIT	22
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#define LPASS_CLK_ID_QUI_MI2S_OSR	23
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#define LPASS_CLK_ID_PRI_PCM_IBIT	24
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#define LPASS_CLK_ID_PRI_PCM_EBIT	25
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#define LPASS_CLK_ID_SEC_PCM_IBIT	26
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#define LPASS_CLK_ID_SEC_PCM_EBIT	27
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#define LPASS_CLK_ID_TER_PCM_IBIT	28
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#define LPASS_CLK_ID_TER_PCM_EBIT	29
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#define LPASS_CLK_ID_QUAD_PCM_IBIT	30
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#define LPASS_CLK_ID_QUAD_PCM_EBIT	31
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#define LPASS_CLK_ID_QUIN_PCM_IBIT	32
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#define LPASS_CLK_ID_QUIN_PCM_EBIT	33
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#define LPASS_CLK_ID_QUI_PCM_OSR	34
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#define LPASS_CLK_ID_PRI_TDM_IBIT	35
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#define LPASS_CLK_ID_PRI_TDM_EBIT	36
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#define LPASS_CLK_ID_SEC_TDM_IBIT	37
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#define LPASS_CLK_ID_SEC_TDM_EBIT	38
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#define LPASS_CLK_ID_TER_TDM_IBIT	39
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#define LPASS_CLK_ID_TER_TDM_EBIT	40
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#define LPASS_CLK_ID_QUAD_TDM_IBIT	41
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#define LPASS_CLK_ID_QUAD_TDM_EBIT	42
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#define LPASS_CLK_ID_QUIN_TDM_IBIT	43
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#define LPASS_CLK_ID_QUIN_TDM_EBIT	44
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#define LPASS_CLK_ID_QUIN_TDM_OSR	45
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#define LPASS_CLK_ID_MCLK_1		46
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#define LPASS_CLK_ID_MCLK_2		47
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#define LPASS_CLK_ID_MCLK_3		48
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#define LPASS_CLK_ID_MCLK_4		49
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#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE	50
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#define LPASS_CLK_ID_INT_MCLK_0		51
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#define LPASS_CLK_ID_INT_MCLK_1		52
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#define LPASS_CLK_ID_MCLK_5		53
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#define LPASS_CLK_ID_WSA_CORE_MCLK	54
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#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK	55
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#define LPASS_CLK_ID_VA_CORE_MCLK	56
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#define LPASS_CLK_ID_TX_CORE_MCLK	57
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#define LPASS_CLK_ID_TX_CORE_NPL_MCLK	58
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#define LPASS_CLK_ID_RX_CORE_MCLK	59
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#define LPASS_CLK_ID_RX_CORE_NPL_MCLK	60
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#define LPASS_CLK_ID_VA_CORE_2X_MCLK	61
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/* Clock ID for MCLK for WSA2 core */
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#define LPASS_CLK_ID_WSA2_CORE_MCLK	62
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/* Clock ID for NPL MCLK for WSA2 core */
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#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK	63
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/* Clock ID for RX Core TX MCLK */
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#define LPASS_CLK_ID_RX_CORE_TX_MCLK	64
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/* Clock ID for RX CORE TX 2X MCLK */
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#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK	65
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/* Clock ID for WSA core TX MCLK */
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#define LPASS_CLK_ID_WSA_CORE_TX_MCLK	66
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/* Clock ID for WSA core TX 2X MCLK */
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#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK	67
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/* Clock ID for WSA2 core TX MCLK */
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#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK	68
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/* Clock ID for WSA2 core TX 2X MCLK */
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#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK	69
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/* Clock ID for RX CORE MCLK2 2X  MCLK */
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#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK	70
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#define LPASS_HW_AVTIMER_VOTE		101
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#define LPASS_HW_MACRO_VOTE		102
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#define LPASS_HW_DCODEC_VOTE		103
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#define Q6AFE_MAX_CLK_ID			104
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#define LPASS_CLK_ATTRIBUTE_INVALID		0x0
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#define LPASS_CLK_ATTRIBUTE_COUPLE_NO		0x1
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#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND	0x2
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#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR	0x3
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#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */
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