CoCalc -- intel8x0.c

GitHub Repository: torvalds/linux
Path: blob/master/sound/pci/intel8x0.c
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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 *   ALSA driver for Intel ICH (i8x0) chipsets
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 *
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 *	Copyright (c) 2000 Jaroslav Kysela <[email protected]>
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 *
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 *   This code also contains alpha support for SiS 735 chipsets provided
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 *   by Mike Pieper <[email protected]>. We have no datasheet
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 *   for SiS735, so the code is not fully functional.
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 *
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 */      
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/ac97_codec.h>
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#include <sound/info.h>
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#include <sound/initval.h>
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MODULE_AUTHOR("Jaroslav Kysela <[email protected]>");
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MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
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MODULE_LICENSE("GPL");
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static int index = SNDRV_DEFAULT_IDX1;	/* Index 0-MAX */
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static char *id = SNDRV_DEFAULT_STR1;	/* ID for this card */
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static int ac97_clock;
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static char *ac97_quirk;
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static bool buggy_semaphore;
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static int buggy_irq = -1; /* auto-check */
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static bool xbox;
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static int spdif_aclink = -1;
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static int inside_vm = -1;
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module_param(index, int, 0444);
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MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
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module_param(id, charp, 0444);
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MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
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module_param(ac97_clock, int, 0444);
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MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
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module_param(ac97_quirk, charp, 0444);
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MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
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module_param(buggy_semaphore, bool, 0444);
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MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
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module_param(buggy_irq, bint, 0444);
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MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
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module_param(xbox, bool, 0444);
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MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
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module_param(spdif_aclink, int, 0444);
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MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
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module_param(inside_vm, bint, 0444);
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MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
59

60
/* just for backward compatibility */
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static bool enable;
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module_param(enable, bool, 0444);
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static int joystick;
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module_param(joystick, int, 0444);
65

66
/*
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 *  Direct registers
68
 */
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enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
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#define ICHREG(x) ICH_REG_##x
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#define DEFINE_REGSET(name,base) \
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enum { \
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	ICH_REG_##name##_BDBAR	= base + 0x0,	/* dword - buffer descriptor list base address */ \
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	ICH_REG_##name##_CIV	= base + 0x04,	/* byte - current index value */ \
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	ICH_REG_##name##_LVI	= base + 0x05,	/* byte - last valid index */ \
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	ICH_REG_##name##_SR	= base + 0x06,	/* byte - status register */ \
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	ICH_REG_##name##_PICB	= base + 0x08,	/* word - position in current buffer */ \
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	ICH_REG_##name##_PIV	= base + 0x0a,	/* byte - prefetched index value */ \
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	ICH_REG_##name##_CR	= base + 0x0b,	/* byte - control register */ \
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}
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/* busmaster blocks */
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DEFINE_REGSET(OFF, 0);		/* offset */
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DEFINE_REGSET(PI, 0x00);	/* PCM in */
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DEFINE_REGSET(PO, 0x10);	/* PCM out */
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DEFINE_REGSET(MC, 0x20);	/* Mic in */
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/* ICH4 busmaster blocks */
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DEFINE_REGSET(MC2, 0x40);	/* Mic in 2 */
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DEFINE_REGSET(PI2, 0x50);	/* PCM in 2 */
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DEFINE_REGSET(SP, 0x60);	/* SPDIF out */
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/* values for each busmaster block */
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/* LVI */
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#define ICH_REG_LVI_MASK		0x1f
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/* SR */
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#define ICH_FIFOE			0x10	/* FIFO error */
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#define ICH_BCIS			0x08	/* buffer completion interrupt status */
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#define ICH_LVBCI			0x04	/* last valid buffer completion interrupt */
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#define ICH_CELV			0x02	/* current equals last valid */
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#define ICH_DCH				0x01	/* DMA controller halted */
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/* PIV */
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#define ICH_REG_PIV_MASK		0x1f	/* mask */
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/* CR */
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#define ICH_IOCE			0x10	/* interrupt on completion enable */
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#define ICH_FEIE			0x08	/* fifo error interrupt enable */
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#define ICH_LVBIE			0x04	/* last valid buffer interrupt enable */
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#define ICH_RESETREGS			0x02	/* reset busmaster registers */
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#define ICH_STARTBM			0x01	/* start busmaster operation */
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117

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/* global block */
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#define ICH_REG_GLOB_CNT		0x2c	/* dword - global control */
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#define   ICH_PCM_SPDIF_MASK	0xc0000000	/* s/pdif pcm slot mask (ICH4) */
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#define   ICH_PCM_SPDIF_NONE	0x00000000	/* reserved - undefined */
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#define   ICH_PCM_SPDIF_78	0x40000000	/* s/pdif pcm on slots 7&8 */
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#define   ICH_PCM_SPDIF_69	0x80000000	/* s/pdif pcm on slots 6&9 */
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#define   ICH_PCM_SPDIF_1011	0xc0000000	/* s/pdif pcm on slots 10&11 */
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#define   ICH_PCM_20BIT		0x00400000	/* 20-bit samples (ICH4) */
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#define   ICH_PCM_246_MASK	0x00300000	/* chan mask (not all chips) */
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#define   ICH_PCM_8		0x00300000      /* 8 channels (not all chips) */
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#define   ICH_PCM_6		0x00200000	/* 6 channels (not all chips) */
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#define   ICH_PCM_4		0x00100000	/* 4 channels (not all chips) */
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#define   ICH_PCM_2		0x00000000	/* 2 channels (stereo) */
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#define   ICH_SIS_PCM_246_MASK	0x000000c0	/* 6 channels (SIS7012) */
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#define   ICH_SIS_PCM_6		0x00000080	/* 6 channels (SIS7012) */
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#define   ICH_SIS_PCM_4		0x00000040	/* 4 channels (SIS7012) */
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#define   ICH_SIS_PCM_2		0x00000000	/* 2 channels (SIS7012) */
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#define   ICH_TRIE		0x00000040	/* tertiary resume interrupt enable */
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#define   ICH_SRIE		0x00000020	/* secondary resume interrupt enable */
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#define   ICH_PRIE		0x00000010	/* primary resume interrupt enable */
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#define   ICH_ACLINK		0x00000008	/* AClink shut off */
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#define   ICH_AC97WARM		0x00000004	/* AC'97 warm reset */
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#define   ICH_AC97COLD		0x00000002	/* AC'97 cold reset */
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#define   ICH_GIE		0x00000001	/* GPI interrupt enable */
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#define ICH_REG_GLOB_STA		0x30	/* dword - global status */
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#define   ICH_TRI		0x20000000	/* ICH4: tertiary (AC_SDIN2) resume interrupt */
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#define   ICH_TCR		0x10000000	/* ICH4: tertiary (AC_SDIN2) codec ready */
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#define   ICH_BCS		0x08000000	/* ICH4: bit clock stopped */
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#define   ICH_SPINT		0x04000000	/* ICH4: S/PDIF interrupt */
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#define   ICH_P2INT		0x02000000	/* ICH4: PCM2-In interrupt */
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#define   ICH_M2INT		0x01000000	/* ICH4: Mic2-In interrupt */
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#define   ICH_SAMPLE_CAP	0x00c00000	/* ICH4: sample capability bits (RO) */
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#define   ICH_SAMPLE_16_20	0x00400000	/* ICH4: 16- and 20-bit samples */
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#define   ICH_MULTICHAN_CAP	0x00300000	/* ICH4: multi-channel capability bits (RO) */
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#define   ICH_SIS_TRI		0x00080000	/* SIS: tertiary resume irq */
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#define   ICH_SIS_TCR		0x00040000	/* SIS: tertiary codec ready */
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#define   ICH_MD3		0x00020000	/* modem power down semaphore */
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#define   ICH_AD3		0x00010000	/* audio power down semaphore */
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#define   ICH_RCS		0x00008000	/* read completion status */
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#define   ICH_BIT3		0x00004000	/* bit 3 slot 12 */
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#define   ICH_BIT2		0x00002000	/* bit 2 slot 12 */
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#define   ICH_BIT1		0x00001000	/* bit 1 slot 12 */
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#define   ICH_SRI		0x00000800	/* secondary (AC_SDIN1) resume interrupt */
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#define   ICH_PRI		0x00000400	/* primary (AC_SDIN0) resume interrupt */
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#define   ICH_SCR		0x00000200	/* secondary (AC_SDIN1) codec ready */
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#define   ICH_PCR		0x00000100	/* primary (AC_SDIN0) codec ready */
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#define   ICH_MCINT		0x00000080	/* MIC capture interrupt */
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#define   ICH_POINT		0x00000040	/* playback interrupt */
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#define   ICH_PIINT		0x00000020	/* capture interrupt */
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#define   ICH_NVSPINT		0x00000010	/* nforce spdif interrupt */
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#define   ICH_MOINT		0x00000004	/* modem playback interrupt */
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#define   ICH_MIINT		0x00000002	/* modem capture interrupt */
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#define   ICH_GSCI		0x00000001	/* GPI status change interrupt */
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#define ICH_REG_ACC_SEMA		0x34	/* byte - codec write semaphore */
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#define   ICH_CAS		0x01		/* codec access semaphore */
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#define ICH_REG_SDM		0x80
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#define   ICH_DI2L_MASK		0x000000c0	/* PCM In 2, Mic In 2 data in line */
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#define   ICH_DI2L_SHIFT	6
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#define   ICH_DI1L_MASK		0x00000030	/* PCM In 1, Mic In 1 data in line */
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#define   ICH_DI1L_SHIFT	4
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#define   ICH_SE		0x00000008	/* steer enable */
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#define   ICH_LDI_MASK		0x00000003	/* last codec read data input */
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#define ICH_MAX_FRAGS		32		/* max hw frags */
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/*
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 * registers for Ali5455
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 */
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/* ALi 5455 busmaster blocks */
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DEFINE_REGSET(AL_PI, 0x40);	/* ALi PCM in */
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DEFINE_REGSET(AL_PO, 0x50);	/* Ali PCM out */
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DEFINE_REGSET(AL_MC, 0x60);	/* Ali Mic in */
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DEFINE_REGSET(AL_CDC_SPO, 0x70);	/* Ali Codec SPDIF out */
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DEFINE_REGSET(AL_CENTER, 0x80);		/* Ali center out */
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DEFINE_REGSET(AL_LFE, 0x90);		/* Ali center out */
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DEFINE_REGSET(AL_CLR_SPI, 0xa0);	/* Ali Controller SPDIF in */
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DEFINE_REGSET(AL_CLR_SPO, 0xb0);	/* Ali Controller SPDIF out */
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DEFINE_REGSET(AL_I2S, 0xc0);	/* Ali I2S in */
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DEFINE_REGSET(AL_PI2, 0xd0);	/* Ali PCM2 in */
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DEFINE_REGSET(AL_MC2, 0xe0);	/* Ali Mic2 in */
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enum {
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	ICH_REG_ALI_SCR = 0x00,		/* System Control Register */
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	ICH_REG_ALI_SSR = 0x04,		/* System Status Register  */
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	ICH_REG_ALI_DMACR = 0x08,	/* DMA Control Register    */
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	ICH_REG_ALI_FIFOCR1 = 0x0c,	/* FIFO Control Register 1  */
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	ICH_REG_ALI_INTERFACECR = 0x10,	/* Interface Control Register */
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	ICH_REG_ALI_INTERRUPTCR = 0x14,	/* Interrupt control Register */
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	ICH_REG_ALI_INTERRUPTSR = 0x18,	/* Interrupt  Status Register */
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	ICH_REG_ALI_FIFOCR2 = 0x1c,	/* FIFO Control Register 2   */
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	ICH_REG_ALI_CPR = 0x20,		/* Command Port Register     */
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	ICH_REG_ALI_CPR_ADDR = 0x22,	/* ac97 addr write */
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	ICH_REG_ALI_SPR = 0x24,		/* Status Port Register      */
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	ICH_REG_ALI_SPR_ADDR = 0x26,	/* ac97 addr read */
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	ICH_REG_ALI_FIFOCR3 = 0x2c,	/* FIFO Control Register 3  */
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	ICH_REG_ALI_TTSR = 0x30,	/* Transmit Tag Slot Register */
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	ICH_REG_ALI_RTSR = 0x34,	/* Receive Tag Slot  Register */
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	ICH_REG_ALI_CSPSR = 0x38,	/* Command/Status Port Status Register */
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	ICH_REG_ALI_CAS = 0x3c,		/* Codec Write Semaphore Register */
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	ICH_REG_ALI_HWVOL = 0xf0,	/* hardware volume control/status */
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	ICH_REG_ALI_I2SCR = 0xf4,	/* I2S control/status */
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	ICH_REG_ALI_SPDIFCSR = 0xf8,	/* spdif channel status register  */
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	ICH_REG_ALI_SPDIFICS = 0xfc,	/* spdif interface control/status  */
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};
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#define ALI_CAS_SEM_BUSY	0x80000000
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#define ALI_CPR_ADDR_SECONDARY	0x100
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#define ALI_CPR_ADDR_READ	0x80
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#define ALI_CSPSR_CODEC_READY	0x08
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#define ALI_CSPSR_READ_OK	0x02
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#define ALI_CSPSR_WRITE_OK	0x01
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/* interrupts for the whole chip by interrupt status register finish */
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#define ALI_INT_MICIN2		(1<<26)
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#define ALI_INT_PCMIN2		(1<<25)
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#define ALI_INT_I2SIN		(1<<24)
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#define ALI_INT_SPDIFOUT	(1<<23)	/* controller spdif out INTERRUPT */
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#define ALI_INT_SPDIFIN		(1<<22)
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#define ALI_INT_LFEOUT		(1<<21)
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#define ALI_INT_CENTEROUT	(1<<20)
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#define ALI_INT_CODECSPDIFOUT	(1<<19)
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#define ALI_INT_MICIN		(1<<18)
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#define ALI_INT_PCMOUT		(1<<17)
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#define ALI_INT_PCMIN		(1<<16)
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#define ALI_INT_CPRAIS		(1<<7)	/* command port available */
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#define ALI_INT_SPRAIS		(1<<5)	/* status port available */
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#define ALI_INT_GPIO		(1<<1)
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#define ALI_INT_MASK		(ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
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				 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
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#define ICH_ALI_SC_RESET	(1<<31)	/* master reset */
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#define ICH_ALI_SC_AC97_DBL	(1<<30)
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#define ICH_ALI_SC_CODEC_SPDF	(3<<20)	/* 1=7/8, 2=6/9, 3=10/11 */
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#define ICH_ALI_SC_IN_BITS	(3<<18)
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#define ICH_ALI_SC_OUT_BITS	(3<<16)
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#define ICH_ALI_SC_6CH_CFG	(3<<14)
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#define ICH_ALI_SC_PCM_4	(1<<8)
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#define ICH_ALI_SC_PCM_6	(2<<8)
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#define ICH_ALI_SC_PCM_246_MASK	(3<<8)
260

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#define ICH_ALI_SS_SEC_ID	(3<<5)
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#define ICH_ALI_SS_PRI_ID	(3<<3)
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#define ICH_ALI_IF_AC97SP	(1<<21)
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#define ICH_ALI_IF_MC		(1<<20)
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#define ICH_ALI_IF_PI		(1<<19)
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#define ICH_ALI_IF_MC2		(1<<18)
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#define ICH_ALI_IF_PI2		(1<<17)
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#define ICH_ALI_IF_LINE_SRC	(1<<15)	/* 0/1 = slot 3/6 */
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#define ICH_ALI_IF_MIC_SRC	(1<<14)	/* 0/1 = slot 3/6 */
271
#define ICH_ALI_IF_SPDF_SRC	(3<<12)	/* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
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#define ICH_ALI_IF_AC97_OUT	(3<<8)	/* 00 = PCM, 10 = spdif-in, 11 = i2s */
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#define ICH_ALI_IF_PO_SPDF	(1<<3)
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#define ICH_ALI_IF_PO		(1<<1)
275

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/*
277
 *  
278
 */
279

280
enum {
281
	ICHD_PCMIN,
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	ICHD_PCMOUT,
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	ICHD_MIC,
284
	ICHD_MIC2,
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	ICHD_PCM2IN,
286
	ICHD_SPBAR,
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	ICHD_LAST = ICHD_SPBAR
288
};
289
enum {
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	NVD_PCMIN,
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	NVD_PCMOUT,
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	NVD_MIC,
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	NVD_SPBAR,
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	NVD_LAST = NVD_SPBAR
295
};
296
enum {
297
	ALID_PCMIN,
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	ALID_PCMOUT,
299
	ALID_MIC,
300
	ALID_AC97SPDIFOUT,
301
	ALID_SPDIFIN,
302
	ALID_SPDIFOUT,
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	ALID_LAST = ALID_SPDIFOUT
304
};
305

306
#define get_ichdev(substream) (substream->runtime->private_data)
307

308
struct ichdev {
309
	unsigned int ichd;			/* ich device number */
310
	unsigned long reg_offset;		/* offset to bmaddr */
311
	__le32 *bdbar;				/* CPU address (32bit) */
312
	unsigned int bdbar_addr;		/* PCI bus address (32bit) */
313
	struct snd_pcm_substream *substream;
314
	unsigned int physbuf;			/* physical address (32bit) */
315
        unsigned int size;
316
        unsigned int fragsize;
317
        unsigned int fragsize1;
318
        unsigned int position;
319
	unsigned int pos_shift;
320
	unsigned int last_pos;
321
        int frags;
322
        int lvi;
323
        int lvi_frag;
324
	int civ;
325
	int ack;
326
	int ack_reload;
327
	unsigned int ack_bit;
328
	unsigned int roff_sr;
329
	unsigned int roff_picb;
330
	unsigned int int_sta_mask;		/* interrupt status mask */
331
	unsigned int ali_slot;			/* ALI DMA slot */
332
	struct ac97_pcm *pcm;
333
	int pcm_open_flag;
334
	unsigned int prepared:1;
335
	unsigned int suspended: 1;
336
};
337

338
struct intel8x0 {
339
	unsigned int device_type;
340

341
	int irq;
342

343
	void __iomem *addr;
344
	void __iomem *bmaddr;
345

346
	struct pci_dev *pci;
347
	struct snd_card *card;
348

349
	int pcm_devs;
350
	struct snd_pcm *pcm[6];
351
	struct ichdev ichd[6];
352

353
	unsigned multi4: 1,
354
		 multi6: 1,
355
		 multi8 :1,
356
		 dra: 1,
357
		 smp20bit: 1;
358
	unsigned in_ac97_init: 1,
359
		 in_sdin_init: 1;
360
	unsigned in_measurement: 1;	/* during ac97 clock measurement */
361
	unsigned fix_nocache: 1; 	/* workaround for 440MX */
362
	unsigned buggy_irq: 1;		/* workaround for buggy mobos */
363
	unsigned xbox: 1;		/* workaround for Xbox AC'97 detection */
364
	unsigned buggy_semaphore: 1;	/* workaround for buggy codec semaphore */
365
	unsigned inside_vm: 1;		/* enable VM optimization */
366

367
	int spdif_idx;	/* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
368
	unsigned int sdm_saved;	/* SDM reg value */
369

370
	struct snd_ac97_bus *ac97_bus;
371
	struct snd_ac97 *ac97[3];
372
	unsigned int ac97_sdin[3];
373
	unsigned int max_codecs, ncodecs;
374
	const unsigned int *codec_bit;
375
	unsigned int codec_isr_bits;
376
	unsigned int codec_ready_bits;
377

378
	spinlock_t reg_lock;
379
	
380
	u32 bdbars_count;
381
	struct snd_dma_buffer *bdbars;
382
	u32 int_sta_reg;		/* interrupt status register */
383
	u32 int_sta_mask;		/* interrupt status mask */
384
};
385

386
static const struct pci_device_id snd_intel8x0_ids[] = {
387
	{ PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },	/* 82801AA */
388
	{ PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },	/* 82901AB */
389
	{ PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },	/* 82801BA */
390
	{ PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },	/* ICH3 */
391
	{ PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
392
	{ PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
393
	{ PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
394
	{ PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
395
	{ PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
396
	{ PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
397
	{ PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },	/* 440MX */
398
	{ PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },	/* SI7012 */
399
	{ PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE },	/* NFORCE */
400
	{ PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE },	/* MCP04 */
401
	{ PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE },	/* NFORCE2 */
402
	{ PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE },	/* CK804 */
403
	{ PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE },	/* CK8 */
404
	{ PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE },	/* NFORCE3 */
405
	{ PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE },	/* CK8S */
406
	{ PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE },	/* MCP51 */
407
	{ PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },	/* AMD8111 */
408
	{ PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },	/* AMD768 */
409
	{ PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
410
	{ 0, }
411
};
412

413
MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
414

415
/*
416
 *  Lowlevel I/O - busmaster
417
 */
418

419
static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
420
{
421
	return ioread8(chip->bmaddr + offset);
422
}
423

424
static inline u16 igetword(struct intel8x0 *chip, u32 offset)
425
{
426
	return ioread16(chip->bmaddr + offset);
427
}
428

429
static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
430
{
431
	return ioread32(chip->bmaddr + offset);
432
}
433

434
static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
435
{
436
	iowrite8(val, chip->bmaddr + offset);
437
}
438

439
static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
440
{
441
	iowrite16(val, chip->bmaddr + offset);
442
}
443

444
static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
445
{
446
	iowrite32(val, chip->bmaddr + offset);
447
}
448

449
/*
450
 *  Lowlevel I/O - AC'97 registers
451
 */
452

453
static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
454
{
455
	return ioread16(chip->addr + offset);
456
}
457

458
static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
459
{
460
	iowrite16(val, chip->addr + offset);
461
}
462

463
/*
464
 *  Basic I/O
465
 */
466

467
/*
468
 * access to AC97 codec via normal i/o (for ICH and SIS7012)
469
 */
470

471
static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
472
{
473
	int time;
474
	
475
	if (codec > 2)
476
		return -EIO;
477
	if (chip->in_sdin_init) {
478
		/* we don't know the ready bit assignment at the moment */
479
		/* so we check any */
480
		codec = chip->codec_isr_bits;
481
	} else {
482
		codec = chip->codec_bit[chip->ac97_sdin[codec]];
483
	}
484

485
	/* codec ready ? */
486
	if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
487
		return -EIO;
488

489
	if (chip->buggy_semaphore)
490
		return 0; /* just ignore ... */
491

492
	/* Anyone holding a semaphore for 1 msec should be shot... */
493
	time = 100;
494
      	do {
495
      		if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
496
      			return 0;
497
		udelay(10);
498
	} while (time--);
499

500
	/* access to some forbidden (non existent) ac97 registers will not
501
	 * reset the semaphore. So even if you don't get the semaphore, still
502
	 * continue the access. We don't need the semaphore anyway. */
503
	dev_err(chip->card->dev,
504
		"codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
505
			igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
506
	iagetword(chip, 0);	/* clear semaphore flag */
507
	/* I don't care about the semaphore */
508
	return -EBUSY;
509
}
510
 
511
static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
512
				     unsigned short reg,
513
				     unsigned short val)
514
{
515
	struct intel8x0 *chip = ac97->private_data;
516
	
517
	if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
518
		if (! chip->in_ac97_init)
519
			dev_err(chip->card->dev,
520
				"codec_write %d: semaphore is not ready for register 0x%x\n",
521
				ac97->num, reg);
522
	}
523
	iaputword(chip, reg + ac97->num * 0x80, val);
524
}
525

526
static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
527
					      unsigned short reg)
528
{
529
	struct intel8x0 *chip = ac97->private_data;
530
	unsigned short res;
531
	unsigned int tmp;
532

533
	if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
534
		if (! chip->in_ac97_init)
535
			dev_err(chip->card->dev,
536
				"codec_read %d: semaphore is not ready for register 0x%x\n",
537
				ac97->num, reg);
538
		res = 0xffff;
539
	} else {
540
		res = iagetword(chip, reg + ac97->num * 0x80);
541
		tmp = igetdword(chip, ICHREG(GLOB_STA));
542
		if (tmp & ICH_RCS) {
543
			/* reset RCS and preserve other R/WC bits */
544
			iputdword(chip, ICHREG(GLOB_STA), tmp &
545
				  ~(chip->codec_ready_bits | ICH_GSCI));
546
			if (! chip->in_ac97_init)
547
				dev_err(chip->card->dev,
548
					"codec_read %d: read timeout for register 0x%x\n",
549
					ac97->num, reg);
550
			res = 0xffff;
551
		}
552
	}
553
	return res;
554
}
555

556
static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
557
					 unsigned int codec)
558
{
559
	unsigned int tmp;
560

561
	if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
562
		iagetword(chip, codec * 0x80);
563
		tmp = igetdword(chip, ICHREG(GLOB_STA));
564
		if (tmp & ICH_RCS) {
565
			/* reset RCS and preserve other R/WC bits */
566
			iputdword(chip, ICHREG(GLOB_STA), tmp &
567
				  ~(chip->codec_ready_bits | ICH_GSCI));
568
		}
569
	}
570
}
571

572
/*
573
 * access to AC97 for Ali5455
574
 */
575
static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
576
{
577
	int count = 0;
578
	for (count = 0; count < 0x7f; count++) {
579
		int val = igetbyte(chip, ICHREG(ALI_CSPSR));
580
		if (val & mask)
581
			return 0;
582
	}
583
	if (! chip->in_ac97_init)
584
		dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
585
	return -EBUSY;
586
}
587

588
static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
589
{
590
	int time = 100;
591
	if (chip->buggy_semaphore)
592
		return 0; /* just ignore ... */
593
	while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
594
		udelay(1);
595
	if (! time && ! chip->in_ac97_init)
596
		dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
597
	return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
598
}
599

600
static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
601
{
602
	struct intel8x0 *chip = ac97->private_data;
603
	unsigned short data = 0xffff;
604

605
	if (snd_intel8x0_ali_codec_semaphore(chip))
606
		goto __err;
607
	reg |= ALI_CPR_ADDR_READ;
608
	if (ac97->num)
609
		reg |= ALI_CPR_ADDR_SECONDARY;
610
	iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
611
	if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
612
		goto __err;
613
	data = igetword(chip, ICHREG(ALI_SPR));
614
 __err:
615
	return data;
616
}
617

618
static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
619
					 unsigned short val)
620
{
621
	struct intel8x0 *chip = ac97->private_data;
622

623
	if (snd_intel8x0_ali_codec_semaphore(chip))
624
		return;
625
	iputword(chip, ICHREG(ALI_CPR), val);
626
	if (ac97->num)
627
		reg |= ALI_CPR_ADDR_SECONDARY;
628
	iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
629
	snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
630
}
631

632

633
/*
634
 * DMA I/O
635
 */
636
static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 
637
{
638
	int idx;
639
	__le32 *bdbar = ichdev->bdbar;
640
	unsigned long port = ichdev->reg_offset;
641

642
	iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
643
	if (ichdev->size == ichdev->fragsize) {
644
		ichdev->ack_reload = ichdev->ack = 2;
645
		ichdev->fragsize1 = ichdev->fragsize >> 1;
646
		for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
647
			bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
648
			bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
649
						     ichdev->fragsize1 >> ichdev->pos_shift);
650
			bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
651
			bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
652
						     ichdev->fragsize1 >> ichdev->pos_shift);
653
		}
654
		ichdev->frags = 2;
655
	} else {
656
		ichdev->ack_reload = ichdev->ack = 1;
657
		ichdev->fragsize1 = ichdev->fragsize;
658
		for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
659
			bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
660
						     (((idx >> 1) * ichdev->fragsize) %
661
						      ichdev->size));
662
			bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
663
						     ichdev->fragsize >> ichdev->pos_shift);
664
#if 0
665
			dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
666
			       idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
667
#endif
668
		}
669
		ichdev->frags = ichdev->size / ichdev->fragsize;
670
	}
671
	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
672
	ichdev->civ = 0;
673
	iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
674
	ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
675
	ichdev->position = 0;
676
#if 0
677
	dev_dbg(chip->card->dev,
678
		"lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
679
	       ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
680
	       ichdev->fragsize1);
681
#endif
682
	/* clear interrupts */
683
	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
684
}
685

686
/*
687
 *  Interrupt handler
688
 */
689

690
static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
691
{
692
	unsigned long port = ichdev->reg_offset;
693
	int status, civ, i, step;
694
	int ack = 0;
695

696
	if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
697
		return;
698

699
	scoped_guard(spinlock_irqsave, &chip->reg_lock) {
700
		status = igetbyte(chip, port + ichdev->roff_sr);
701
		civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
702
		if (!(status & ICH_BCIS)) {
703
			step = 0;
704
		} else if (civ == ichdev->civ) {
705
			step = 1;
706
			ichdev->civ++;
707
			ichdev->civ &= ICH_REG_LVI_MASK;
708
		} else {
709
			step = civ - ichdev->civ;
710
			if (step < 0)
711
				step += ICH_REG_LVI_MASK + 1;
712
			ichdev->civ = civ;
713
		}
714

715
		ichdev->position += step * ichdev->fragsize1;
716
		if (! chip->in_measurement)
717
			ichdev->position %= ichdev->size;
718
		ichdev->lvi += step;
719
		ichdev->lvi &= ICH_REG_LVI_MASK;
720
		iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
721
		for (i = 0; i < step; i++) {
722
			ichdev->lvi_frag++;
723
			ichdev->lvi_frag %= ichdev->frags;
724
			ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
725
#if 0
726
			dev_dbg(chip->card->dev,
727
				"new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
728
				ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
729
				ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
730
				inl(port + 4), inb(port + ICH_REG_OFF_CR));
731
#endif
732
			if (--ichdev->ack == 0) {
733
				ichdev->ack = ichdev->ack_reload;
734
				ack = 1;
735
			}
736
		}
737
	}
738
	if (ack && ichdev->substream) {
739
		snd_pcm_period_elapsed(ichdev->substream);
740
	}
741
	iputbyte(chip, port + ichdev->roff_sr,
742
		 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
743
}
744

745
static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
746
{
747
	struct intel8x0 *chip = dev_id;
748
	struct ichdev *ichdev;
749
	unsigned int status;
750
	unsigned int i;
751

752
	status = igetdword(chip, chip->int_sta_reg);
753
	if (status == 0xffffffff)	/* we are not yet resumed */
754
		return IRQ_NONE;
755

756
	if ((status & chip->int_sta_mask) == 0) {
757
		if (status) {
758
			/* ack */
759
			iputdword(chip, chip->int_sta_reg, status);
760
			if (! chip->buggy_irq)
761
				status = 0;
762
		}
763
		return IRQ_RETVAL(status);
764
	}
765

766
	for (i = 0; i < chip->bdbars_count; i++) {
767
		ichdev = &chip->ichd[i];
768
		if (status & ichdev->int_sta_mask)
769
			snd_intel8x0_update(chip, ichdev);
770
	}
771

772
	/* ack them */
773
	iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
774
	
775
	return IRQ_HANDLED;
776
}
777

778
/*
779
 *  PCM part
780
 */
781

782
static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
783
{
784
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
785
	struct ichdev *ichdev = get_ichdev(substream);
786
	unsigned char val = 0;
787
	unsigned long port = ichdev->reg_offset;
788

789
	switch (cmd) {
790
	case SNDRV_PCM_TRIGGER_RESUME:
791
		ichdev->suspended = 0;
792
		fallthrough;
793
	case SNDRV_PCM_TRIGGER_START:
794
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
795
		val = ICH_IOCE | ICH_STARTBM;
796
		ichdev->last_pos = ichdev->position;
797
		break;
798
	case SNDRV_PCM_TRIGGER_SUSPEND:
799
		ichdev->suspended = 1;
800
		fallthrough;
801
	case SNDRV_PCM_TRIGGER_STOP:
802
		val = 0;
803
		break;
804
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
805
		val = ICH_IOCE;
806
		break;
807
	default:
808
		return -EINVAL;
809
	}
810
	iputbyte(chip, port + ICH_REG_OFF_CR, val);
811
	if (cmd == SNDRV_PCM_TRIGGER_STOP) {
812
		/* wait until DMA stopped */
813
		while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
814
		/* reset whole DMA things */
815
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
816
	}
817
	return 0;
818
}
819

820
static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
821
{
822
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
823
	struct ichdev *ichdev = get_ichdev(substream);
824
	unsigned long port = ichdev->reg_offset;
825
	static const int fiforeg[] = {
826
		ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
827
	};
828
	unsigned int val, fifo;
829

830
	val = igetdword(chip, ICHREG(ALI_DMACR));
831
	switch (cmd) {
832
	case SNDRV_PCM_TRIGGER_RESUME:
833
		ichdev->suspended = 0;
834
		fallthrough;
835
	case SNDRV_PCM_TRIGGER_START:
836
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
837
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
838
			/* clear FIFO for synchronization of channels */
839
			fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
840
			fifo &= ~(0xff << (ichdev->ali_slot % 4));  
841
			fifo |= 0x83 << (ichdev->ali_slot % 4); 
842
			iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
843
		}
844
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
845
		val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
846
		/* start DMA */
847
		iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
848
		break;
849
	case SNDRV_PCM_TRIGGER_SUSPEND:
850
		ichdev->suspended = 1;
851
		fallthrough;
852
	case SNDRV_PCM_TRIGGER_STOP:
853
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
854
		/* pause */
855
		iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
856
		iputbyte(chip, port + ICH_REG_OFF_CR, 0);
857
		while (igetbyte(chip, port + ICH_REG_OFF_CR))
858
			;
859
		if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
860
			break;
861
		/* reset whole DMA things */
862
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
863
		/* clear interrupts */
864
		iputbyte(chip, port + ICH_REG_OFF_SR,
865
			 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
866
		iputdword(chip, ICHREG(ALI_INTERRUPTSR),
867
			  igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
868
		break;
869
	default:
870
		return -EINVAL;
871
	}
872
	return 0;
873
}
874

875
static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
876
				  struct snd_pcm_hw_params *hw_params)
877
{
878
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
879
	struct ichdev *ichdev = get_ichdev(substream);
880
	int dbl = params_rate(hw_params) > 48000;
881
	int err;
882

883
	if (ichdev->pcm_open_flag) {
884
		snd_ac97_pcm_close(ichdev->pcm);
885
		ichdev->pcm_open_flag = 0;
886
		ichdev->prepared = 0;
887
	}
888
	err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
889
				params_channels(hw_params),
890
				ichdev->pcm->r[dbl].slots);
891
	if (err >= 0) {
892
		ichdev->pcm_open_flag = 1;
893
		/* Force SPDIF setting */
894
		if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
895
			snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
896
					  params_rate(hw_params));
897
	}
898
	return err;
899
}
900

901
static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
902
{
903
	struct ichdev *ichdev = get_ichdev(substream);
904

905
	if (ichdev->pcm_open_flag) {
906
		snd_ac97_pcm_close(ichdev->pcm);
907
		ichdev->pcm_open_flag = 0;
908
		ichdev->prepared = 0;
909
	}
910
	return 0;
911
}
912

913
static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
914
				       struct snd_pcm_runtime *runtime)
915
{
916
	unsigned int cnt;
917
	int dbl = runtime->rate > 48000;
918

919
	guard(spinlock_irq)(&chip->reg_lock);
920
	switch (chip->device_type) {
921
	case DEVICE_ALI:
922
		cnt = igetdword(chip, ICHREG(ALI_SCR));
923
		cnt &= ~ICH_ALI_SC_PCM_246_MASK;
924
		if (runtime->channels == 4 || dbl)
925
			cnt |= ICH_ALI_SC_PCM_4;
926
		else if (runtime->channels == 6)
927
			cnt |= ICH_ALI_SC_PCM_6;
928
		iputdword(chip, ICHREG(ALI_SCR), cnt);
929
		break;
930
	case DEVICE_SIS:
931
		cnt = igetdword(chip, ICHREG(GLOB_CNT));
932
		cnt &= ~ICH_SIS_PCM_246_MASK;
933
		if (runtime->channels == 4 || dbl)
934
			cnt |= ICH_SIS_PCM_4;
935
		else if (runtime->channels == 6)
936
			cnt |= ICH_SIS_PCM_6;
937
		iputdword(chip, ICHREG(GLOB_CNT), cnt);
938
		break;
939
	default:
940
		cnt = igetdword(chip, ICHREG(GLOB_CNT));
941
		cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
942
		if (runtime->channels == 4 || dbl)
943
			cnt |= ICH_PCM_4;
944
		else if (runtime->channels == 6)
945
			cnt |= ICH_PCM_6;
946
		else if (runtime->channels == 8)
947
			cnt |= ICH_PCM_8;
948
		if (chip->device_type == DEVICE_NFORCE) {
949
			/* reset to 2ch once to keep the 6 channel data in alignment,
950
			 * to start from Front Left always
951
			 */
952
			if (cnt & ICH_PCM_246_MASK) {
953
				iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
954
				spin_unlock_irq(&chip->reg_lock);
955
				msleep(50); /* grrr... */
956
				spin_lock_irq(&chip->reg_lock);
957
			}
958
		} else if (chip->device_type == DEVICE_INTEL_ICH4) {
959
			if (runtime->sample_bits > 16)
960
				cnt |= ICH_PCM_20BIT;
961
		}
962
		iputdword(chip, ICHREG(GLOB_CNT), cnt);
963
		break;
964
	}
965
}
966

967
static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
968
{
969
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
970
	struct snd_pcm_runtime *runtime = substream->runtime;
971
	struct ichdev *ichdev = get_ichdev(substream);
972

973
	ichdev->physbuf = runtime->dma_addr;
974
	ichdev->size = snd_pcm_lib_buffer_bytes(substream);
975
	ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
976
	if (ichdev->ichd == ICHD_PCMOUT) {
977
		snd_intel8x0_setup_pcm_out(chip, runtime);
978
		if (chip->device_type == DEVICE_INTEL_ICH4)
979
			ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
980
	}
981
	snd_intel8x0_setup_periods(chip, ichdev);
982
	ichdev->prepared = 1;
983
	return 0;
984
}
985

986
static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
987
{
988
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
989
	struct ichdev *ichdev = get_ichdev(substream);
990
	size_t ptr1, ptr;
991
	int civ, timeout = 10;
992
	unsigned int position;
993

994
	guard(spinlock)(&chip->reg_lock);
995
	do {
996
		civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
997
		ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
998
		position = ichdev->position;
999
		if (ptr1 == 0) {
1000
			udelay(10);
1001
			continue;
1002
		}
1003
		if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1004
			continue;
1005

1006
		/* IO read operation is very expensive inside virtual machine
1007
		 * as it is emulated. The probability that subsequent PICB read
1008
		 * will return different result is high enough to loop till
1009
		 * timeout here.
1010
		 * Same CIV is strict enough condition to be sure that PICB
1011
		 * is valid inside VM on emulated card. */
1012
		if (chip->inside_vm)
1013
			break;
1014
		if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1015
			break;
1016
	} while (timeout--);
1017
	ptr = ichdev->last_pos;
1018
	if (ptr1 != 0) {
1019
		ptr1 <<= ichdev->pos_shift;
1020
		ptr = ichdev->fragsize1 - ptr1;
1021
		ptr += position;
1022
		if (ptr < ichdev->last_pos) {
1023
			unsigned int pos_base, last_base;
1024
			pos_base = position / ichdev->fragsize1;
1025
			last_base = ichdev->last_pos / ichdev->fragsize1;
1026
			/* another sanity check; ptr1 can go back to full
1027
			 * before the base position is updated
1028
			 */
1029
			if (pos_base == last_base)
1030
				ptr = ichdev->last_pos;
1031
		}
1032
	}
1033
	ichdev->last_pos = ptr;
1034
	if (ptr >= ichdev->size)
1035
		return 0;
1036
	return bytes_to_frames(substream->runtime, ptr);
1037
}
1038

1039
static const struct snd_pcm_hardware snd_intel8x0_stream =
1040
{
1041
	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1042
				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1043
				 SNDRV_PCM_INFO_MMAP_VALID |
1044
				 SNDRV_PCM_INFO_PAUSE |
1045
				 SNDRV_PCM_INFO_RESUME),
1046
	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
1047
	.rates =		SNDRV_PCM_RATE_48000,
1048
	.rate_min =		48000,
1049
	.rate_max =		48000,
1050
	.channels_min =		2,
1051
	.channels_max =		2,
1052
	.buffer_bytes_max =	128 * 1024,
1053
	.period_bytes_min =	32,
1054
	.period_bytes_max =	128 * 1024,
1055
	.periods_min =		1,
1056
	.periods_max =		1024,
1057
	.fifo_size =		0,
1058
};
1059

1060
static const unsigned int channels4[] = {
1061
	2, 4,
1062
};
1063

1064
static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1065
	.count = ARRAY_SIZE(channels4),
1066
	.list = channels4,
1067
	.mask = 0,
1068
};
1069

1070
static const unsigned int channels6[] = {
1071
	2, 4, 6,
1072
};
1073

1074
static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1075
	.count = ARRAY_SIZE(channels6),
1076
	.list = channels6,
1077
	.mask = 0,
1078
};
1079

1080
static const unsigned int channels8[] = {
1081
	2, 4, 6, 8,
1082
};
1083

1084
static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1085
	.count = ARRAY_SIZE(channels8),
1086
	.list = channels8,
1087
	.mask = 0,
1088
};
1089

1090
static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1091
{
1092
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1093
	struct snd_pcm_runtime *runtime = substream->runtime;
1094
	int err;
1095

1096
	ichdev->substream = substream;
1097
	runtime->hw = snd_intel8x0_stream;
1098
	runtime->hw.rates = ichdev->pcm->rates;
1099
	snd_pcm_limit_hw_rates(runtime);
1100
	if (chip->device_type == DEVICE_SIS) {
1101
		runtime->hw.buffer_bytes_max = 64*1024;
1102
		runtime->hw.period_bytes_max = 64*1024;
1103
	}
1104
	err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1105
	if (err < 0)
1106
		return err;
1107
	runtime->private_data = ichdev;
1108
	return 0;
1109
}
1110

1111
static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1112
{
1113
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1114
	struct snd_pcm_runtime *runtime = substream->runtime;
1115
	int err;
1116

1117
	err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1118
	if (err < 0)
1119
		return err;
1120

1121
	if (chip->multi8) {
1122
		runtime->hw.channels_max = 8;
1123
		snd_pcm_hw_constraint_list(runtime, 0,
1124
						SNDRV_PCM_HW_PARAM_CHANNELS,
1125
						&hw_constraints_channels8);
1126
	} else if (chip->multi6) {
1127
		runtime->hw.channels_max = 6;
1128
		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1129
					   &hw_constraints_channels6);
1130
	} else if (chip->multi4) {
1131
		runtime->hw.channels_max = 4;
1132
		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1133
					   &hw_constraints_channels4);
1134
	}
1135
	if (chip->dra) {
1136
		snd_ac97_pcm_double_rate_rules(runtime);
1137
	}
1138
	if (chip->smp20bit) {
1139
		runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1140
		snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1141
	}
1142
	return 0;
1143
}
1144

1145
static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1146
{
1147
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1148

1149
	chip->ichd[ICHD_PCMOUT].substream = NULL;
1150
	return 0;
1151
}
1152

1153
static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1154
{
1155
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1156

1157
	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1158
}
1159

1160
static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1161
{
1162
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1163

1164
	chip->ichd[ICHD_PCMIN].substream = NULL;
1165
	return 0;
1166
}
1167

1168
static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1169
{
1170
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1171

1172
	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1173
}
1174

1175
static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1176
{
1177
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1178

1179
	chip->ichd[ICHD_MIC].substream = NULL;
1180
	return 0;
1181
}
1182

1183
static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1184
{
1185
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1186

1187
	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1188
}
1189

1190
static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1191
{
1192
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1193

1194
	chip->ichd[ICHD_MIC2].substream = NULL;
1195
	return 0;
1196
}
1197

1198
static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1199
{
1200
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1201

1202
	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1203
}
1204

1205
static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1206
{
1207
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1208

1209
	chip->ichd[ICHD_PCM2IN].substream = NULL;
1210
	return 0;
1211
}
1212

1213
static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1214
{
1215
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1216
	int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1217

1218
	return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1219
}
1220

1221
static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1222
{
1223
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1224
	int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1225

1226
	chip->ichd[idx].substream = NULL;
1227
	return 0;
1228
}
1229

1230
static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1231
{
1232
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1233
	unsigned int val;
1234

1235
	scoped_guard(spinlock_irq, &chip->reg_lock) {
1236
		val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1237
		val |= ICH_ALI_IF_AC97SP;
1238
		iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1239
		/* also needs to set ALI_SC_CODEC_SPDF correctly */
1240
	}
1241

1242
	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1243
}
1244

1245
static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1246
{
1247
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1248
	unsigned int val;
1249

1250
	chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1251
	guard(spinlock_irq)(&chip->reg_lock);
1252
	val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1253
	val &= ~ICH_ALI_IF_AC97SP;
1254
	iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1255

1256
	return 0;
1257
}
1258

1259
#if 0 // NYI
1260
static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1261
{
1262
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1263

1264
	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1265
}
1266

1267
static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1268
{
1269
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1270

1271
	chip->ichd[ALID_SPDIFIN].substream = NULL;
1272
	return 0;
1273
}
1274

1275
static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1276
{
1277
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1278

1279
	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1280
}
1281

1282
static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1283
{
1284
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1285

1286
	chip->ichd[ALID_SPDIFOUT].substream = NULL;
1287
	return 0;
1288
}
1289
#endif
1290

1291
static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1292
	.open =		snd_intel8x0_playback_open,
1293
	.close =	snd_intel8x0_playback_close,
1294
	.hw_params =	snd_intel8x0_hw_params,
1295
	.hw_free =	snd_intel8x0_hw_free,
1296
	.prepare =	snd_intel8x0_pcm_prepare,
1297
	.trigger =	snd_intel8x0_pcm_trigger,
1298
	.pointer =	snd_intel8x0_pcm_pointer,
1299
};
1300

1301
static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1302
	.open =		snd_intel8x0_capture_open,
1303
	.close =	snd_intel8x0_capture_close,
1304
	.hw_params =	snd_intel8x0_hw_params,
1305
	.hw_free =	snd_intel8x0_hw_free,
1306
	.prepare =	snd_intel8x0_pcm_prepare,
1307
	.trigger =	snd_intel8x0_pcm_trigger,
1308
	.pointer =	snd_intel8x0_pcm_pointer,
1309
};
1310

1311
static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1312
	.open =		snd_intel8x0_mic_open,
1313
	.close =	snd_intel8x0_mic_close,
1314
	.hw_params =	snd_intel8x0_hw_params,
1315
	.hw_free =	snd_intel8x0_hw_free,
1316
	.prepare =	snd_intel8x0_pcm_prepare,
1317
	.trigger =	snd_intel8x0_pcm_trigger,
1318
	.pointer =	snd_intel8x0_pcm_pointer,
1319
};
1320

1321
static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1322
	.open =		snd_intel8x0_mic2_open,
1323
	.close =	snd_intel8x0_mic2_close,
1324
	.hw_params =	snd_intel8x0_hw_params,
1325
	.hw_free =	snd_intel8x0_hw_free,
1326
	.prepare =	snd_intel8x0_pcm_prepare,
1327
	.trigger =	snd_intel8x0_pcm_trigger,
1328
	.pointer =	snd_intel8x0_pcm_pointer,
1329
};
1330

1331
static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1332
	.open =		snd_intel8x0_capture2_open,
1333
	.close =	snd_intel8x0_capture2_close,
1334
	.hw_params =	snd_intel8x0_hw_params,
1335
	.hw_free =	snd_intel8x0_hw_free,
1336
	.prepare =	snd_intel8x0_pcm_prepare,
1337
	.trigger =	snd_intel8x0_pcm_trigger,
1338
	.pointer =	snd_intel8x0_pcm_pointer,
1339
};
1340

1341
static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1342
	.open =		snd_intel8x0_spdif_open,
1343
	.close =	snd_intel8x0_spdif_close,
1344
	.hw_params =	snd_intel8x0_hw_params,
1345
	.hw_free =	snd_intel8x0_hw_free,
1346
	.prepare =	snd_intel8x0_pcm_prepare,
1347
	.trigger =	snd_intel8x0_pcm_trigger,
1348
	.pointer =	snd_intel8x0_pcm_pointer,
1349
};
1350

1351
static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1352
	.open =		snd_intel8x0_playback_open,
1353
	.close =	snd_intel8x0_playback_close,
1354
	.hw_params =	snd_intel8x0_hw_params,
1355
	.hw_free =	snd_intel8x0_hw_free,
1356
	.prepare =	snd_intel8x0_pcm_prepare,
1357
	.trigger =	snd_intel8x0_ali_trigger,
1358
	.pointer =	snd_intel8x0_pcm_pointer,
1359
};
1360

1361
static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1362
	.open =		snd_intel8x0_capture_open,
1363
	.close =	snd_intel8x0_capture_close,
1364
	.hw_params =	snd_intel8x0_hw_params,
1365
	.hw_free =	snd_intel8x0_hw_free,
1366
	.prepare =	snd_intel8x0_pcm_prepare,
1367
	.trigger =	snd_intel8x0_ali_trigger,
1368
	.pointer =	snd_intel8x0_pcm_pointer,
1369
};
1370

1371
static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1372
	.open =		snd_intel8x0_mic_open,
1373
	.close =	snd_intel8x0_mic_close,
1374
	.hw_params =	snd_intel8x0_hw_params,
1375
	.hw_free =	snd_intel8x0_hw_free,
1376
	.prepare =	snd_intel8x0_pcm_prepare,
1377
	.trigger =	snd_intel8x0_ali_trigger,
1378
	.pointer =	snd_intel8x0_pcm_pointer,
1379
};
1380

1381
static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1382
	.open =		snd_intel8x0_ali_ac97spdifout_open,
1383
	.close =	snd_intel8x0_ali_ac97spdifout_close,
1384
	.hw_params =	snd_intel8x0_hw_params,
1385
	.hw_free =	snd_intel8x0_hw_free,
1386
	.prepare =	snd_intel8x0_pcm_prepare,
1387
	.trigger =	snd_intel8x0_ali_trigger,
1388
	.pointer =	snd_intel8x0_pcm_pointer,
1389
};
1390

1391
#if 0 // NYI
1392
static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1393
	.open =		snd_intel8x0_ali_spdifin_open,
1394
	.close =	snd_intel8x0_ali_spdifin_close,
1395
	.hw_params =	snd_intel8x0_hw_params,
1396
	.hw_free =	snd_intel8x0_hw_free,
1397
	.prepare =	snd_intel8x0_pcm_prepare,
1398
	.trigger =	snd_intel8x0_pcm_trigger,
1399
	.pointer =	snd_intel8x0_pcm_pointer,
1400
};
1401

1402
static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1403
	.open =		snd_intel8x0_ali_spdifout_open,
1404
	.close =	snd_intel8x0_ali_spdifout_close,
1405
	.hw_params =	snd_intel8x0_hw_params,
1406
	.hw_free =	snd_intel8x0_hw_free,
1407
	.prepare =	snd_intel8x0_pcm_prepare,
1408
	.trigger =	snd_intel8x0_pcm_trigger,
1409
	.pointer =	snd_intel8x0_pcm_pointer,
1410
};
1411
#endif // NYI
1412

1413
struct ich_pcm_table {
1414
	char *suffix;
1415
	const struct snd_pcm_ops *playback_ops;
1416
	const struct snd_pcm_ops *capture_ops;
1417
	size_t prealloc_size;
1418
	size_t prealloc_max_size;
1419
	int ac97_idx;
1420
};
1421

1422
#define intel8x0_dma_type(chip) \
1423
	((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_WC : SNDRV_DMA_TYPE_DEV)
1424

1425
static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1426
			     const struct ich_pcm_table *rec)
1427
{
1428
	struct snd_pcm *pcm;
1429
	int err;
1430
	char name[32];
1431

1432
	if (rec->suffix)
1433
		sprintf(name, "Intel ICH - %s", rec->suffix);
1434
	else
1435
		strscpy(name, "Intel ICH");
1436
	err = snd_pcm_new(chip->card, name, device,
1437
			  rec->playback_ops ? 1 : 0,
1438
			  rec->capture_ops ? 1 : 0, &pcm);
1439
	if (err < 0)
1440
		return err;
1441

1442
	if (rec->playback_ops)
1443
		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1444
	if (rec->capture_ops)
1445
		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1446

1447
	pcm->private_data = chip;
1448
	pcm->info_flags = 0;
1449
	if (rec->suffix)
1450
		sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1451
	else
1452
		strscpy(pcm->name, chip->card->shortname);
1453
	chip->pcm[device] = pcm;
1454

1455
	snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
1456
				       &chip->pci->dev,
1457
				       rec->prealloc_size, rec->prealloc_max_size);
1458

1459
	if (rec->playback_ops &&
1460
	    rec->playback_ops->open == snd_intel8x0_playback_open) {
1461
		struct snd_pcm_chmap *chmap;
1462
		int chs = 2;
1463
		if (chip->multi8)
1464
			chs = 8;
1465
		else if (chip->multi6)
1466
			chs = 6;
1467
		else if (chip->multi4)
1468
			chs = 4;
1469
		err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1470
					     snd_pcm_alt_chmaps, chs, 0,
1471
					     &chmap);
1472
		if (err < 0)
1473
			return err;
1474
		chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1475
		chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1476
	}
1477

1478
	return 0;
1479
}
1480

1481
static const struct ich_pcm_table intel_pcms[] = {
1482
	{
1483
		.playback_ops = &snd_intel8x0_playback_ops,
1484
		.capture_ops = &snd_intel8x0_capture_ops,
1485
		.prealloc_size = 64 * 1024,
1486
		.prealloc_max_size = 128 * 1024,
1487
	},
1488
	{
1489
		.suffix = "MIC ADC",
1490
		.capture_ops = &snd_intel8x0_capture_mic_ops,
1491
		.prealloc_size = 0,
1492
		.prealloc_max_size = 128 * 1024,
1493
		.ac97_idx = ICHD_MIC,
1494
	},
1495
	{
1496
		.suffix = "MIC2 ADC",
1497
		.capture_ops = &snd_intel8x0_capture_mic2_ops,
1498
		.prealloc_size = 0,
1499
		.prealloc_max_size = 128 * 1024,
1500
		.ac97_idx = ICHD_MIC2,
1501
	},
1502
	{
1503
		.suffix = "ADC2",
1504
		.capture_ops = &snd_intel8x0_capture2_ops,
1505
		.prealloc_size = 0,
1506
		.prealloc_max_size = 128 * 1024,
1507
		.ac97_idx = ICHD_PCM2IN,
1508
	},
1509
	{
1510
		.suffix = "IEC958",
1511
		.playback_ops = &snd_intel8x0_spdif_ops,
1512
		.prealloc_size = 64 * 1024,
1513
		.prealloc_max_size = 128 * 1024,
1514
		.ac97_idx = ICHD_SPBAR,
1515
	},
1516
};
1517

1518
static const struct ich_pcm_table nforce_pcms[] = {
1519
	{
1520
		.playback_ops = &snd_intel8x0_playback_ops,
1521
		.capture_ops = &snd_intel8x0_capture_ops,
1522
		.prealloc_size = 64 * 1024,
1523
		.prealloc_max_size = 128 * 1024,
1524
	},
1525
	{
1526
		.suffix = "MIC ADC",
1527
		.capture_ops = &snd_intel8x0_capture_mic_ops,
1528
		.prealloc_size = 0,
1529
		.prealloc_max_size = 128 * 1024,
1530
		.ac97_idx = NVD_MIC,
1531
	},
1532
	{
1533
		.suffix = "IEC958",
1534
		.playback_ops = &snd_intel8x0_spdif_ops,
1535
		.prealloc_size = 64 * 1024,
1536
		.prealloc_max_size = 128 * 1024,
1537
		.ac97_idx = NVD_SPBAR,
1538
	},
1539
};
1540

1541
static const struct ich_pcm_table ali_pcms[] = {
1542
	{
1543
		.playback_ops = &snd_intel8x0_ali_playback_ops,
1544
		.capture_ops = &snd_intel8x0_ali_capture_ops,
1545
		.prealloc_size = 64 * 1024,
1546
		.prealloc_max_size = 128 * 1024,
1547
	},
1548
	{
1549
		.suffix = "MIC ADC",
1550
		.capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1551
		.prealloc_size = 0,
1552
		.prealloc_max_size = 128 * 1024,
1553
		.ac97_idx = ALID_MIC,
1554
	},
1555
	{
1556
		.suffix = "IEC958",
1557
		.playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1558
		/* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1559
		.prealloc_size = 64 * 1024,
1560
		.prealloc_max_size = 128 * 1024,
1561
		.ac97_idx = ALID_AC97SPDIFOUT,
1562
	},
1563
#if 0 // NYI
1564
	{
1565
		.suffix = "HW IEC958",
1566
		.playback_ops = &snd_intel8x0_ali_spdifout_ops,
1567
		.prealloc_size = 64 * 1024,
1568
		.prealloc_max_size = 128 * 1024,
1569
	},
1570
#endif
1571
};
1572

1573
static int snd_intel8x0_pcm(struct intel8x0 *chip)
1574
{
1575
	int i, tblsize, device, err;
1576
	const struct ich_pcm_table *tbl, *rec;
1577

1578
	switch (chip->device_type) {
1579
	case DEVICE_INTEL_ICH4:
1580
		tbl = intel_pcms;
1581
		tblsize = ARRAY_SIZE(intel_pcms);
1582
		if (spdif_aclink)
1583
			tblsize--;
1584
		break;
1585
	case DEVICE_NFORCE:
1586
		tbl = nforce_pcms;
1587
		tblsize = ARRAY_SIZE(nforce_pcms);
1588
		if (spdif_aclink)
1589
			tblsize--;
1590
		break;
1591
	case DEVICE_ALI:
1592
		tbl = ali_pcms;
1593
		tblsize = ARRAY_SIZE(ali_pcms);
1594
		break;
1595
	default:
1596
		tbl = intel_pcms;
1597
		tblsize = 2;
1598
		break;
1599
	}
1600

1601
	device = 0;
1602
	for (i = 0; i < tblsize; i++) {
1603
		rec = tbl + i;
1604
		if (i > 0 && rec->ac97_idx) {
1605
			/* activate PCM only when associated AC'97 codec */
1606
			if (! chip->ichd[rec->ac97_idx].pcm)
1607
				continue;
1608
		}
1609
		err = snd_intel8x0_pcm1(chip, device, rec);
1610
		if (err < 0)
1611
			return err;
1612
		device++;
1613
	}
1614

1615
	chip->pcm_devs = device;
1616
	return 0;
1617
}
1618
	
1619

1620
/*
1621
 *  Mixer part
1622
 */
1623

1624
static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1625
{
1626
	struct intel8x0 *chip = bus->private_data;
1627
	chip->ac97_bus = NULL;
1628
}
1629

1630
static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1631
{
1632
	struct intel8x0 *chip = ac97->private_data;
1633
	chip->ac97[ac97->num] = NULL;
1634
}
1635

1636
static const struct ac97_pcm ac97_pcm_defs[] = {
1637
	/* front PCM */
1638
	{
1639
		.exclusive = 1,
1640
		.r = {	{
1641
				.slots = (1 << AC97_SLOT_PCM_LEFT) |
1642
					 (1 << AC97_SLOT_PCM_RIGHT) |
1643
					 (1 << AC97_SLOT_PCM_CENTER) |
1644
					 (1 << AC97_SLOT_PCM_SLEFT) |
1645
					 (1 << AC97_SLOT_PCM_SRIGHT) |
1646
					 (1 << AC97_SLOT_LFE)
1647
			},
1648
			{
1649
				.slots = (1 << AC97_SLOT_PCM_LEFT) |
1650
					 (1 << AC97_SLOT_PCM_RIGHT) |
1651
					 (1 << AC97_SLOT_PCM_LEFT_0) |
1652
					 (1 << AC97_SLOT_PCM_RIGHT_0)
1653
			}
1654
		}
1655
	},
1656
	/* PCM IN #1 */
1657
	{
1658
		.stream = 1,
1659
		.exclusive = 1,
1660
		.r = {	{
1661
				.slots = (1 << AC97_SLOT_PCM_LEFT) |
1662
					 (1 << AC97_SLOT_PCM_RIGHT)
1663
			}
1664
		}
1665
	},
1666
	/* MIC IN #1 */
1667
	{
1668
		.stream = 1,
1669
		.exclusive = 1,
1670
		.r = {	{
1671
				.slots = (1 << AC97_SLOT_MIC)
1672
			}
1673
		}
1674
	},
1675
	/* S/PDIF PCM */
1676
	{
1677
		.exclusive = 1,
1678
		.spdif = 1,
1679
		.r = {	{
1680
				.slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1681
					 (1 << AC97_SLOT_SPDIF_RIGHT2)
1682
			}
1683
		}
1684
	},
1685
	/* PCM IN #2 */
1686
	{
1687
		.stream = 1,
1688
		.exclusive = 1,
1689
		.r = {	{
1690
				.slots = (1 << AC97_SLOT_PCM_LEFT) |
1691
					 (1 << AC97_SLOT_PCM_RIGHT)
1692
			}
1693
		}
1694
	},
1695
	/* MIC IN #2 */
1696
	{
1697
		.stream = 1,
1698
		.exclusive = 1,
1699
		.r = {	{
1700
				.slots = (1 << AC97_SLOT_MIC)
1701
			}
1702
		}
1703
	},
1704
};
1705

1706
static const struct ac97_quirk ac97_quirks[] = {
1707
        {
1708
		.subvendor = 0x0e11,
1709
		.subdevice = 0x000e,
1710
		.name = "Compaq Deskpro EN",	/* AD1885 */
1711
		.type = AC97_TUNE_HP_ONLY
1712
        },
1713
	{
1714
		.subvendor = 0x0e11,
1715
		.subdevice = 0x008a,
1716
		.name = "Compaq Evo W4000",	/* AD1885 */
1717
		.type = AC97_TUNE_HP_ONLY
1718
	},
1719
	{
1720
		.subvendor = 0x0e11,
1721
		.subdevice = 0x00b8,
1722
		.name = "Compaq Evo D510C",
1723
		.type = AC97_TUNE_HP_ONLY
1724
	},
1725
        {
1726
		.subvendor = 0x0e11,
1727
		.subdevice = 0x0860,
1728
		.name = "HP/Compaq nx7010",
1729
		.type = AC97_TUNE_MUTE_LED
1730
        },
1731
	{
1732
		.subvendor = 0x1014,
1733
		.subdevice = 0x0534,
1734
		.name = "ThinkPad X31",
1735
		.type = AC97_TUNE_INV_EAPD
1736
	},
1737
	{
1738
		.subvendor = 0x1014,
1739
		.subdevice = 0x1f00,
1740
		.name = "MS-9128",
1741
		.type = AC97_TUNE_ALC_JACK
1742
	},
1743
	{
1744
		.subvendor = 0x1014,
1745
		.subdevice = 0x0267,
1746
		.name = "IBM NetVista A30p",	/* AD1981B */
1747
		.type = AC97_TUNE_HP_ONLY
1748
	},
1749
	{
1750
		.subvendor = 0x1025,
1751
		.subdevice = 0x0082,
1752
		.name = "Acer Travelmate 2310",
1753
		.type = AC97_TUNE_HP_ONLY
1754
	},
1755
	{
1756
		.subvendor = 0x1025,
1757
		.subdevice = 0x0083,
1758
		.name = "Acer Aspire 3003LCi",
1759
		.type = AC97_TUNE_HP_ONLY
1760
	},
1761
	{
1762
		.subvendor = 0x1028,
1763
		.subdevice = 0x00d8,
1764
		.name = "Dell Precision 530",	/* AD1885 */
1765
		.type = AC97_TUNE_HP_ONLY
1766
	},
1767
	{
1768
		.subvendor = 0x1028,
1769
		.subdevice = 0x010d,
1770
		.name = "Dell",	/* which model?  AD1885 */
1771
		.type = AC97_TUNE_HP_ONLY
1772
	},
1773
	{
1774
		.subvendor = 0x1028,
1775
		.subdevice = 0x0126,
1776
		.name = "Dell Optiplex GX260",	/* AD1981A */
1777
		.type = AC97_TUNE_HP_ONLY
1778
	},
1779
	{
1780
		.subvendor = 0x1028,
1781
		.subdevice = 0x012c,
1782
		.name = "Dell Precision 650",	/* AD1981A */
1783
		.type = AC97_TUNE_HP_ONLY
1784
	},
1785
	{
1786
		.subvendor = 0x1028,
1787
		.subdevice = 0x012d,
1788
		.name = "Dell Precision 450",	/* AD1981B*/
1789
		.type = AC97_TUNE_HP_ONLY
1790
	},
1791
	{
1792
		.subvendor = 0x1028,
1793
		.subdevice = 0x0147,
1794
		.name = "Dell",	/* which model?  AD1981B*/
1795
		.type = AC97_TUNE_HP_ONLY
1796
	},
1797
	{
1798
		.subvendor = 0x1028,
1799
		.subdevice = 0x0151,
1800
		.name = "Dell Optiplex GX270",  /* AD1981B */
1801
		.type = AC97_TUNE_HP_ONLY
1802
	},
1803
	{
1804
		.subvendor = 0x1028,
1805
		.subdevice = 0x014e,
1806
		.name = "Dell D800", /* STAC9750/51 */
1807
		.type = AC97_TUNE_HP_ONLY
1808
	},
1809
	{
1810
		.subvendor = 0x1028,
1811
		.subdevice = 0x0163,
1812
		.name = "Dell Unknown",	/* STAC9750/51 */
1813
		.type = AC97_TUNE_HP_ONLY
1814
	},
1815
	{
1816
		.subvendor = 0x1028,
1817
		.subdevice = 0x016a,
1818
		.name = "Dell Inspiron 8600",	/* STAC9750/51 */
1819
		.type = AC97_TUNE_HP_ONLY
1820
	},
1821
	{
1822
		.subvendor = 0x1028,
1823
		.subdevice = 0x0182,
1824
		.name = "Dell Latitude D610",	/* STAC9750/51 */
1825
		.type = AC97_TUNE_HP_ONLY
1826
	},
1827
	{
1828
		.subvendor = 0x1028,
1829
		.subdevice = 0x0186,
1830
		.name = "Dell Latitude D810", /* cf. Malone #41015 */
1831
		.type = AC97_TUNE_HP_MUTE_LED
1832
	},
1833
	{
1834
		.subvendor = 0x1028,
1835
		.subdevice = 0x0188,
1836
		.name = "Dell Inspiron 6000",
1837
		.type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1838
	},
1839
	{
1840
		.subvendor = 0x1028,
1841
		.subdevice = 0x0189,
1842
		.name = "Dell Inspiron 9300",
1843
		.type = AC97_TUNE_HP_MUTE_LED
1844
	},
1845
	{
1846
		.subvendor = 0x1028,
1847
		.subdevice = 0x0191,
1848
		.name = "Dell Inspiron 8600",
1849
		.type = AC97_TUNE_HP_ONLY
1850
	},
1851
	{
1852
		.subvendor = 0x103c,
1853
		.subdevice = 0x006d,
1854
		.name = "HP zv5000",
1855
		.type = AC97_TUNE_MUTE_LED	/*AD1981B*/
1856
	},
1857
	{	/* FIXME: which codec? */
1858
		.subvendor = 0x103c,
1859
		.subdevice = 0x00c3,
1860
		.name = "HP xw6000",
1861
		.type = AC97_TUNE_HP_ONLY
1862
	},
1863
	{
1864
		.subvendor = 0x103c,
1865
		.subdevice = 0x088c,
1866
		.name = "HP nc8000",
1867
		.type = AC97_TUNE_HP_MUTE_LED
1868
	},
1869
	{
1870
		.subvendor = 0x103c,
1871
		.subdevice = 0x0890,
1872
		.name = "HP nc6000",
1873
		.type = AC97_TUNE_MUTE_LED
1874
	},
1875
	{
1876
		.subvendor = 0x103c,
1877
		.subdevice = 0x129d,
1878
		.name = "HP xw8000",
1879
		.type = AC97_TUNE_HP_ONLY
1880
	},
1881
	{
1882
		.subvendor = 0x103c,
1883
		.subdevice = 0x0938,
1884
		.name = "HP nc4200",
1885
		.type = AC97_TUNE_HP_MUTE_LED
1886
	},
1887
	{
1888
		.subvendor = 0x103c,
1889
		.subdevice = 0x099c,
1890
		.name = "HP nx6110/nc6120",
1891
		.type = AC97_TUNE_HP_MUTE_LED
1892
	},
1893
	{
1894
		.subvendor = 0x103c,
1895
		.subdevice = 0x0944,
1896
		.name = "HP nc6220",
1897
		.type = AC97_TUNE_HP_MUTE_LED
1898
	},
1899
	{
1900
		.subvendor = 0x103c,
1901
		.subdevice = 0x0934,
1902
		.name = "HP nc8220",
1903
		.type = AC97_TUNE_HP_MUTE_LED
1904
	},
1905
	{
1906
		.subvendor = 0x103c,
1907
		.subdevice = 0x12f1,
1908
		.name = "HP xw8200",	/* AD1981B*/
1909
		.type = AC97_TUNE_HP_ONLY
1910
	},
1911
	{
1912
		.subvendor = 0x103c,
1913
		.subdevice = 0x12f2,
1914
		.name = "HP xw6200",
1915
		.type = AC97_TUNE_HP_ONLY
1916
	},
1917
	{
1918
		.subvendor = 0x103c,
1919
		.subdevice = 0x3008,
1920
		.name = "HP xw4200",	/* AD1981B*/
1921
		.type = AC97_TUNE_HP_ONLY
1922
	},
1923
	{
1924
		.subvendor = 0x104d,
1925
		.subdevice = 0x8144,
1926
		.name = "Sony",
1927
		.type = AC97_TUNE_INV_EAPD
1928
	},
1929
	{
1930
		.subvendor = 0x104d,
1931
		.subdevice = 0x8197,
1932
		.name = "Sony S1XP",
1933
		.type = AC97_TUNE_INV_EAPD
1934
	},
1935
	{
1936
		.subvendor = 0x104d,
1937
		.subdevice = 0x81c0,
1938
		.name = "Sony VAIO VGN-T350P", /*AD1981B*/
1939
		.type = AC97_TUNE_INV_EAPD
1940
	},
1941
	{
1942
		.subvendor = 0x104d,
1943
		.subdevice = 0x81c5,
1944
		.name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1945
		.type = AC97_TUNE_INV_EAPD
1946
	},
1947
 	{
1948
		.subvendor = 0x1043,
1949
		.subdevice = 0x80f3,
1950
		.name = "ASUS ICH5/AD1985",
1951
		.type = AC97_TUNE_AD_SHARING
1952
	},
1953
	{
1954
		.subvendor = 0x10cf,
1955
		.subdevice = 0x11c3,
1956
		.name = "Fujitsu-Siemens E4010",
1957
		.type = AC97_TUNE_HP_ONLY
1958
	},
1959
	{
1960
		.subvendor = 0x10cf,
1961
		.subdevice = 0x1225,
1962
		.name = "Fujitsu-Siemens T3010",
1963
		.type = AC97_TUNE_HP_ONLY
1964
	},
1965
	{
1966
		.subvendor = 0x10cf,
1967
		.subdevice = 0x1253,
1968
		.name = "Fujitsu S6210",	/* STAC9750/51 */
1969
		.type = AC97_TUNE_HP_ONLY
1970
	},
1971
	{
1972
		.subvendor = 0x10cf,
1973
		.subdevice = 0x127d,
1974
		.name = "Fujitsu Lifebook P7010",
1975
		.type = AC97_TUNE_HP_ONLY
1976
	},
1977
	{
1978
		.subvendor = 0x10cf,
1979
		.subdevice = 0x127e,
1980
		.name = "Fujitsu Lifebook C1211D",
1981
		.type = AC97_TUNE_HP_ONLY
1982
	},
1983
	{
1984
		.subvendor = 0x10cf,
1985
		.subdevice = 0x12ec,
1986
		.name = "Fujitsu-Siemens 4010",
1987
		.type = AC97_TUNE_HP_ONLY
1988
	},
1989
	{
1990
		.subvendor = 0x10cf,
1991
		.subdevice = 0x12f2,
1992
		.name = "Fujitsu-Siemens Celsius H320",
1993
		.type = AC97_TUNE_SWAP_HP
1994
	},
1995
	{
1996
		.subvendor = 0x10f1,
1997
		.subdevice = 0x2665,
1998
		.name = "Fujitsu-Siemens Celsius",	/* AD1981? */
1999
		.type = AC97_TUNE_HP_ONLY
2000
	},
2001
	{
2002
		.subvendor = 0x10f1,
2003
		.subdevice = 0x2885,
2004
		.name = "AMD64 Mobo",	/* ALC650 */
2005
		.type = AC97_TUNE_HP_ONLY
2006
	},
2007
	{
2008
		.subvendor = 0x10f1,
2009
		.subdevice = 0x2895,
2010
		.name = "Tyan Thunder K8WE",
2011
		.type = AC97_TUNE_HP_ONLY
2012
	},
2013
	{
2014
		.subvendor = 0x10f7,
2015
		.subdevice = 0x834c,
2016
		.name = "Panasonic CF-R4",
2017
		.type = AC97_TUNE_HP_ONLY,
2018
	},
2019
	{
2020
		.subvendor = 0x110a,
2021
		.subdevice = 0x0056,
2022
		.name = "Fujitsu-Siemens Scenic",	/* AD1981? */
2023
		.type = AC97_TUNE_HP_ONLY
2024
	},
2025
	{
2026
		.subvendor = 0x11d4,
2027
		.subdevice = 0x5375,
2028
		.name = "ADI AD1985 (discrete)",
2029
		.type = AC97_TUNE_HP_ONLY
2030
	},
2031
	{
2032
		.subvendor = 0x1462,
2033
		.subdevice = 0x5470,
2034
		.name = "MSI P4 ATX 645 Ultra",
2035
		.type = AC97_TUNE_HP_ONLY
2036
	},
2037
	{
2038
		.subvendor = 0x161f,
2039
		.subdevice = 0x202f,
2040
		.name = "Gateway M520",
2041
		.type = AC97_TUNE_INV_EAPD
2042
	},
2043
	{
2044
		.subvendor = 0x161f,
2045
		.subdevice = 0x203a,
2046
		.name = "Gateway 4525GZ",		/* AD1981B */
2047
		.type = AC97_TUNE_INV_EAPD
2048
	},
2049
	{
2050
		.subvendor = 0x1734,
2051
		.subdevice = 0x0088,
2052
		.name = "Fujitsu-Siemens D1522",	/* AD1981 */
2053
		.type = AC97_TUNE_HP_ONLY
2054
	},
2055
	{
2056
		.subvendor = 0x8086,
2057
		.subdevice = 0x2000,
2058
		.mask = 0xfff0,
2059
		.name = "Intel ICH5/AD1985",
2060
		.type = AC97_TUNE_AD_SHARING
2061
	},
2062
	{
2063
		.subvendor = 0x8086,
2064
		.subdevice = 0x4000,
2065
		.mask = 0xfff0,
2066
		.name = "Intel ICH5/AD1985",
2067
		.type = AC97_TUNE_AD_SHARING
2068
	},
2069
	{
2070
		.subvendor = 0x8086,
2071
		.subdevice = 0x4856,
2072
		.name = "Intel D845WN (82801BA)",
2073
		.type = AC97_TUNE_SWAP_HP
2074
	},
2075
	{
2076
		.subvendor = 0x8086,
2077
		.subdevice = 0x4d44,
2078
		.name = "Intel D850EMV2",	/* AD1885 */
2079
		.type = AC97_TUNE_HP_ONLY
2080
	},
2081
	{
2082
		.subvendor = 0x8086,
2083
		.subdevice = 0x4d56,
2084
		.name = "Intel ICH/AD1885",
2085
		.type = AC97_TUNE_HP_ONLY
2086
	},
2087
	{
2088
		.subvendor = 0x8086,
2089
		.subdevice = 0x6000,
2090
		.mask = 0xfff0,
2091
		.name = "Intel ICH5/AD1985",
2092
		.type = AC97_TUNE_AD_SHARING
2093
	},
2094
	{
2095
		.subvendor = 0x8086,
2096
		.subdevice = 0xe000,
2097
		.mask = 0xfff0,
2098
		.name = "Intel ICH5/AD1985",
2099
		.type = AC97_TUNE_AD_SHARING
2100
	},
2101
#if 0 /* FIXME: this seems wrong on most boards */
2102
	{
2103
		.subvendor = 0x8086,
2104
		.subdevice = 0xa000,
2105
		.mask = 0xfff0,
2106
		.name = "Intel ICH5/AD1985",
2107
		.type = AC97_TUNE_HP_ONLY
2108
	},
2109
#endif
2110
	{ } /* terminator */
2111
};
2112

2113
static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2114
			      const char *quirk_override)
2115
{
2116
	struct snd_ac97_bus *pbus;
2117
	struct snd_ac97_template ac97;
2118
	int err;
2119
	unsigned int i, codecs;
2120
	unsigned int glob_sta = 0;
2121
	const struct snd_ac97_bus_ops *ops;
2122
	static const struct snd_ac97_bus_ops standard_bus_ops = {
2123
		.write = snd_intel8x0_codec_write,
2124
		.read = snd_intel8x0_codec_read,
2125
	};
2126
	static const struct snd_ac97_bus_ops ali_bus_ops = {
2127
		.write = snd_intel8x0_ali_codec_write,
2128
		.read = snd_intel8x0_ali_codec_read,
2129
	};
2130

2131
	chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2132
	if (!spdif_aclink) {
2133
		switch (chip->device_type) {
2134
		case DEVICE_NFORCE:
2135
			chip->spdif_idx = NVD_SPBAR;
2136
			break;
2137
		case DEVICE_ALI:
2138
			chip->spdif_idx = ALID_AC97SPDIFOUT;
2139
			break;
2140
		case DEVICE_INTEL_ICH4:
2141
			chip->spdif_idx = ICHD_SPBAR;
2142
			break;
2143
		}
2144
	}
2145

2146
	chip->in_ac97_init = 1;
2147
	
2148
	memset(&ac97, 0, sizeof(ac97));
2149
	ac97.private_data = chip;
2150
	ac97.private_free = snd_intel8x0_mixer_free_ac97;
2151
	ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2152
	if (chip->xbox)
2153
		ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2154
	if (chip->device_type != DEVICE_ALI) {
2155
		glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2156
		ops = &standard_bus_ops;
2157
		chip->in_sdin_init = 1;
2158
		codecs = 0;
2159
		for (i = 0; i < chip->max_codecs; i++) {
2160
			if (! (glob_sta & chip->codec_bit[i]))
2161
				continue;
2162
			if (chip->device_type == DEVICE_INTEL_ICH4) {
2163
				snd_intel8x0_codec_read_test(chip, codecs);
2164
				chip->ac97_sdin[codecs] =
2165
					igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2166
				if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2167
					chip->ac97_sdin[codecs] = 0;
2168
			} else
2169
				chip->ac97_sdin[codecs] = i;
2170
			codecs++;
2171
		}
2172
		chip->in_sdin_init = 0;
2173
		if (! codecs)
2174
			codecs = 1;
2175
	} else {
2176
		ops = &ali_bus_ops;
2177
		codecs = 1;
2178
		/* detect the secondary codec */
2179
		for (i = 0; i < 100; i++) {
2180
			unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2181
			if (reg & 0x40) {
2182
				codecs = 2;
2183
				break;
2184
			}
2185
			iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2186
			udelay(1);
2187
		}
2188
	}
2189
	err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus);
2190
	if (err < 0)
2191
		goto __err;
2192
	pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2193
	if (ac97_clock >= 8000 && ac97_clock <= 48000)
2194
		pbus->clock = ac97_clock;
2195
	/* FIXME: my test board doesn't work well with VRA... */
2196
	if (chip->device_type == DEVICE_ALI)
2197
		pbus->no_vra = 1;
2198
	else
2199
		pbus->dra = 1;
2200
	chip->ac97_bus = pbus;
2201
	chip->ncodecs = codecs;
2202

2203
	ac97.pci = chip->pci;
2204
	for (i = 0; i < codecs; i++) {
2205
		ac97.num = i;
2206
		err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
2207
		if (err < 0) {
2208
			if (err != -EACCES)
2209
				dev_err(chip->card->dev,
2210
					"Unable to initialize codec #%d\n", i);
2211
			if (i == 0)
2212
				goto __err;
2213
		}
2214
	}
2215
	/* tune up the primary codec */
2216
	snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2217
	/* enable separate SDINs for ICH4 */
2218
	if (chip->device_type == DEVICE_INTEL_ICH4)
2219
		pbus->isdin = 1;
2220
	/* find the available PCM streams */
2221
	i = ARRAY_SIZE(ac97_pcm_defs);
2222
	if (chip->device_type != DEVICE_INTEL_ICH4)
2223
		i -= 2;		/* do not allocate PCM2IN and MIC2 */
2224
	if (chip->spdif_idx < 0)
2225
		i--;		/* do not allocate S/PDIF */
2226
	err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2227
	if (err < 0)
2228
		goto __err;
2229
	chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2230
	chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2231
	chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2232
	if (chip->spdif_idx >= 0)
2233
		chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2234
	if (chip->device_type == DEVICE_INTEL_ICH4) {
2235
		chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2236
		chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2237
	}
2238
	/* enable separate SDINs for ICH4 */
2239
	if (chip->device_type == DEVICE_INTEL_ICH4) {
2240
		struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2241
		u8 tmp = igetbyte(chip, ICHREG(SDM));
2242
		tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2243
		if (pcm) {
2244
			tmp |= ICH_SE;	/* steer enable for multiple SDINs */
2245
			tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2246
			for (i = 1; i < 4; i++) {
2247
				if (pcm->r[0].codec[i]) {
2248
					tmp |= chip->ac97_sdin[pcm->r[0].codec[i]->num] << ICH_DI2L_SHIFT;
2249
					break;
2250
				}
2251
			}
2252
		} else {
2253
			tmp &= ~ICH_SE; /* steer disable */
2254
		}
2255
		iputbyte(chip, ICHREG(SDM), tmp);
2256
	}
2257
	if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2258
		chip->multi4 = 1;
2259
		if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2260
			chip->multi6 = 1;
2261
			if (chip->ac97[0]->flags & AC97_HAS_8CH)
2262
				chip->multi8 = 1;
2263
		}
2264
	}
2265
	if (pbus->pcms[0].r[1].rslots[0]) {
2266
		chip->dra = 1;
2267
	}
2268
	if (chip->device_type == DEVICE_INTEL_ICH4) {
2269
		if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2270
			chip->smp20bit = 1;
2271
	}
2272
	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2273
		/* 48kHz only */
2274
		chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2275
	}
2276
	if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2277
		/* use slot 10/11 for SPDIF */
2278
		u32 val;
2279
		val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2280
		val |= ICH_PCM_SPDIF_1011;
2281
		iputdword(chip, ICHREG(GLOB_CNT), val);
2282
		snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2283
	}
2284
	chip->in_ac97_init = 0;
2285
	return 0;
2286

2287
 __err:
2288
	/* clear the cold-reset bit for the next chance */
2289
	if (chip->device_type != DEVICE_ALI)
2290
		iputdword(chip, ICHREG(GLOB_CNT),
2291
			  igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2292
	return err;
2293
}
2294

2295

2296
/*
2297
 *
2298
 */
2299

2300
static void do_ali_reset(struct intel8x0 *chip)
2301
{
2302
	iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2303
	iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2304
	iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2305
	iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2306
	iputdword(chip, ICHREG(ALI_INTERFACECR),
2307
		  ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2308
	iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2309
	iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2310
}
2311

2312
#ifdef CONFIG_SND_AC97_POWER_SAVE
2313
static const struct snd_pci_quirk ich_chip_reset_mode[] = {
2314
	SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2315
	{ } /* end */
2316
};
2317

2318
static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2319
{
2320
	unsigned int cnt;
2321
	/* ACLink on, 2 channels */
2322

2323
	if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2324
		return -EIO;
2325

2326
	cnt = igetdword(chip, ICHREG(GLOB_CNT));
2327
	cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2328

2329
	/* do cold reset - the full ac97 powerdown may leave the controller
2330
	 * in a warm state but actually it cannot communicate with the codec.
2331
	 */
2332
	iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2333
	cnt = igetdword(chip, ICHREG(GLOB_CNT));
2334
	udelay(10);
2335
	iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2336
	msleep(1);
2337
	return 0;
2338
}
2339
#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2340
	(!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2341
#else
2342
#define snd_intel8x0_ich_chip_cold_reset(chip)	0
2343
#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2344
#endif
2345

2346
static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2347
{
2348
	unsigned long end_time;
2349
	unsigned int cnt;
2350
	/* ACLink on, 2 channels */
2351
	cnt = igetdword(chip, ICHREG(GLOB_CNT));
2352
	cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2353
	/* finish cold or do warm reset */
2354
	cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2355
	iputdword(chip, ICHREG(GLOB_CNT), cnt);
2356
	end_time = (jiffies + (HZ / 4)) + 1;
2357
	do {
2358
		if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2359
			return 0;
2360
		schedule_timeout_uninterruptible(1);
2361
	} while (time_after_eq(end_time, jiffies));
2362
	dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2363
		   igetdword(chip, ICHREG(GLOB_CNT)));
2364
	return -EIO;
2365
}
2366

2367
static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2368
{
2369
	unsigned long end_time;
2370
	unsigned int status, nstatus;
2371
	unsigned int cnt;
2372
	int err;
2373

2374
	/* put logic to right state */
2375
	/* first clear status bits */
2376
	status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2377
	if (chip->device_type == DEVICE_NFORCE)
2378
		status |= ICH_NVSPINT;
2379
	cnt = igetdword(chip, ICHREG(GLOB_STA));
2380
	iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2381

2382
	if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2383
		err = snd_intel8x0_ich_chip_cold_reset(chip);
2384
	else
2385
		err = snd_intel8x0_ich_chip_reset(chip);
2386
	if (err < 0)
2387
		return err;
2388

2389
	if (probing) {
2390
		/* wait for any codec ready status.
2391
		 * Once it becomes ready it should remain ready
2392
		 * as long as we do not disable the ac97 link.
2393
		 */
2394
		end_time = jiffies + HZ;
2395
		do {
2396
			status = igetdword(chip, ICHREG(GLOB_STA)) &
2397
				chip->codec_isr_bits;
2398
			if (status)
2399
				break;
2400
			schedule_timeout_uninterruptible(1);
2401
		} while (time_after_eq(end_time, jiffies));
2402
		if (! status) {
2403
			/* no codec is found */
2404
			dev_err(chip->card->dev,
2405
				"codec_ready: codec is not ready [0x%x]\n",
2406
				   igetdword(chip, ICHREG(GLOB_STA)));
2407
			return -EIO;
2408
		}
2409

2410
		/* wait for other codecs ready status. */
2411
		end_time = jiffies + HZ / 4;
2412
		while (status != chip->codec_isr_bits &&
2413
		       time_after_eq(end_time, jiffies)) {
2414
			schedule_timeout_uninterruptible(1);
2415
			status |= igetdword(chip, ICHREG(GLOB_STA)) &
2416
				chip->codec_isr_bits;
2417
		}
2418

2419
	} else {
2420
		/* resume phase */
2421
		int i;
2422
		status = 0;
2423
		for (i = 0; i < chip->ncodecs; i++)
2424
			if (chip->ac97[i])
2425
				status |= chip->codec_bit[chip->ac97_sdin[i]];
2426
		/* wait until all the probed codecs are ready */
2427
		end_time = jiffies + HZ;
2428
		do {
2429
			nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2430
				chip->codec_isr_bits;
2431
			if (status == nstatus)
2432
				break;
2433
			schedule_timeout_uninterruptible(1);
2434
		} while (time_after_eq(end_time, jiffies));
2435
	}
2436

2437
	if (chip->device_type == DEVICE_SIS) {
2438
		/* unmute the output on SIS7012 */
2439
		iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2440
	}
2441
	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2442
		/* enable SPDIF interrupt */
2443
		unsigned int val;
2444
		pci_read_config_dword(chip->pci, 0x4c, &val);
2445
		val |= 0x1000000;
2446
		pci_write_config_dword(chip->pci, 0x4c, val);
2447
	}
2448
      	return 0;
2449
}
2450

2451
static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2452
{
2453
	u32 reg;
2454
	int i = 0;
2455

2456
	reg = igetdword(chip, ICHREG(ALI_SCR));
2457
	if ((reg & 2) == 0)	/* Cold required */
2458
		reg |= 2;
2459
	else
2460
		reg |= 1;	/* Warm */
2461
	reg &= ~0x80000000;	/* ACLink on */
2462
	iputdword(chip, ICHREG(ALI_SCR), reg);
2463

2464
	for (i = 0; i < HZ / 2; i++) {
2465
		if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2466
			goto __ok;
2467
		schedule_timeout_uninterruptible(1);
2468
	}
2469
	dev_err(chip->card->dev, "AC'97 reset failed.\n");
2470
	if (probing)
2471
		return -EIO;
2472

2473
 __ok:
2474
	for (i = 0; i < HZ / 2; i++) {
2475
		reg = igetdword(chip, ICHREG(ALI_RTSR));
2476
		if (reg & 0x80) /* primary codec */
2477
			break;
2478
		iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2479
		schedule_timeout_uninterruptible(1);
2480
	}
2481

2482
	do_ali_reset(chip);
2483
	return 0;
2484
}
2485

2486
static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2487
{
2488
	unsigned int i, timeout;
2489
	int err;
2490
	
2491
	if (chip->device_type != DEVICE_ALI) {
2492
		err = snd_intel8x0_ich_chip_init(chip, probing);
2493
		if (err < 0)
2494
			return err;
2495
		iagetword(chip, 0);	/* clear semaphore flag */
2496
	} else {
2497
		err = snd_intel8x0_ali_chip_init(chip, probing);
2498
		if (err < 0)
2499
			return err;
2500
	}
2501

2502
	/* disable interrupts */
2503
	for (i = 0; i < chip->bdbars_count; i++)
2504
		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2505
	/* reset channels */
2506
	for (i = 0; i < chip->bdbars_count; i++)
2507
		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2508
	for (i = 0; i < chip->bdbars_count; i++) {
2509
	        timeout = 100000;
2510
	        while (--timeout != 0) {
2511
        		if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2512
        		        break;
2513
                }
2514
                if (timeout == 0)
2515
			dev_err(chip->card->dev, "reset of registers failed?\n");
2516
        }
2517
	/* initialize Buffer Descriptor Lists */
2518
	for (i = 0; i < chip->bdbars_count; i++)
2519
		iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2520
			  chip->ichd[i].bdbar_addr);
2521
	return 0;
2522
}
2523

2524
static void snd_intel8x0_free(struct snd_card *card)
2525
{
2526
	struct intel8x0 *chip = card->private_data;
2527
	unsigned int i;
2528

2529
	if (chip->irq < 0)
2530
		goto __hw_end;
2531
	/* disable interrupts */
2532
	for (i = 0; i < chip->bdbars_count; i++)
2533
		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2534
	/* reset channels */
2535
	for (i = 0; i < chip->bdbars_count; i++)
2536
		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2537
	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2538
		/* stop the spdif interrupt */
2539
		unsigned int val;
2540
		pci_read_config_dword(chip->pci, 0x4c, &val);
2541
		val &= ~0x1000000;
2542
		pci_write_config_dword(chip->pci, 0x4c, val);
2543
	}
2544
	/* --- */
2545

2546
      __hw_end:
2547
	if (chip->irq >= 0)
2548
		free_irq(chip->irq, chip);
2549
}
2550

2551
/*
2552
 * power management
2553
 */
2554
static int intel8x0_suspend(struct device *dev)
2555
{
2556
	struct snd_card *card = dev_get_drvdata(dev);
2557
	struct intel8x0 *chip = card->private_data;
2558
	int i;
2559

2560
	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2561
	for (i = 0; i < chip->ncodecs; i++)
2562
		snd_ac97_suspend(chip->ac97[i]);
2563
	if (chip->device_type == DEVICE_INTEL_ICH4)
2564
		chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2565

2566
	if (chip->irq >= 0) {
2567
		free_irq(chip->irq, chip);
2568
		chip->irq = -1;
2569
		card->sync_irq = -1;
2570
	}
2571
	return 0;
2572
}
2573

2574
static int intel8x0_resume(struct device *dev)
2575
{
2576
	struct pci_dev *pci = to_pci_dev(dev);
2577
	struct snd_card *card = dev_get_drvdata(dev);
2578
	struct intel8x0 *chip = card->private_data;
2579
	int i;
2580

2581
	snd_intel8x0_chip_init(chip, 0);
2582
	if (request_irq(pci->irq, snd_intel8x0_interrupt,
2583
			IRQF_SHARED, KBUILD_MODNAME, chip)) {
2584
		dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2585
			pci->irq);
2586
		snd_card_disconnect(card);
2587
		return -EIO;
2588
	}
2589
	chip->irq = pci->irq;
2590
	card->sync_irq = chip->irq;
2591

2592
	/* re-initialize mixer stuff */
2593
	if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2594
		/* enable separate SDINs for ICH4 */
2595
		iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2596
		/* use slot 10/11 for SPDIF */
2597
		iputdword(chip, ICHREG(GLOB_CNT),
2598
			  (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2599
			  ICH_PCM_SPDIF_1011);
2600
	}
2601

2602
	for (i = 0; i < chip->ncodecs; i++)
2603
		snd_ac97_resume(chip->ac97[i]);
2604

2605
	/* resume status */
2606
	for (i = 0; i < chip->bdbars_count; i++) {
2607
		struct ichdev *ichdev = &chip->ichd[i];
2608
		unsigned long port = ichdev->reg_offset;
2609
		if (! ichdev->substream || ! ichdev->suspended)
2610
			continue;
2611
		if (ichdev->ichd == ICHD_PCMOUT)
2612
			snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2613
		iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2614
		iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2615
		iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2616
		iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2617
	}
2618

2619
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2620
	return 0;
2621
}
2622

2623
static DEFINE_SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2624

2625
#define INTEL8X0_TESTBUF_SIZE	32768	/* enough large for one shot */
2626

2627
static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2628
{
2629
	struct snd_pcm_substream *subs;
2630
	struct ichdev *ichdev;
2631
	unsigned long port;
2632
	unsigned long pos, pos1, t;
2633
	int civ, timeout = 1000, attempt = 1;
2634
	ktime_t start_time, stop_time;
2635

2636
	if (chip->ac97_bus->clock != 48000)
2637
		return; /* specified in module option */
2638
	if (chip->inside_vm && !ac97_clock)
2639
		return; /* no measurement on VM */
2640

2641
      __again:
2642
	subs = chip->pcm[0]->streams[0].substream;
2643
	if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2644
		dev_warn(chip->card->dev,
2645
			 "no playback buffer allocated - aborting measure ac97 clock\n");
2646
		return;
2647
	}
2648
	ichdev = &chip->ichd[ICHD_PCMOUT];
2649
	ichdev->physbuf = subs->dma_buffer.addr;
2650
	ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2651
	ichdev->substream = NULL; /* don't process interrupts */
2652

2653
	/* set rate */
2654
	if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2655
		dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2656
			chip->ac97_bus->clock);
2657
		return;
2658
	}
2659
	snd_intel8x0_setup_periods(chip, ichdev);
2660
	port = ichdev->reg_offset;
2661
	scoped_guard(spinlock_irq, &chip->reg_lock) {
2662
		chip->in_measurement = 1;
2663
		/* trigger */
2664
		if (chip->device_type != DEVICE_ALI)
2665
			iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2666
		else {
2667
			iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2668
			iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2669
		}
2670
		start_time = ktime_get();
2671
	}
2672
	msleep(50);
2673
	scoped_guard(spinlock_irq, &chip->reg_lock) {
2674
		/* check the position */
2675
		do {
2676
			civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2677
			pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2678
			if (pos1 == 0) {
2679
				udelay(10);
2680
				continue;
2681
			}
2682
			if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2683
			    pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2684
				break;
2685
		} while (timeout--);
2686
		if (pos1 == 0) {	/* oops, this value is not reliable */
2687
			pos = 0;
2688
		} else {
2689
			pos = ichdev->fragsize1;
2690
			pos -= pos1 << ichdev->pos_shift;
2691
			pos += ichdev->position;
2692
		}
2693
		chip->in_measurement = 0;
2694
		stop_time = ktime_get();
2695
		/* stop */
2696
		if (chip->device_type == DEVICE_ALI) {
2697
			iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2698
			iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2699
			while (igetbyte(chip, port + ICH_REG_OFF_CR))
2700
				;
2701
		} else {
2702
			iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2703
			while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2704
				;
2705
		}
2706
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2707
	}
2708

2709
	if (pos == 0) {
2710
		dev_err(chip->card->dev,
2711
			"measure - unreliable DMA position..\n");
2712
	      __retry:
2713
		if (attempt < 3) {
2714
			msleep(300);
2715
			attempt++;
2716
			goto __again;
2717
		}
2718
		goto __end;
2719
	}
2720

2721
	pos /= 4;
2722
	t = ktime_us_delta(stop_time, start_time);
2723
	dev_info(chip->card->dev,
2724
		 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2725
	if (t == 0) {
2726
		dev_err(chip->card->dev, "?? calculation error..\n");
2727
		goto __retry;
2728
	}
2729
	pos *= 1000;
2730
	pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2731
	if (pos < 40000 || pos >= 60000) {
2732
		/* abnormal value. hw problem? */
2733
		dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2734
		goto __retry;
2735
	} else if (pos > 40500 && pos < 41500)
2736
		/* first exception - 41000Hz reference clock */
2737
		chip->ac97_bus->clock = 41000;
2738
	else if (pos > 43600 && pos < 44600)
2739
		/* second exception - 44100HZ reference clock */
2740
		chip->ac97_bus->clock = 44100;
2741
	else if (pos < 47500 || pos > 48500)
2742
		/* not 48000Hz, tuning the clock.. */
2743
		chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2744
      __end:
2745
	dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2746
	snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2747
}
2748

2749
static const struct snd_pci_quirk intel8x0_clock_list[] = {
2750
	SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2751
	SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2752
	SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2753
	SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2754
	SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2755
	SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2756
	{ }	/* terminator */
2757
};
2758

2759
static int intel8x0_in_clock_list(struct intel8x0 *chip)
2760
{
2761
	struct pci_dev *pci = chip->pci;
2762
	const struct snd_pci_quirk *wl;
2763

2764
	wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2765
	if (!wl)
2766
		return 0;
2767
	dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
2768
	       pci->subsystem_vendor, pci->subsystem_device, wl->value);
2769
	chip->ac97_bus->clock = wl->value;
2770
	return 1;
2771
}
2772

2773
static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2774
				   struct snd_info_buffer *buffer)
2775
{
2776
	struct intel8x0 *chip = entry->private_data;
2777
	unsigned int tmp;
2778

2779
	snd_iprintf(buffer, "Intel8x0\n\n");
2780
	if (chip->device_type == DEVICE_ALI)
2781
		return;
2782
	tmp = igetdword(chip, ICHREG(GLOB_STA));
2783
	snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2784
	snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2785
	if (chip->device_type == DEVICE_INTEL_ICH4)
2786
		snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2787
	snd_iprintf(buffer, "AC'97 codecs ready    :");
2788
	if (tmp & chip->codec_isr_bits) {
2789
		int i;
2790
		static const char *codecs[3] = {
2791
			"primary", "secondary", "tertiary"
2792
		};
2793
		for (i = 0; i < chip->max_codecs; i++)
2794
			if (tmp & chip->codec_bit[i])
2795
				snd_iprintf(buffer, " %s", codecs[i]);
2796
	} else
2797
		snd_iprintf(buffer, " none");
2798
	snd_iprintf(buffer, "\n");
2799
	if (chip->device_type == DEVICE_INTEL_ICH4 ||
2800
	    chip->device_type == DEVICE_SIS)
2801
		snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2802
			chip->ac97_sdin[0],
2803
			chip->ac97_sdin[1],
2804
			chip->ac97_sdin[2]);
2805
}
2806

2807
static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2808
{
2809
	snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2810
			     snd_intel8x0_proc_read);
2811
}
2812

2813
struct ich_reg_info {
2814
	unsigned int int_sta_mask;
2815
	unsigned int offset;
2816
};
2817

2818
static const unsigned int ich_codec_bits[3] = {
2819
	ICH_PCR, ICH_SCR, ICH_TCR
2820
};
2821
static const unsigned int sis_codec_bits[3] = {
2822
	ICH_PCR, ICH_SCR, ICH_SIS_TCR
2823
};
2824

2825
static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2826
{
2827
	int result  = inside_vm;
2828
	char *msg   = NULL;
2829

2830
	/* check module parameter first (override detection) */
2831
	if (result >= 0) {
2832
		msg = result ? "enable (forced) VM" : "disable (forced) VM";
2833
		goto fini;
2834
	}
2835

2836
	/* check for known (emulated) devices */
2837
	result = 0;
2838
	if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2839
	    pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2840
		/* KVM emulated sound, PCI SSID: 1af4:1100 */
2841
		msg = "enable KVM";
2842
		result = 1;
2843
	} else if (pci->subsystem_vendor == 0x1ab8) {
2844
		/* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2845
		msg = "enable Parallels VM";
2846
		result = 1;
2847
	}
2848

2849
fini:
2850
	if (msg != NULL)
2851
		dev_info(&pci->dev, "%s optimization\n", msg);
2852

2853
	return result;
2854
}
2855

2856
static int snd_intel8x0_init(struct snd_card *card,
2857
			     struct pci_dev *pci,
2858
			     unsigned long device_type)
2859
{
2860
	struct intel8x0 *chip = card->private_data;
2861
	int err;
2862
	unsigned int i;
2863
	unsigned int int_sta_masks;
2864
	struct ichdev *ichdev;
2865

2866
	static const unsigned int bdbars[] = {
2867
		3, /* DEVICE_INTEL */
2868
		6, /* DEVICE_INTEL_ICH4 */
2869
		3, /* DEVICE_SIS */
2870
		6, /* DEVICE_ALI */
2871
		4, /* DEVICE_NFORCE */
2872
	};
2873
	static const struct ich_reg_info intel_regs[6] = {
2874
		{ ICH_PIINT, 0 },
2875
		{ ICH_POINT, 0x10 },
2876
		{ ICH_MCINT, 0x20 },
2877
		{ ICH_M2INT, 0x40 },
2878
		{ ICH_P2INT, 0x50 },
2879
		{ ICH_SPINT, 0x60 },
2880
	};
2881
	static const struct ich_reg_info nforce_regs[4] = {
2882
		{ ICH_PIINT, 0 },
2883
		{ ICH_POINT, 0x10 },
2884
		{ ICH_MCINT, 0x20 },
2885
		{ ICH_NVSPINT, 0x70 },
2886
	};
2887
	static const struct ich_reg_info ali_regs[6] = {
2888
		{ ALI_INT_PCMIN, 0x40 },
2889
		{ ALI_INT_PCMOUT, 0x50 },
2890
		{ ALI_INT_MICIN, 0x60 },
2891
		{ ALI_INT_CODECSPDIFOUT, 0x70 },
2892
		{ ALI_INT_SPDIFIN, 0xa0 },
2893
		{ ALI_INT_SPDIFOUT, 0xb0 },
2894
	};
2895
	const struct ich_reg_info *tbl;
2896

2897
	err = pcim_enable_device(pci);
2898
	if (err < 0)
2899
		return err;
2900

2901
	spin_lock_init(&chip->reg_lock);
2902
	chip->device_type = device_type;
2903
	chip->card = card;
2904
	chip->pci = pci;
2905
	chip->irq = -1;
2906

2907
	/* module parameters */
2908
	chip->buggy_irq = buggy_irq;
2909
	chip->buggy_semaphore = buggy_semaphore;
2910
	if (xbox)
2911
		chip->xbox = 1;
2912

2913
	chip->inside_vm = snd_intel8x0_inside_vm(pci);
2914

2915
	/*
2916
	 * Intel 82443MX running a 100MHz processor system bus has a hardware
2917
	 * bug, which aborts PCI busmaster for audio transfer.  A workaround
2918
	 * is to set the pages as non-cached.  For details, see the errata in
2919
	 *     http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2920
	 */
2921
	if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2922
	    pci->device == PCI_DEVICE_ID_INTEL_440MX)
2923
		chip->fix_nocache = 1; /* enable workaround */
2924

2925
	err = pcim_request_all_regions(pci, card->shortname);
2926
	if (err < 0)
2927
		return err;
2928

2929
	if (device_type == DEVICE_ALI) {
2930
		/* ALI5455 has no ac97 region */
2931
		chip->bmaddr = pcim_iomap(pci, 0, 0);
2932
	} else {
2933
		if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2934
			chip->addr = pcim_iomap(pci, 2, 0);
2935
		else
2936
			chip->addr = pcim_iomap(pci, 0, 0);
2937
		if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2938
			chip->bmaddr = pcim_iomap(pci, 3, 0);
2939
		else
2940
			chip->bmaddr = pcim_iomap(pci, 1, 0);
2941
	}
2942

2943
	chip->bdbars_count = bdbars[device_type];
2944

2945
	/* initialize offsets */
2946
	switch (device_type) {
2947
	case DEVICE_NFORCE:
2948
		tbl = nforce_regs;
2949
		break;
2950
	case DEVICE_ALI:
2951
		tbl = ali_regs;
2952
		break;
2953
	default:
2954
		tbl = intel_regs;
2955
		break;
2956
	}
2957
	for (i = 0; i < chip->bdbars_count; i++) {
2958
		ichdev = &chip->ichd[i];
2959
		ichdev->ichd = i;
2960
		ichdev->reg_offset = tbl[i].offset;
2961
		ichdev->int_sta_mask = tbl[i].int_sta_mask;
2962
		if (device_type == DEVICE_SIS) {
2963
			/* SiS 7012 swaps the registers */
2964
			ichdev->roff_sr = ICH_REG_OFF_PICB;
2965
			ichdev->roff_picb = ICH_REG_OFF_SR;
2966
		} else {
2967
			ichdev->roff_sr = ICH_REG_OFF_SR;
2968
			ichdev->roff_picb = ICH_REG_OFF_PICB;
2969
		}
2970
		if (device_type == DEVICE_ALI)
2971
			ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2972
		/* SIS7012 handles the pcm data in bytes, others are in samples */
2973
		ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2974
	}
2975

2976
	/* allocate buffer descriptor lists */
2977
	/* the start of each lists must be aligned to 8 bytes */
2978
	chip->bdbars = snd_devm_alloc_pages(&pci->dev, intel8x0_dma_type(chip),
2979
					    chip->bdbars_count * sizeof(u32) *
2980
					    ICH_MAX_FRAGS * 2);
2981
	if (!chip->bdbars)
2982
		return -ENOMEM;
2983

2984
	/* tables must be aligned to 8 bytes here, but the kernel pages
2985
	   are much bigger, so we don't care (on i386) */
2986
	int_sta_masks = 0;
2987
	for (i = 0; i < chip->bdbars_count; i++) {
2988
		ichdev = &chip->ichd[i];
2989
		ichdev->bdbar = ((__le32 *)chip->bdbars->area) +
2990
			(i * ICH_MAX_FRAGS * 2);
2991
		ichdev->bdbar_addr = chip->bdbars->addr +
2992
			(i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2993
		int_sta_masks |= ichdev->int_sta_mask;
2994
	}
2995
	chip->int_sta_reg = device_type == DEVICE_ALI ?
2996
		ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2997
	chip->int_sta_mask = int_sta_masks;
2998

2999
	pci_set_master(pci);
3000

3001
	switch(chip->device_type) {
3002
	case DEVICE_INTEL_ICH4:
3003
		/* ICH4 can have three codecs */
3004
		chip->max_codecs = 3;
3005
		chip->codec_bit = ich_codec_bits;
3006
		chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3007
		break;
3008
	case DEVICE_SIS:
3009
		/* recent SIS7012 can have three codecs */
3010
		chip->max_codecs = 3;
3011
		chip->codec_bit = sis_codec_bits;
3012
		chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3013
		break;
3014
	default:
3015
		/* others up to two codecs */
3016
		chip->max_codecs = 2;
3017
		chip->codec_bit = ich_codec_bits;
3018
		chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3019
		break;
3020
	}
3021
	for (i = 0; i < chip->max_codecs; i++)
3022
		chip->codec_isr_bits |= chip->codec_bit[i];
3023

3024
	err = snd_intel8x0_chip_init(chip, 1);
3025
	if (err < 0)
3026
		return err;
3027

3028
	/* request irq after initializaing int_sta_mask, etc */
3029
	/* NOTE: we don't use devm version here since it's released /
3030
	 * re-acquired in PM callbacks.
3031
	 * It's released explicitly in snd_intel8x0_free(), too.
3032
	 */
3033
	if (request_irq(pci->irq, snd_intel8x0_interrupt,
3034
			IRQF_SHARED, KBUILD_MODNAME, chip)) {
3035
		dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3036
		return -EBUSY;
3037
	}
3038
	chip->irq = pci->irq;
3039
	card->sync_irq = chip->irq;
3040

3041
	card->private_free = snd_intel8x0_free;
3042

3043
	return 0;
3044
}
3045

3046
static struct shortname_table {
3047
	unsigned int id;
3048
	const char *s;
3049
} shortnames[] = {
3050
	{ PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3051
	{ PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3052
	{ PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3053
	{ PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3054
	{ PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3055
	{ PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3056
	{ PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3057
	{ PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3058
	{ PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3059
	{ PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3060
	{ PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3061
	{ PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3062
	{ PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3063
	{ PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3064
	{ PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3065
	{ PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3066
	{ PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3067
	{ PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3068
	{ 0x003a, "NVidia MCP04" },
3069
	{ 0x746d, "AMD AMD8111" },
3070
	{ 0x7445, "AMD AMD768" },
3071
	{ 0x5455, "ALi M5455" },
3072
	{ 0, NULL },
3073
};
3074

3075
static const struct snd_pci_quirk spdif_aclink_defaults[] = {
3076
	SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3077
	{ } /* end */
3078
};
3079

3080
/* look up allow/deny list for SPDIF over ac-link */
3081
static int check_default_spdif_aclink(struct pci_dev *pci)
3082
{
3083
	const struct snd_pci_quirk *w;
3084

3085
	w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3086
	if (w) {
3087
		if (w->value)
3088
			dev_dbg(&pci->dev,
3089
				"Using SPDIF over AC-Link for %s\n",
3090
				    snd_pci_quirk_name(w));
3091
		else
3092
			dev_dbg(&pci->dev,
3093
				"Using integrated SPDIF DMA for %s\n",
3094
				    snd_pci_quirk_name(w));
3095
		return w->value;
3096
	}
3097
	return 0;
3098
}
3099

3100
static int __snd_intel8x0_probe(struct pci_dev *pci,
3101
				const struct pci_device_id *pci_id)
3102
{
3103
	struct snd_card *card;
3104
	struct intel8x0 *chip;
3105
	int err;
3106
	struct shortname_table *name;
3107

3108
	err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
3109
				sizeof(*chip), &card);
3110
	if (err < 0)
3111
		return err;
3112
	chip = card->private_data;
3113

3114
	if (spdif_aclink < 0)
3115
		spdif_aclink = check_default_spdif_aclink(pci);
3116

3117
	strscpy(card->driver, "ICH");
3118
	if (!spdif_aclink) {
3119
		switch (pci_id->driver_data) {
3120
		case DEVICE_NFORCE:
3121
			strscpy(card->driver, "NFORCE");
3122
			break;
3123
		case DEVICE_INTEL_ICH4:
3124
			strscpy(card->driver, "ICH4");
3125
		}
3126
	}
3127

3128
	strscpy(card->shortname, "Intel ICH");
3129
	for (name = shortnames; name->id; name++) {
3130
		if (pci->device == name->id) {
3131
			strscpy(card->shortname, name->s);
3132
			break;
3133
		}
3134
	}
3135

3136
	if (buggy_irq < 0) {
3137
		/* some Nforce[2] and ICH boards have problems with IRQ handling.
3138
		 * Needs to return IRQ_HANDLED for unknown irqs.
3139
		 */
3140
		if (pci_id->driver_data == DEVICE_NFORCE)
3141
			buggy_irq = 1;
3142
		else
3143
			buggy_irq = 0;
3144
	}
3145

3146
	err = snd_intel8x0_init(card, pci, pci_id->driver_data);
3147
	if (err < 0)
3148
		return err;
3149

3150
	err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk);
3151
	if (err < 0)
3152
		return err;
3153
	err = snd_intel8x0_pcm(chip);
3154
	if (err < 0)
3155
		return err;
3156
	
3157
	snd_intel8x0_proc_init(chip);
3158

3159
	snprintf(card->longname, sizeof(card->longname),
3160
		 "%s with %s at irq %i", card->shortname,
3161
		 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3162

3163
	if (ac97_clock == 0 || ac97_clock == 1) {
3164
		if (ac97_clock == 0) {
3165
			if (intel8x0_in_clock_list(chip) == 0)
3166
				intel8x0_measure_ac97_clock(chip);
3167
		} else {
3168
			intel8x0_measure_ac97_clock(chip);
3169
		}
3170
	}
3171

3172
	err = snd_card_register(card);
3173
	if (err < 0)
3174
		return err;
3175

3176
	pci_set_drvdata(pci, card);
3177
	return 0;
3178
}
3179

3180
static int snd_intel8x0_probe(struct pci_dev *pci,
3181
			      const struct pci_device_id *pci_id)
3182
{
3183
	return snd_card_free_on_error(&pci->dev, __snd_intel8x0_probe(pci, pci_id));
3184
}
3185

3186
static struct pci_driver intel8x0_driver = {
3187
	.name = KBUILD_MODNAME,
3188
	.id_table = snd_intel8x0_ids,
3189
	.probe = snd_intel8x0_probe,
3190
	.driver = {
3191
		.pm = &intel8x0_pm,
3192
	},
3193
};
3194

3195
module_pci_driver(intel8x0_driver);
3196

3197
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