CoCalc -- resample

05. Matplotlib / ffmpeg-3.0 / libavresample / arm / resample_neon.S
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/*
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 * Copyright (c) 2014 Peter Meerwald <[email protected]>
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 *
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 * This file is part of FFmpeg.
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 *
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 * FFmpeg is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2.1 of the License, or (at your option) any later version.
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 *
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 * FFmpeg is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with FFmpeg; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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 */
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#include "libavutil/arm/asm.S"
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#include "asm-offsets.h"
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.macro resample_one     fmt, es=2
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function ff_resample_one_\fmt\()_neon, export=1
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        push            {r4, r5}
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        add             r1, r1, r2, lsl #\es
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        ldr             r2, [r0, #PHASE_SHIFT+4] /* phase_mask */
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        ldr             ip, [sp, #8] /* index */
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        ldr             r5, [r0, #FILTER_LENGTH]
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        and             r2, ip, r2 /* (index & phase_mask) */
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        ldr             r4, [r0, #PHASE_SHIFT]
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        lsr             r4, ip, r4 /* compute sample_index */
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        mul             r2, r2, r5
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        ldr             ip, [r0, #FILTER_BANK]
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        add             r3, r3, r4, lsl #\es /* &src[sample_index] */
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        cmp             r5, #8
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        add             r0, ip, r2, lsl #\es /* filter = &filter_bank[...] */
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        blt             5f
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8:
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        subs            r5, r5, #8
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        LOAD4
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        MUL4
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        LOAD4
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        beq             6f
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        cmp             r5, #8
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        MLA4
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        blt             4f
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        subs            r5, r5, #8
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        LOAD4
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        MLA4
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        b               7b
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6:
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        MLA4
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        STORE
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        pop             {r4, r5}
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        bx              lr
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5:
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        INIT4
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4:      /* remaining filter_length 1 to 7 */
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        cmp             r5, #4
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        blt             2f
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        subs            r5, r5, #4
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        LOAD4
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        MLA4
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        beq             0f
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2:      /* remaining filter_length 1 to 3 */
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        cmp             r5, #2
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        blt             1f
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        subs            r5, r5, #2
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        LOAD2
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        MLA2
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        beq             0f
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1:      /* remaining filter_length 1 */
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        LOAD1
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        MLA1
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0:
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        STORE
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        pop             {r4, r5}
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        bx              lr
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endfunc
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.purgem LOAD1
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.purgem LOAD2
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.purgem LOAD4
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.purgem MLA1
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.purgem MLA2
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.purgem MLA4
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.purgem MUL4
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.purgem INIT4
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.purgem STORE
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.endm
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/* float32 */
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.macro  LOAD1
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        veor.32         d0, d0
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        vld1.32         {d0[0]}, [r0]! /* load filter */
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        vld1.32         {d4[0]}, [r3]! /* load src */
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.endm
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.macro  LOAD2
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        vld1.32         {d0}, [r0]! /* load filter */
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        vld1.32         {d4}, [r3]! /* load src */
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.endm
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.macro  LOAD4
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        vld1.32         {d0,d1}, [r0]! /* load filter */
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        vld1.32         {d4,d5}, [r3]! /* load src */
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.endm
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.macro  MLA1
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        vmla.f32        d16, d0, d4[0]
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.endm
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.macro  MLA2
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        vmla.f32        d16, d0, d4
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.endm
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.macro  MLA4
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        vmla.f32        d16, d0, d4
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        vmla.f32        d17, d1, d5
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.endm
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.macro  MUL4
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        vmul.f32        d16, d0, d4
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        vmul.f32        d17, d1, d5
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.endm
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.macro  INIT4
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        veor.f32        q8, q8
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.endm
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.macro  STORE
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        vpadd.f32       d16, d16, d17
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        vpadd.f32       d16, d16, d16
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        vst1.32         d16[0], [r1]
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.endm
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resample_one flt, 2
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/* s32 */
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.macro  LOAD1
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        veor.32         d0, d0
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        vld1.32         {d0[0]}, [r0]! /* load filter */
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        vld1.32         {d4[0]}, [r3]! /* load src */
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.endm
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.macro  LOAD2
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        vld1.32         {d0}, [r0]! /* load filter */
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        vld1.32         {d4}, [r3]! /* load src */
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.endm
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.macro  LOAD4
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        vld1.32         {d0,d1}, [r0]! /* load filter */
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        vld1.32         {d4,d5}, [r3]! /* load src */
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.endm
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.macro  MLA1
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        vmlal.s32       q8, d0, d4[0]
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.endm
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.macro  MLA2
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        vmlal.s32       q8, d0, d4
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.endm
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.macro  MLA4
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        vmlal.s32       q8, d0, d4
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        vmlal.s32       q9, d1, d5
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.endm
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.macro  MUL4
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        vmull.s32       q8, d0, d4
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        vmull.s32       q9, d1, d5
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.endm
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.macro  INIT4
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        veor.s64        q8, q8
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        veor.s64        q9, q9
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.endm
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.macro  STORE
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        vadd.s64        q8, q8, q9
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        vadd.s64        d16, d16, d17
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        vqrshrn.s64     d16, q8, #30
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        vst1.32         d16[0], [r1]
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.endm
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resample_one s32, 2
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/* s16 */
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.macro  LOAD1
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        veor.16         d0, d0
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        vld1.16         {d0[0]}, [r0]! /* load filter */
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        vld1.16         {d4[0]}, [r3]! /* load src */
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.endm
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.macro  LOAD2
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        veor.16         d0, d0
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        vld1.32         {d0[0]}, [r0]! /* load filter */
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        veor.16         d4, d4
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        vld1.32         {d4[0]}, [r3]! /* load src */
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.endm
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.macro  LOAD4
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        vld1.16         {d0}, [r0]! /* load filter */
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        vld1.16         {d4}, [r3]! /* load src */
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.endm
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.macro  MLA1
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        vmlal.s16       q8, d0, d4[0]
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.endm
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.macro  MLA2
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        vmlal.s16       q8, d0, d4
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.endm
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.macro  MLA4
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        vmlal.s16       q8, d0, d4
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.endm
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.macro  MUL4
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        vmull.s16       q8, d0, d4
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.endm
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.macro  INIT4
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        veor.s32        q8, q8
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.endm
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.macro  STORE
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        vpadd.s32       d16, d16, d17
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        vpadd.s32       d16, d16, d16
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        vqrshrn.s32     d16, q8, #15
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        vst1.16         d16[0], [r1]
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.endm
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resample_one s16, 1
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.macro resample_linear  fmt, es=2
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function ff_resample_linear_\fmt\()_neon, export=1
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        push            {r4, r5}
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        add             r1, r1, r2, lsl #\es
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        ldr             r2, [r0, #PHASE_SHIFT+4] /* phase_mask */
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        ldr             ip, [sp, #8] /* index */
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        ldr             r5, [r0, #FILTER_LENGTH]
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        and             r2, ip, r2 /* (index & phase_mask) */
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        ldr             r4, [r0, #PHASE_SHIFT]
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        lsr             r4, ip, r4 /* compute sample_index */
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        mul             r2, r2, r5
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        ldr             ip, [r0, #FILTER_BANK]
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        add             r3, r3, r4, lsl #\es /* &src[sample_index] */
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        cmp             r5, #8
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        ldr             r4, [r0, #SRC_INCR]
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        add             r0, ip, r2, lsl #\es /* filter = &filter_bank[...] */
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        add             r2, r0, r5, lsl #\es /* filter[... + c->filter_length] */
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        blt             5f
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        subs            r5, r5, #8
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        LOAD4
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        MUL4
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        LOAD4
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        beq             6f
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        cmp             r5, #8
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        MLA4
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        blt             4f
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        subs            r5, r5, #8
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        LOAD4
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        MLA4
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        b               7b
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6:
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        MLA4
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        STORE
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        pop             {r4, r5}
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        bx              lr
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5:
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        INIT4
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4:      /* remaining filter_length 1 to 7 */
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        cmp             r5, #4
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        blt             2f
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        subs            r5, r5, #4
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        LOAD4
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        MLA4
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        beq             0f
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2:      /* remaining filter_length 1 to 3 */
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        cmp             r5, #2
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        blt             1f
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        subs            r5, r5, #2
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        LOAD2
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        MLA2
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        beq             0f
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1:      /* remaining filter_length 1 */
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        LOAD1
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        MLA1
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0:
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        STORE
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        pop             {r4, r5}
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        bx              lr
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endfunc
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.purgem LOAD1
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.purgem LOAD2
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.purgem LOAD4
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.purgem MLA1
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.purgem MLA2
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.purgem MLA4
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.purgem MUL4
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.purgem INIT4
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.purgem STORE
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.endm
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/* float32 linear */
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.macro  LOAD1
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        veor.32         d0, d0
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        veor.32         d2, d2
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        vld1.32         {d0[0]}, [r0]! /* load filter */
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        vld1.32         {d2[0]}, [r2]! /* load filter */
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        vld1.32         {d4[0]}, [r3]! /* load src */
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.endm
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.macro  LOAD2
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        vld1.32         {d0}, [r0]! /* load filter */
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        vld1.32         {d2}, [r2]! /* load filter */
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        vld1.32         {d4}, [r3]! /* load src */
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.endm
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.macro  LOAD4
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        vld1.32         {d0,d1}, [r0]! /* load filter */
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        vld1.32         {d2,d3}, [r2]! /* load filter */
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        vld1.32         {d4,d5}, [r3]! /* load src */
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.endm
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.macro  MLA1
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        vmla.f32        d18, d0, d4[0]
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        vmla.f32        d16, d2, d4[0]
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.endm
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.macro  MLA2
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        vmla.f32        d18, d0, d4
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        vmla.f32        d16, d2, d4
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.endm
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.macro  MLA4
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        vmla.f32        q9, q0, q2
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        vmla.f32        q8, q1, q2
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.endm
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.macro  MUL4
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        vmul.f32        q9, q0, q2
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        vmul.f32        q8, q1, q2
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.endm
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.macro  INIT4
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        veor.f32        q9, q9
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        veor.f32        q8, q8
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.endm
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.macro  STORE
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        vldr            s0, [sp, #12] /* frac */
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        vmov            s1, r4
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        vcvt.f32.s32    d0, d0
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        vsub.f32        q8, q8, q9 /* v2 - val */
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        vpadd.f32       d18, d18, d19
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        vpadd.f32       d16, d16, d17
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        vpadd.f32       d2, d18, d18
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        vpadd.f32       d1, d16, d16
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        vmul.f32        s2, s2, s0 /* (v2 - val) * frac */
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        vdiv.f32        s2, s2, s1 /* / c->src_incr */
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        vadd.f32        s4, s4, s2
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        vstr            s4, [r1]
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.endm
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resample_linear flt, 2
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